JP3098514B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, in particular, an MO for connecting a sense amplifier and a bit line of a DRAM.
It relates to a gate circuit of an S transistor and a power supply.

In recent years, memory cells have been miniaturized due to high integration of DRAMs. As a result, the gate length of a transistor used for a memory cell is also decreasing. For example, about 4 μM is about 0.9 μm, and 16M is about 0.1 μm.
For example, about 5 μm. As a result, the withstand voltage of the transistor also decreases, so that it is necessary to reduce the voltage applied from the memory cell. In addition, by reducing the voltage applied to the memory cells, that is, the voltage amplitude of the bit lines, the power consumed by the memory cell array is also reduced. As a result, the number of bit lines that can be charged and discharged at one time increases with high integration. Inevitably, power consumption can be prevented from increasing.

[0003]

2. Description of the Related Art A connection between a sense amplifier and a bit line is MO.
In most cases, this is done via an S transistor. The purpose of this transistor is mainly the following three.

A resistance component is inserted between the sense amplifier and the bit line by the channel resistance of the transistor to form a bit line capacitance and a CR time constant. To be added to the amplifier and not to burden the operation of the sense amplifier. For this purpose, the transistor may always remain conductive. That is, the gate of the transistor may be connected to the power supply V _CC supplied from the outside.

[0005] Clock control of the gate of the transistor to turn off the transistor when the sense amplifier is operating so that the bit line is not loaded while the sense amplifier is operating. In this case, the gate of the transistor is not directly connected to a power supply, but to a clock generation circuit for controlling the gate. Since this clock controls the gate in synchronization with the RAS clock, the clock generation circuit may be supplied with power from the power supply of the row-related peripheral circuit as a part of the row-related peripheral circuit, or may be directly supplied from the outside. Supply from

In the case of a so-called shared sense amplifier, it is used as an array selection switch. Since the shared sense amplifier uses one sense amplifier in common for two pairs of bit lines, the sense amplifier and the bit lines are connected via transistors (switches). What is necessary is just to make the transistor conductive to the cell array side to be selected and to cut off the other. The relationship between the conducting transistor, the sense amplifier, and the bit line is the same.

In any case, the transistor connecting the sense amplifier and the bit line is not used for the means for defining the voltage to be written to the memory cell, but is used for an array selection switch in the case of a shared sense amplifier. It was only for resistance for formation.

FIG. 6 shows a power distribution structure of a conventional DRAM. The dynamic RAM is divided into a cell array 10, a sense amplifier group 11, and a RAS (Row Addr).
essStrobe) Peripheral circuit 12, CAS (Colu-mm Addres
s Strobe) system peripheral circuit 13, data output system peripheral circuit 14
Becomes the like, the peripheral circuit 14 is generally receives power supply voltage V _CC of 5V, the peripheral circuits 12 and 13 receives the V _cc2 is the voltage of, for example, 4V were made from the V _cc, a sense amplifier group 1
1 is subjected to a voltage V _cc1 of 3.3V, for example made from the V _CC. The gate of the MOS transistor Q _1, Q ₂ ... Q _n for connecting the bit lines and the sense amplifier of the cell array is connected to the power supply V _CC in this embodiment, work Raku as mere resistance.

[0009] When by connecting the gate to V _CC i.e. external power supply, the restoring voltage to the highest voltage, that cells of the bit line becomes V _CC -V _th, the voltage of the memory cell array drops below the supply voltage. Further, the restore voltage obtained in this way tracks the supply voltage and becomes a voltage that always drops by the threshold voltage _Vth from the supply voltage. If the power supply voltage changes, the restore voltage of the bit line changes accordingly. Would. Therefore, putting the transistor between the bit line and the sense amplifier, only things to its gate connected to power supply V _CC is about a memory cell operating voltage 0.
Although the voltage is reduced by 7 V, it is not a means for stably limiting the voltage.

Conventionally, there are two methods for stably limiting the voltage applied to a memory cell.

A voltage (for example, 3.3 V) is generated in the chip from an external supply voltage (for example, 5 V), and this is used as a power supply for all circuits in the chip. This voltage conversion circuit is designed so that a constant voltage can be generated even when the temperature or external supply voltage changes, so even if the memory is miniaturized, the optimum voltage can be generated in accordance with it. It's just good. However, although this method is simple in concept, there are two types of cells, one is that it is necessary to advance the miniaturization at a rapid pitch with the improvement of the integration degree, and the other is a peripheral circuit that does not have a large change in the chip size even if the miniaturization is not so rapid. The applied voltage cannot be different, and the design is not always optimal. Also, in DRAMs where the current consumption changes dynamically, the instantaneous current generated by the operation of some circuits affects other circuits as noise, so the voltage applied to the cell array must be stabilized by the collective on-chip voltage drop method. Is not easy.

A voltage (for example, 4 V) is generated in the chip from an externally supplied voltage (for example, 5 V) and supplied to peripheral circuits. At the same time, another voltage (for example, 3.3 V) generated in the chip is supplied to the sense amplifier to lower the voltage of the cell array with further miniaturization. FIG. 6 shows this example. V _cc1 is 3.3V, V _cc2 is set to 4V. According to this method, since the sense amplifier and the peripheral circuit having a large instantaneous current change can be used as power supplies of different systems, there is an advantage that the sense amplifier does not give noise to other circuits. However, in this method in which the restore voltage of the bit line is limited by the amplitude of the sense amplifier, the lower the voltage is, the smaller the driving force of the sense amplifier to drive the data bus becomes. There is a disadvantage that it becomes. This drawback appears as the same drawback in lowering the voltage.

[0013]

As described above, when the voltage for driving the memory cell array is reduced in accordance with the miniaturization of the cell, if the voltage is reduced at once, the load current becomes DRA.
In M, since the change is particularly severe, it is difficult to stabilize the voltage in the chip. Specifically, the voltage must be controlled by a large transistor capable of driving a large instantaneous current, and the large transistor must be driven by a large amplifier circuit with large power consumption. Accordingly, it is not easy to stabilize the feedback loop of the control circuit. Further, the voltage cannot always be optimized between the cell array and the peripheral circuit. Furthermore, even when the peripheral circuit and the sense amplifier are driven by different voltages generated in the chip, if the amplitude of the sense amplifier is reduced according to the desired voltage of the cell array, there is a problem that the access time becomes longer.

The present invention has been made to improve this point and to enable a constant low voltage to be supplied to a cell array without being affected by a change in load current. On the other hand, a sense amplifier can operate with a relatively large amplitude. An object of the present invention is to make it possible to drive a data bus strongly and not to increase current consumption.

[0015]

As shown in FIG. 1, in the present invention, each bit line of a cell array 10 and a sense amplifier group 1 are arranged.
MOS transistor Q connecting each sense amplifier
_1, Q _2, ... the gate of Q _n, the power supply circuit 15 of the sense amplifier group, separate power circuit is a power supply circuit 16 of the peripheral circuit 17
Drive with

The power supply circuit 17 is a stabilized power supply circuit and outputs a constant voltage. This constant voltage is preferably lower than the voltage finally reached by the sense amplifier after amplification (output terminal voltage). The power supply circuits 15 and 16 may or may not be stabilized power supplies. If the voltage may be _Vcc , the power supply circuits may be simple wiring without any circuit.

In the shared sense amplifier, one sense amplifier group is provided in two cell arrays, and each cell array is selectively connected to the sense amplifier group by MOS transistors. Therefore, the gate drive circuit of this MOS transistor is a logic circuit, and turns on / off the MOS transistors Q ₁ , Q, ₂ ... According to a cell array to be connected, specifically, a row (row, word line) address. For example, the first cell array used is the first half of the Q ₁ to Q _n, when the second cell array and the second half is used, the logic circuit 17A when accessing a first cell array Q ₁ to Q _n
Turn on the first half and turn off the second half (driving the gates that way). Power of at least the last stage in the logic circuit 17A is also present invention, the power supply circuit of the sense amplifier and the peripheral circuit is supplied from a separate chip stabilized power supply circuit to drive the transistors Q ₁ to Q _n at a constant voltage .

This constant voltage is preferably lower than the voltage (output terminal voltage) reached by the sense amplifier after amplification.

As described above, when the gate of the MOS transistor connecting the bit line and the sense amplifier is driven at a constant voltage equal to or lower than the sense amplifier output voltage supplied from the stabilized power supply circuit 17 or the logic circuit 17A, According to the source voltage, the bit line voltage is defined by the constant voltage, becomes a constant value, and is not affected by load current fluctuation.

Since the restore voltage of the memory cell is defined by the constant voltage in accordance with the bit line voltage, the cell array side has a low voltage and a small amplitude to increase the speed, while the sense amplifier side has a large amplitude to strongly control the data bus. It can drive and speed up.

The load of the stabilized power supplies 17 and 17A is a light load only by the gate circuits of the MOS transistors Q _{1 to} Q _n , and the output voltage thereof can be easily stabilized.
Does not require large power consumption.

[0022]

FIG. 3 shows an embodiment of the present invention. Since this example has a shared sense amplifier configuration, it corresponds to FIG. The power supply V _cc in this example is 3.3V, the bit line BL1a, .... and the sense amplifier 11A, MOS transistor Q _1a for connecting ..., logic circuit Q ₁₁ and Q ₁₂ for driving the gate of ..., The power supply voltage V _cc3 of 2.2 is 2.2V. The power supply of the sense amplifier is a constant current source, so its voltage V _cc1 is not constant, but the final voltage after amplification is V _cc
Become closer to The power supply 16 for the peripheral circuit is not shown here. In the drawing, signal lines marked with * represent inverted signal lines.

The resistance R ₁ of the power supply section of the logic circuit 17A, the diode-connected n-channel MOS transistor Q ₁₇ ,
Q ₁₈ and the p-channel MOS transistor Q ₁₉ output a constant voltage of 2.2V. That is, V is applied to the transistors Q ₁₇ and Q ₁₈ .
_th (= 0.6 V), and Q _{19 has} V _th
(= 1V) and a total of 2.2V. Note that V _th = 1 V in Q _{19 is due to} the addition of the substrate bias effect to the threshold value of 0.8 V at the common source. Transistor Q of the 2.2V differential pair Q ₁₁ to Q ₁₅
Applied to the gate _11, the gate of the other transistor Q ₁₂ and the voltage V _cc3 of the feedback circuit (transistors Q ₁₆₎ is applied, the V _CC3 is automatically adjusted to be equal to 2.2V.

The logic of the logic circuit 17A is a CMOS inverter formed by the transistors Q ₁₁ and Q _12, Q ₁₃ and Q _14, the selection signal BTX1 when row address belongs to the left of the cell array 10A is L , BTX2 is turned H, CMOS inverter Q ₁₁ and Q ₁₂ are H (2.
2V) Output, CMOS inverter Q ₁₃ and Q ₁₄ is L (0
V) Output. Therefore, the transistors Q _1a , Q _2a ... are turned on, the transistors Q _1b , Q _2b ... are turned off, and the left cell array is connected to the sense amplifier. Selection signal B
The reverse is true when TX1 is H and BTX2 is L, and the right cell array 10B is connected to the sense amplifier. If the gate voltage of the transistors Q _1a is 2.2 V, the bit lines BL1 _a ,... Are 1.6 V lower than that by V _th = 0.6 V, and are constant voltages lower than the power supply voltage of the sense amplifier. It is.

The power supply voltage for outputting the voltage V _cc3 is extremely light because the load is only the gate circuits of the transistors Q _{1a to} Q _na and Q _{1b to} Q _nb . Therefore, it is easy to output a constant low voltage _Vcc3, and it is not necessary to use a large current element. Further, it is hardly affected by a large current fluctuation due to the operation of the sense amplifier, the output circuit, and the like. As a result, the "1" write level of the memory cell is always stable according to the bit line restore voltage.

The power supply voltage of the sense amplifier group is composed of transistors Q ₁₅ and Q _16, resistors R _2, transistor Q _17. When Q ₁₇ contains a sense enable signal SE is turned on, the resistance R ₂ current flows, Q _15, Q ₁₆ is from a current mirror, resistance to the sense amplifier group in accordance with Q ₁₆ R ₂ and the power supply V _cc A constant current determined by the above flows.

The operation of the sense amplifier is known, and the bit line BL is supplied by the memory cell MC selected by the word line WL.
When the 1 _a is * BL1 _a will than H, the sense amplifier 11A
Transistor Q ₃₃ is turned on, Q ₃₂ are turned off, Q ₃₀ is turned on,
Q ₃₁ is driven to the OFF side, pulled up BL1 _a to V _cc1, * the BL1 _a, is pulled down to ground through the transistor Q ₂₅ ON this time. Although V _cc1 finally rises to V _cc = 3.3 V, transistors Q _1a and Q ₁
The 1 Restricted BL1 _a that can be raised by _2a is.
Up to 6V. L-level side of the * BL1 _a is Q _2a, Q ₃₃
Is pulled down to the ground level.

The transistors Q _{18 to} Q ₂₁ and the resistor R ₃ are circuits that generate a reset voltage, in this example, 0.8 V.
V _th of the p-channel MOS transistors Q ₂₁ and Q ₁₉ is.
8 V, V _{th of} n-channel MOS transistors Q ₂₀ and Q ₁₈
Is 0.6V, where the the gate of Q ₁₈ is given a constant voltage of 1.4V, which in are constant current transistor Q ₁₉
Generates 0.8V. Reset signal RE at reset
Appears, the transistors Q ₂₂ and Q ₂₃ are turned on, the power supply and the ground terminal of the sense amplifier are short-circuited by the transistor Q ₂₃ , and 0.8 V is supplied by the transistor Q ₂₂ . This bit line BL, * BL (subscript 1 _a, 1 _b, etc. will be appropriately omitted) is reset to half of 0.8V amplitude 1.6V. At this time, since the clock SE is L, the sense amplifier power supply (V _cc1 ) circuit does not operate and the transistor Q ₂₅ is off.

The transistors Q ₃₅ and Q ₃₆ are column gates, which are turned on by the outputs CL _{1 to} CL _n to the column decoder, and apply the output of the sense amplifier to the data bus DB. This is at the time of memory reading, but at the time of memory writing, the voltage of the data bus DB is applied to the bit lines BL and * BL.

The transistors Q ₃₈ and Q ₃₉ are connected to the bit line BL,
* BL is a short-circuit line transistor and is turned on by a reset signal RE.

FIG. 4 shows voltage waveforms at various points in FIG. R
When the AS bar clock falls and the chip enters the selected state, the reset clock RE falls, and the BTX BTX2 in this example rises according to the row address. Thereby, the cell array 10A is connected to the sense amplifier on the left side in FIG. 3, and the cell array 10B is disconnected from the sense amplifier on the right side in FIG.

When the word line WL rises and the sense amplifier activation clock SE rises, the sense amplifier amplifies the bit line voltage. N _1, N ₂ at the output terminal of the sense amplifier, the bit lines BL1 _a as shown, varies faster than * BL1 _a. This is because there are transistors Q _1a and Q _2a between the bit line and the sense amplifier, and the bit line capacitance is not directly connected to the sense amplifier due to the channel resistance of these transistors.

[0033] out the column selection signal CL ₁ when the voltage of the output terminal of the sense amplifier becomes large to some extent transistors Q _35, Q ₃₆ are turned on, thereby the data bus DB
Is connected to the sense amplifier. The H level rises to near _Vcc while the sense amplifier is also driving the data bus. The H-level side BL1 _a bit line is close in transistor Q _1a 1.6V because starts off, does not rise to more than 1.6V. Thus, the restore voltage of the bit line is limited to 1.6V. When the transistor _Q1a is turned off, the bit line does not become a load when viewed from the sense amplifier side, and the amplification operation speeds up. However, almost at this time, since the data bus is connected to the sense amplifier, this becomes a load on the sense amplifier. Since the output of the sense amplifier eventually rises to near _Vcc , the data bus is driven strongly and the access speed is increased.

[0034] S _ap in FIG 4, S _an, the sense amplifier power high, indicating the low potential side. ΔV is the transistor Q _1a.
(Difference voltage) for driving the sense amplifier to a voltage higher than or equal to the gate voltage.

As described above, the restore voltage of the bit line is defined by limiting the voltage at the gate of the transistor connecting the bit line and the sense amplifier, and the sense amplifier is driven at a higher voltage to increase the access speed. The power consumption of the array can be reduced while measuring the power consumption.

FIG. 5 shows another embodiment of the present invention. The basic configuration is the same as FIG. 3, the transistor Q ₄₁ to Q ₄₄ that connects the read-only bit line data bus provided, the bit lines during the read operation are prevented from being connected directly to the data bus DB. That is, the bit line is connected to Q ₄₁ ,
Receiving at the gate of Q _42, it reads the data of the transistor as a buffer. The selection of the column is performed by driving the transistors Q ₄₃ and Q ₄₄ with the selection signal CL ₁ R.
As a result, since the sense amplifier does not have the data bus line as a load capacitance, the speed of the amplification operation is further increased.

Data writing is performed in the same manner as in the prior art by driving the transistors Q ₃₅ and Q ₃₆ with the selection signal CL ₁ . The transistor Q ₄₅ , so that the wiring of the write gate portion does not become an unnecessary load capacitance at the time of reading.
The gate of Q ₄₆ is controlled by the clock BS, during a read operation disconnects the wire of this part.

The connection between the bit line and the data bus via the transistor has been separately proposed by the present inventors. In the present invention, the gate of the MOS transistor connecting the bit line and the sense amplifier of such a storage device is driven by the output voltage of the stabilized logic circuit 17A.

[0039]

As described above, according to the present invention, the maximum voltage on the bit line is defined by the gate voltage of the transistor connecting the bit line and the sense amplifier. Can work with As a result, by operating the sense amplifier at a voltage higher than the voltage applied to the memory cell, the data bus can be strongly driven, and the access can be speeded up. Furthermore, the in-chip stabilized power supply circuit that defines the gate voltage of this transistor is:
Since it has only a gate as a load and does not need to cover a large current consumption, there is an advantage that a small-sized one with low current consumption in a steady state can be used.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a principle diagram of the present invention.

FIG. 3 is a circuit diagram showing an embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of FIG. 3;

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

Q ₁ to Q _n: MOS transistors 17: stabilized power supply circuit 17A: logic circuit 11: a sense amplifier 15, 16: power supply means

Claims (10)

(57) [Claims] 1. A MOS transistor for connecting a bit line connected to a memory cell to a sense amplifier, a stabilized power supply circuit in a chip for supplying a gate voltage to a gate of the MOS transistor, and a reset voltage generation for generating a reset voltage A sense amplifier reset means for supplying the reset voltage to a power supply terminal of the sense amplifier in response to a reset signal; and a bit line provided on the memory cell side of the MOS transistor, in response to the reset signal. A semiconductor memory device having bit line reset means for resetting a level of the memory cell, wherein a restore voltage to the memory cell is defined by a gate voltage of the MOS transistor. 2. The semiconductor memory device according to claim 1, wherein said reset voltage is equal to a reset level of said bit line. 3. The semiconductor memory device according to claim 1, wherein said on-chip stabilized power supply circuit outputs a constant voltage lower than a voltage finally reached by said sense amplifier after amplification. 4. A logic circuit comprising: a MOS transistor connecting a bit line connected to a memory cell to a sense amplifier; and a logic circuit for selectively driving a gate of the MOS transistor in accordance with an address. The power supply of the stage is supplied from an in-chip stabilized power supply circuit different from the power supply means to the sense amplifier, and a restore voltage to the memory cell is defined by a gate voltage of the MOS transistor. Semiconductor storage device. 5. The semiconductor memory device according to claim 4, wherein at least the last stage of said logic circuit outputs a constant voltage lower than a voltage finally reached after said sense amplifier amplifies. 6. A logic circuit according to claim 4, wherein said power supply means for said sense amplifier is a constant current source, and said logic circuit outputs a constant voltage lower than a voltage finally reached by said sense amplifier after amplification. A stabilized power supply section,
A semiconductor memory device comprising a CMOS inverter driven by a part of the address to supply the constant voltage or the ground potential output from the stabilized power supply unit to the gate of the MOS transistor. 7. A bit line, a memory cell connected to the bit line, a sense amplifier, first means for applying a first voltage as an operation power supply voltage to the sense amplifier, the sense amplifier and the bit M connected between the wire
An OS transistor; a second means having a stabilized power supply circuit for applying a stabilized second voltage lower than the first voltage to a gate electrode of the MOS transistor during a restore operation to the memory cell; A reset voltage generating circuit, a third means for supplying the reset voltage to a power supply terminal of the sense amplifier in response to a reset signal, a third means provided on the memory cell side of the MOS transistor, And a bit line reset means for resetting the level of the bit line. 8. A first bit line connected to a first memory cell, a second bit line connected to a second memory cell, a sense amplifier, the first bit line and the sense. A first MOS transistor provided between the sense amplifier and a second MOS transistor provided between the second bit line and the sense amplifier; a first MOS transistor provided between the second bit line and the sense amplifier; First means for applying one voltage, a stabilized power supply circuit for outputting a stabilized second voltage lower than the first voltage, and gates of the first and second MOS transistors in response to an address signal A second means for selectively applying the second voltage to one of the electrodes. 9. The stabilized power supply circuit according to claim 7, further comprising: a step-down element for stepping down an external power supply voltage to generate the second voltage, wherein the step-down element is connected to the second voltage and a reference voltage. A semiconductor memory device controlled in response to a result of comparison with a voltage. 10. A reset voltage generating circuit for generating a reset voltage, a first reset means for supplying said reset voltage to a power supply terminal of said sense amplifier in response to a reset signal, A second reset means for resetting the first bit line; and a third reset means for resetting the second bit line, wherein the reset level of the first and second bit lines is A semiconductor memory device characterized by being equal to a voltage.