JP3098786B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to improvement of electrical characteristics of a semiconductor integrated circuit device having an SRAM.

[0002]

2. Description of the Related Art DRAM (Dynamic RAM), SR
A memory LSI such as an AM (static RAM) has a memory array in which a large number of memory cells are arranged in a matrix on a main surface of a semiconductor chip.

Conventionally, it has been pointed out that a memory cell arranged at the end of the memory array tends to have a reduced power margin as compared with a memory cell arranged inside the memory array.

This will be described with reference to an SRAM memory array (MA) shown in FIG.

In this memory array (MA), diffusion layers 4 of MOSFETs constituting a memory cell of an SRAM are arranged in a matrix, and an insulating film 6 for element isolation is provided between the diffusion layers 4. Is provided. A gate electrode 7 of a MOSFET is arranged on each of the diffusion layers 4. On the other hand, a guard ring (G) for power supply is provided outside the memory array (MA).
It is provided so as to surround the periphery of A).

Therefore, focusing on the diffusion layer 4 of the MOSFET, the diffusion layer 4 disposed inside the memory array (MA) is surrounded by another diffusion layer 4 while the memory array (MA) is surrounded by the other diffusion layer 4. The diffusion layer 4a disposed at the end of the memory array (MA) has a different shape from the diffusion layer 4 inside the memory array (MA) because the guard ring (G) is opposed to one side thereof.

As a result, the surface tension of the photoresist applied on the semiconductor wafer in the lithography process is different between the inside and the end of the memory array (MA). Since the processing dimensions of the diffusion layer 4a differ from those of the internal diffusion layer 4, it is considered that the electrical characteristics of the transistor at the end deteriorate.

The same applies to the gate electrode 7 disposed on the diffusion layer 4. This is because four gate electrodes 7 are arranged on the diffusion layer 4 inside the memory array (MA), whereas on the diffusion layer 4a at the end of the memory array (MA), This is because only two gate electrodes 7 exist.

Conventionally, as a countermeasure to solve such a problem, dummy cells which do not operate as memory cells are arranged around the memory array, so that the shape of the diffusion layer and the arrangement of the gate electrodes are changed in all the memory arrays. The same method was used. The technology for arranging such dummy cells in an SRAM is disclosed in
It is described in Japanese Patent Application Laid-Open No. 1-215559.

[0010]

However, the prior art in which dummy cells are arranged around the memory array has a problem that the area of the memory array is increased. In particular, in a large-capacity memory LSI, a memory array is divided into a large number of memory mats in order to prevent a wiring delay of a circuit accompanying a large-capacity memory. Therefore, when dummy cells are arranged around each memory mat. In addition, the occupation ratio of the dummy cell to the total area of the memory mat increases, and the area of the semiconductor chip increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to increase the size of a transistor arranged at the end of a memory array (or memory mat) without increasing the chip area. It is an object of the present invention to provide a technique capable of preventing deterioration of electric characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

A semiconductor integrated circuit device according to the present invention has a memory array or memory mat in which a plurality of SRAM memory cells are arranged in a matrix on a main surface of a semiconductor chip. On the surface, the S
An element isolation insulating film having a repetitive pattern for partitioning a RAM memory cell, and a guard ring composed of a semiconductor region arranged so as to surround the memory array or the memory mat; and forming the memory array of the guard ring. Or the shape of the area facing the memory mat is
Including the shape of the repeating pattern of the element isolation insulating film, a dummy pattern electrically connected to the guard ring is formed above the guard ring, and the memory array or the memory of the dummy pattern is formed. The shape of the region facing the mat is configured to be substantially equal to the shape of the gate electrode of the MOSFET constituting the memory cell.

[0014]

[0015]

According to the above-mentioned means, the shape of the memory cell arranged inside the memory array (or memory mat) is substantially equal to the shape of the memory cell arranged at the end. Variations in the processing dimensions of the transistors forming the memory cells at the ends of the (or memory mat) are prevented.

According to the above means, unlike the prior art in which dummy cells are arranged around the memory array (or memory mat), only the shape inside the guard ring is changed. Does not increase.

[0017]

As shown in FIG. 3, for example, at the center of the main surface of a semiconductor chip 1 made of n-type silicon
An SRAM memory array (MA) having a large capacity of megabits (Mbit) is formed. In this SRAM, a memory array (MA) is divided into a large number of memory mats (MM) in order to prevent a wiring delay of a circuit accompanying an increase in capacity.

Peripheral circuits 2 are arranged outside the memory array (MA) along the long side direction of the chip 1, and further outside, bonding pads for making an electrical connection with the outside. 3 are arranged.

FIG. 1 is an enlarged view of a corner portion (a region surrounded by a broken line A in FIG. 3) of the memory mat (MM), and FIG.
FIG. 2 is a sectional view of the chip 1 taken along line II-II in FIG.

The memory mat (MM) has an SRAM
N-channel MOSFET (Q) constituting the memory cell of FIG.
Are arranged in a matrix. As shown in FIG. 1, the memory mats (M
The shape of the diffusion layer 4a arranged at the end of M) is a shape obtained by dividing the diffusion layer 4 inside the memory mat (MM) into two. In addition, as shown in FIG.
It comprises an n-type semiconductor region formed on the main surface of the well 5.

The respective diffusion layers 4 are separated from each other by an element isolation insulating film 6 made of, for example, silicon oxide. A gate electrode 7 of an n-channel MOSFET (Q) is provided on each of the diffusion layers 4. This gate electrode 7 is made of, for example, polycrystalline silicon. As shown in FIG. 1, four gate electrodes 7 are arranged on the diffusion layer 4 inside the memory mat (MM), and two gate electrodes 7 are formed on the diffusion layer 4a at the end. Is arranged.

Outside the memory mat (MM), a guard ring (G) for supplying a power supply unit (V _SS ) to, for example, the P-type well 5 is provided. As shown in FIG. 2, the guard ring (G) is formed of a p ^{+ -type} semiconductor region formed on the main surface of the p-type well 5, and is arranged so as to surround the periphery of the memory mat (MM).

As shown in FIG. 1, the guard ring (G) of this embodiment has a memory mat (MM) having an inner shape.
Is substantially equal to the shape of the diffusion layer 4a at the end of the above. Therefore, the combined shape of the shape of the diffusion layer 4a and the shape inside the guard ring (G) adjacent thereto is substantially equal to the shape of the diffusion layer 4 inside the memory mat (MM).

As shown in FIG. 1, a dummy pattern 8 is provided on the guard ring (G). The dummy pattern 8 is arranged so as to surround the memory mat (MM) along the guard ring (G). The dummy pattern 8 is made of, for example, the same material (polycrystalline silicon or the like) as the gate electrode 7 and is formed simultaneously in the same step as the gate electrode 7.

The inside shape of the dummy pattern 8 is substantially equal to the shape of the gate electrode 7 provided on the diffusion layer 4a at the end of the memory mat (MM). Therefore, the shape obtained by combining the shape of the two gate electrodes 7 on the diffusion layer 4a with the shape inside the dummy pattern 8 adjacent to the gate electrode 7 is the same as the shape provided on the diffusion layer 4 inside the memory mat (MM). The shape is substantially equal to the shape of the two gate electrodes 7.

In order to prevent the dummy pattern 8 from becoming an active transistor, a lower guard ring (C) is formed through a contact hole (C) formed in an insulating layer (not shown) on the guard ring (G). G). The contact hole (C) opened on the diffusion layer 4 of the memory mat (MM) is for transmitting the node potential of the memory cell to a wiring layer (not shown).

According to the SRAM of the present embodiment having the above configuration, the following operations and effects can be obtained.

(1) The inner shape of the guard ring (G) is
Since the shape of the diffusion layer 4a at the end of the memory mat (MM) is substantially equal to the shape of the diffusion layer 4a and the shape inside the guard ring (G) adjacent thereto, the shape of the memory mat (MM) is changed. ) Is substantially equal to the shape of the diffusion layer 4 inside.

(2) The shape of the inside of the dummy pattern 8 is made substantially equal to the shape of the gate electrode 7 provided on the diffusion layer 4a at the end of the memory mat (MM). The shape obtained by combining the shape of the gate electrode 7 and the shape inside the dummy pattern 8 adjacent thereto becomes substantially equal to the shape of the gate electrode 7 provided on the diffusion layer 4 inside the memory mat (MM).

(3) According to the above (1) and (2), the shape of the memory cell arranged inside the memory mat (MM)
The shape of the memory cell arranged at the end becomes substantially equal, thereby preventing the processing dimensions of the diffusion layer 4 and the gate electrode 7 from being varied between the inside of the memory array (MA) and the end. Therefore, it is possible to prevent the deterioration of the electrical characteristics of the MOSFET constituting the memory cell at the end of the memory array (MA).

(4) Unlike the prior art in which dummy cells are arranged around the memory array, only the shape inside the guard ring (G) is changed, so that the area of the memory mat (MM) does not increase. Absent.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

In the above embodiment, an SRAM in which a memory array is divided into a large number of memory mats has been described. However, the present invention is not limited to this. A memory array in which memory cells are arranged in a matrix or a memory LSI having a memory mat Can be applied generally.

[0034]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, it is possible to prevent the deterioration of the electrical characteristics of the transistors arranged at the end of the memory array (or memory mat) without increasing the area of the chip.

[Brief description of the drawings]

FIG. 1 is an enlarged plan view showing a part of a memory mat of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor chip taken along line II-II in FIG.

FIG. 3 is an overall plan view of a semiconductor chip on which the semiconductor integrated circuit device is formed.

FIG. 4 is an enlarged plan view showing a part of a conventional memory array.

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 peripheral circuit 3 bonding pad 4 diffusion layer 4a diffusion layer 5 p-type well 6 element isolation insulating film 7 gate electrode 8 dummy pattern A broken line C contact hole G guard ring MA memory array MM memory mat Q n-channel MOSFET

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuyuki Moriwaki 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Musashi Plant, Hitachi, Ltd. (72) Inventor Shuji Ikeda 5-chome, Josuihoncho, Kodaira-shi, Tokyo No. 20-1 Inside the Musashi Factory, Hitachi, Ltd. (72) Inventor Hideaki Nakamura 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra-LSI Engineering Co., Ltd. (72) Inventor Shigeru Honjo 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (56) References JP-A-60-140662 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8244 H01L 27/11

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit device having a memory array or memory mat in which a plurality of SRAM memory cells are arranged in a matrix on a main surface of a semiconductor chip,
On a main surface of the semiconductor chip, an element isolation insulating film having a repetitive pattern for partitioning the SRAM memory cell, and a guard ring composed of a semiconductor region arranged so as to surround the memory array or memory mat are formed. and, the shape of the region facing the memory array or memory mats of the guard ring, viewed including the shape of the repeated pattern of the element isolation insulating film, the guard
The upper part of the ring is electrically connected to the guard ring.
Dummy pattern is formed, and the dummy pattern
Area facing the memory array or memory mat
The shape of the region is determined by the MOSFET of the memory cell
It characterized <br/> be configured to be substantially equal to the shape of the gate electrode semiconductors integrated circuit device. 2. The semiconductor device according to claim 1, wherein the dummy pattern is made of the same material as the gate electrode.
2. The semiconductor integrated circuit device according to 1.