JP3098796B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as an IC) having a protection diode connected between a semiconductor substrate and an external terminal.

[0002]

2. Description of the Related Art In order to protect an internal circuit connected to an external terminal of an IC, a diode is conventionally provided between an external terminal such as an input terminal and a substrate potential point.
You. This converts the voltage input to its external terminals
To protect the internal circuit elements from static electricity.
You are.

An example of a configuration of a protection circuit in a general IC will be described with reference to a sectional view of a main part in FIG. 5 and a plan view in FIG.

[0005] As shown in FIG. 5, an N-type epitaxial layer 2 formed on a P-type semiconductor substrate 1 has a P-type structure so as to reach the semiconductor substrate 1 from the main surface side of the N-type epitaxial layer 2.
The mold separation region 3 is formed. Then, on the periphery of the IC substrate 4 including the semiconductor substrate 1 and the N-type epitaxial layer 2,
As shown in FIG. 6, the wiring 6 for the substrate potential is provided. Further, a substrate potential contact portion 7 is provided in the region of the substrate potential wiring 6, and as shown in FIG.
Is connected to the P-type isolation region 3. An external lead terminal (not shown) of the IC is connected to the pad 8 using a thin metal wire, and the diode contact 9 is connected to the pad 8.

The diode contact portion 9 forms a diode with the P-type isolation region 3 and the island 10 in the N-type epitaxial layer 2 which is junction-isolated by the P-type isolation region 3.
It should be noted that a high concentration of N in the island 10 of the N-type epitaxial layer 2
Impurity diffusion layer 11 and high-concentration P
The type impurity diffusion region 20 is for reducing the contact resistance between the wiring material and the diffusion layer.

[0006] In its, the P-type semiconductor substrate 1 or P-type isolation region 3 anode - and de, the islands 10 in the N-type epitaxial layer 2 cathode - protective diode and de - the de, point substrate potential and the Connect to each pad.

In such an IC, when a negative surge voltage such as static electricity is applied between the pad 8 and the semiconductor substrate 1, the protection diode 12 conducts in the forward direction and the pad 8
Is limited by the forward voltage of the protection diode 12. Thereby, the circuit element 14 is protected from destruction by static electricity.

[0008]

In the above-mentioned conventional surge protection circuit, as shown in an equivalent circuit diagram of FIG. 7, an N-type is provided between the pad 8 and the substrate potential wiring 6, which is normally a ground point. The protection diode 12 formed by the island 10 of the epitaxial layer and the P-type isolation region 3 is connected. An ohmic resistor 13 is interposed between the PN junction formed by the island 10 and the P-type isolation region 3 and the contact portion 7 for substrate potential.

The resistance of the ohmic resistor 13 is substantially proportional to the distance d between the contact portion 9 for the diode and the contact portion 7 for the substrate potential, and the value decreases as the distance decreases. When the resistance value is reduced, when a negative voltage is applied to the pad 8 with respect to the ground point, an excessive current flows through the protection diode, and the protection diode itself is destroyed by Joule heat.

The present invention has solved the conventional disadvantages.
It is an object of the present invention to provide a semiconductor integrated circuit device in which a protection diode is not damaged by an excessive current even when static electricity is applied to an external terminal or pad of C.

[0011]

In order to achieve this object, a semiconductor integrated circuit device according to the present invention comprises a plurality of pads which are spaced apart from and about 30 μm apart from a wiring for substrate potential at the periphery of a semiconductor substrate. A plurality of protection diodes which are arranged and are separated by PN junction between the substrate potential wiring and the pad.
Arrange islands on the island, and die formed on each island
The substrate potential contact portion is divided into a plurality of portions so as to sandwich one of the ode contact portions, and the substrate potential contact portion is excluded from a portion of the substrate potential wiring opposed to the diode contact portion , The diode capacitor
The distance between the tact portion and the contact portion for substrate potential is 50
μm or more .

[0012]

According to the above arrangement, the diode contact portion of the protection diode is disposed between the substrate potential wiring and the pad separated by about 30 μm therefrom .
The contact portion for the substrate potential is divided so as to sandwich the contact portion, and the contact portion for the substrate potential is excluded from the portion of the wiring for the substrate potential opposite to the contact portion for the diode , so that the blank area around the pad is effectively utilized. Thus, the degree of integration of the IC can be increased. Further, after reducing the separation distance between the substrate potential wiring and the pad, the separation distance between the substrate potential contact portion and the diode contact portion is set to (50).
(μm or more) can be made sufficiently large to increase the value of the ohmic resistance formed in the P-type isolation region . Therefore , the current when a surge voltage is applied to the external terminal of the IC can be suppressed, and the protection diode can be prevented from being destroyed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of one embodiment of the present invention.
Since the cross-sectional structure of the main part is substantially the same as the structure shown in FIG. 5, the corresponding components are denoted by the same reference numerals.

As shown in FIG. 5, first, an N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1, and a P-type isolation region 3 is formed from the main surface thereof so as to reach the surface of the semiconductor substrate 1. Thus, an N-type epitaxial island 10 is formed.
Then, as shown in FIG. 1, a wiring 6 for substrate potential is provided on the insulating film 5 on the main surface of the IC substrate 4 so as to be located at a peripheral portion of the IC substrate 4. The diode contact 9 of the protection diode connected to each pad and the substrate potential contacts 7-1 and 7 in the region of the substrate potential wiring 6.
−2, 7-3, 7-4 at least 50
Provide a distance of μm.

Further, a wiring 6 for substrate potential is connected to the P-type isolation region 3, and an external lead terminal (not shown) of the IC is connected to the pad 8 by a metal wiring. Thus, the protection diode is connected to the IC internal circuit element 14 connected to the pad 8 and the external lead terminal.

FIG. 2 shows an equivalent circuit for evaluating the surge withstand voltage of the IC. The capacitor 16 is charged by the DC voltage source 17 by turning on the switch means 15 to the a contact side. After charging, the switch means 15 is switched to the contact b to supply the electric charge accumulated in the capacitor 16 through the external lead terminal 19 of the IC. With this, IC
Then, the surge withstand voltage is evaluated at a voltage level at which the internal circuit of the IC is damaged.

The evaluation of the damage of the IC is performed by applying a surge voltage to the IC and then evaluating the DC characteristics and the AC characteristics.
The surge withstand voltage of the IC is determined based on whether or not the characteristics have deteriorated.

Under the condition that the IC is left unattended, assuming that the electrostatic energy to be charged is constant, the voltage to be charged differs depending on the capacitance value to be charged. The voltage charged on the capacitor C ₁ and V _1, are represented the voltage charged on the capacitor C ₂ in relation of _{V 1 = V 2 · C 1} / C 2 When V _2.

[0020] Under environmental conditions where static electricity affects the IC, the frequency of damage to the IC due to contact with the human body is high.
Therefore, evaluations targeting the human body are generally performed. The equivalent capacitance C ₀ between the human body and ground is 200 pF
In addition , an electric charge is charged to C ₀ = 200 pF , and an electrostatic withstand test of the IC is performed.

As a criterion for surge withstand, empirically, 20
250 V or more at 0 pF, 350 V at 100 pF
It is said that if the breakdown voltage is as described above, it can withstand practical use.

The breakdown voltage of an IC is generally lower than a surge voltage applied from the outside. Therefore, as means for protecting the internal circuit of the IC, means for clamping the input voltage with the breakdown voltage or forward diode voltage of the device is used. Then, a charge discharge path is formed with a small voltage drop, and the input voltage is limited to protect the IC.

However, there is a danger that Joule heat is generated by the discharge current flowing when discharging the electric charge, the PN junction is damaged, and the protection circuit itself is damaged.

FIG. 3 shows the relationship between the linear distance d between the contact portion 9 for the diode and the contact portion 7 for the substrate potential, and the withstand voltage of the protection diode against the surge voltage.

When the capacitance C ₀ is 100 pF,
The surge resistance is different from the case of 0 pF, and 200 pF.
The value of F is lower.

[0026] Protection against electrostatic diode - from the perspective of protecting the de, if capacitance C ₀ of 250V at 200pF is a diode contact portion 9 and the substrate potential contact portion 7 closer than 50 [mu] m, the capacity C ₀ is 200
When the pF is 350 V, it is preferable that the distance be 80 μm or more.
However, it is necessary to determine the surge withstand capability of the IC based on the surge withstand capability when the internal circuit and the protection diode are both connected to the input terminal of the IC.

FIG. 4 shows the surge withstand capability of the IC when a protection diode is incorporated in the input terminal of the IC and the diode.
The relationship with the distance d between the contact part 9 for substrate and the contact part 7 for substrate potential is shown.

This is because the specific resistance of the semiconductor substrate is 10Ωc.
m, a relationship obtained by conducting an experiment under the condition that the capacitor C ₀ is 200 pF using a sample in which the sheet resistance of the separation / diffusion region is 10 Ωsq. In this case, it can be said that the maximum value of the distance d between the diode contact portion 9 of the protection diode and the substrate potential contact portion 7 is around 400 μm.

It can be said from FIG. 4 that the contact portion 7 for the substrate potential and the contact for the diode of the protection diode are provided.
When the distance between the isolation portions 9 to lengthen the protective diode - O intervening de 12 series - the value of Mick resistor 13 increases, the protection diode - de 12 Sa - but di strength is enhanced, the input voltage It is presumed that the function of clamping decreases and the function of protecting the element 14 of the internal circuit of the IC decreases.

Further, the substrate potential contact portion 7 protection diode - The longer the distance between the de diode contact portion 9, although yield strength is increased, the degree of integration of IC becomes low. Conversely, when the distance is shortened, although the proof strength is reduced, the degree of integration of the IC can be increased.

Incidentally, the cause of the change in surge resistance is not only this, but the resistance value also changes due to the mask pattern around the protection diode, and the surge resistance also changes. On the other hand, fixing a circuit to be integrated loses the degree of freedom in mask design and is almost impossible.

Further, the electronic device IC is applied, the required service - di yield strength slightly different. The combined consider these matters may be appropriately setting the position of the protection diode according to the application of the IC.

The present invention relates to a protection diode for a diode .
By setting the distance d between the contact portion 9 and the contact portion 7 for substrate potential to 50 μm or more, a sufficiently large ohmic resistance is interposed in series with the protection diode to limit the current, and the protection diode is provided. -To increase the surge resistance of the blade.

Next, a second embodiment of the present invention will be described.

In order to enhance the surge withstand capability of the pad 8, which is the input terminal of the IC, a diode for the protection diode is used.
Assume that contact portion 9 and substrate potential contact portion 7 are sufficiently separated from each other. Then, the protection diode diode core
The connection between the contact section 9 and the pad 8 (the input terminal or the output terminal of the IC) becomes an obstacle in arranging the circuit connection arranged around the pad 8. Therefore, if the wiring of the peripheral circuit is to be bypassed, the degree of integration of the entire IC is reduced.

An object of the second embodiment of the present invention is to provide a means for limiting an overcurrent when discharging static electricity by interposing a resistor in series with a protection diode without deteriorating the integration degree of an IC. To provide.

That is, in this embodiment, as shown in FIG. 1, the wiring 6 for the substrate potential formed on the IC substrate 4 and the wiring 6 for the substrate potential are brought into electrical contact with the IC substrate (semiconductor substrate) 4. A plurality of substrate potential contact portions 7-1 and 7-
2, 7-3, 7-4, a plurality of pads arranged along the substrate potential wiring 6, and a plurality of IC terminals (pads 8) formed on the main surface of the semiconductor substrate 4 and electrically connected to each of the plurality of IC terminals (pads 8). and a plurality of diodes contact portions 9 connected to a plurality of substrate potential contact portion 7-1,7-2,7-
3, 7-4 and the contact portion 9 for the diode are 50 μm
It separated above, substrate potential wirings 6 are arranged in the peripheral portion of the semiconductor substrate 4, a substrate potential contact portion by excluding the portion facing the diode contact portion 9 7-1,7-2,7
-3 and 7-4 are divided and arranged.

In such a structure, the distance between the substrate potential wiring 6 and the pad 8 in the periphery of the IC chip is determined by masking.
The distance d between the diode contact portion 9 and the substrate potential contact portion (7-1, 7-2) can be sufficiently ensured while approaching the minimum allowable dimension (about 30 μm). Therefore, circuit arrangement and wiring around the pad 8 are facilitated. In other words, there is an effect that the integration degree of the IC does not decrease by adding the protection circuit.

The distance between the pad 8 and the wiring 6 for the substrate potential and the distance between the wiring for the peripheral circuit and the wiring for the peripheral circuit are determined by the assembling accuracy of the wire-bonding process, but a margin of about 30 μm is required. On the other hand, the diode contact 9
If there is a margin having a width of about 30 μm, the diode contact portion 9 can be accommodated in the margin.

Therefore, when the contact portion 9 for diode is accommodated between the pad 8 and the wiring 6 for the substrate potential at the periphery of the IC chip, the connection between the protection diode and the pad 8 is arranged at the periphery of the pad 8. Since it does not hinder the connection of circuit elements, a particularly remarkable effect can be exhibited.

[0041]

In the semiconductor integrated circuit device according to the present invention, the distance between the substrate potential wiring and the pad in the peripheral portion of the IC chip can be reduced to the minimum allowable size of the mask rule, and the degree of integration of the IC is not reduced. Also, an ohmic resistor required to protect the PN junction is interposed in series with the protection diode, thereby enhancing the surge resistance of the protection diode itself. The reliability of the circuit function can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of one embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a test circuit diagram of surge resistance.

FIG. 3 shows a contact portion for a substrate potential and a contour for a diode.
Diagram showing the relationship between the distance between the protection sections and the surge withstand voltage of the protection diode

FIG. 4 is a diagram showing the relationship between the surge resistance of the IC when a protection diode is incorporated in the input terminal of the IC and the distance between the contact portion for the substrate potential and the contact portion for the diode.

FIG. 5 is a sectional view of a semiconductor integrated circuit.

FIG. 6 is a plan view of a conventional semiconductor integrated circuit device.

FIG. 7 is an equivalent circuit diagram of a conventional protection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 N-type epitaxial layer 3 P-type isolation region 4 IC substrate 5 Protective film 6 Substrate potential wiring 7 Substrate potential contact part 8 Pad 9 Diode contact part 10 N-type epitaxial layer island 11 Diode Negative diffusion region for contact 12 Protection diode 13 Ohmic resistance

Claims (1)

(57) [Claims] 1. A wiring for a substrate potential formed along a peripheral portion of a semiconductor substrate of one conductivity type, and a wiring for a substrate potential for electrically contacting the wiring for a substrate potential and the semiconductor substrate. A contact portion for substrate potential provided in the region, a plurality of pads spaced apart from and about 30 μm from the wiring for substrate potential, and islands of the opposite conductivity type joined and separated from the semiconductor substrate. Is
Pad type in the island of a plurality of PN junction protection diodes
With smaller are formed from Jo, the plurality of pads provided between the substrate potential line, and a front SL respectively connected to the contact portion for multiple diodes <br/> the plurality of pads, the divided plurality of the substrate potential contact portion so as to sandwich one of the diodes contact portion into a plurality, the substrate potential contact portion from the point opposed to the diode contact portion of the wiring substrate potential A semiconductor integrated circuit device wherein a distance between the diode contact portion and the substrate potential contact portion is set to 50 μm or more.