JP3100802B2 - Method for manufacturing charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a charge transfer device applied to a solid-state imaging device and the like.

[0002]

2. Description of the Related Art As shown in FIG. 3A, a conventional charge transfer device has a P-type substrate 41 on which an N-type region 43 forming a buried channel CCD (hereinafter referred to as BCCD) is formed.
After the gate insulating film 42 is formed, a polysilicon electrode 44 serving as an electrode is selectively formed.

In this charge transfer device, the N-type region 43 is completely depleted by completely removing electrons from the N-type region 43, and the potential depression 45 shown in FIG. The electron of the signal charge is accumulated such that The transfer of charge is carried out by providing a difference in potential between electrodes Tonaria' applying a voltage V _G to polysicon electrode 44.

In the manufacture of this charge transfer device, N
The p-type region 43 is formed by selectively introducing one or both of N-type impurities, phosphorus and arsenic, into the P-type substrate 41 by ion implantation. The conditions for the ion implantation are 50
An acceleration voltage of about 100 KeV, a dose of 1 to 5E12 cm ^-2 , and an impurity concentration distribution are shown in FIG. 47 is the distribution of the N-type region 43, and 48 is the signal charge distribution.

[0005]

In this conventional example, the peak of the impurity concentration distribution of the buried channel has a P-type substrate 41.
In this case, there is a disadvantage that the amount of signal charges is small and the amount of handled charges is small because the transfer efficiency is deteriorated. Further, this conventional example is easy to manufacture, but has a drawback that it is difficult to control and stabilize the potential. That is, the factor that determines the potential is the gate insulating film 4
2 and the impurity distribution 47 of the N-type region 43. If these values fluctuate, the potential fluctuates. For example, if the gate insulating film 42 is thicker, the potential becomes deeper and the impurity concentration of the N-type region 43 becomes higher. Or the diffusion length becomes longer, the potential becomes deeper.

However, the controllability of the thickness of the gate insulating film 2 is about ± 5% with respect to the center, and when the center is 100 nm, the variation is 10%, that is, 10 nm. Therefore, the fluctuation of the potential is about 1 V or more. . Also, the gate insulating film 4
Since the control of the film thickness of No. 2 is performed by adjusting the processing time, the thermal history at the time of forming the gate insulating film 42 directly affects the distribution of impurities in the N-type region 43, and this further increases the variation in potential.

It is therefore an object of the present invention is to solve the above-mentioned conventional drawbacks, transfer efficiency can be increased to Turkey with no amount of charges to degrade, also are easy to control and stabilization of the potential, yet the process An object of the present invention is to provide a method of manufacturing a charge transfer device that can be easily realized and can sufficiently cope with a low voltage.

[0008]

[Means for Solving the Problems]

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a charge transfer device including a gate insulating film having a first oxide film, a nitride film, and a second oxide film. After sequentially stacking the oxide film and the nitride film, a buried channel is formed by ion implantation such that the impurity concentration of the buried channel after the ion implantation has a maximum value inside the surface of the buried channel. Then, the second oxide film is formed.

[0011]

[Action]

[0012]

According to the method of manufacturing a charge transfer device of the first aspect, a buried channel is formed by ion implantation.
Therefore, the thermal history during the formation of the gate insulating film depends on the impurity concentration distribution.
No longer affect the embedded channel area
Depth of impurity concentration distribution is negative with respect to gate insulating film thickness
And the potential change due to manufacturing process fluctuations.
Movement can be controlled by itself,
And keep it stable, while lowering the voltage.
Becomes possible. Also, the impurity concentration of the buried channel
The peak position can be determined with good controllability by the acceleration voltage.
And impurities in the buried channel after ion implantation
Concentration reaches a maximum inside the surface of the buried channel
At the center of the distribution of signal charge, even if the charge increases.
The signal charge accumulates on the substrate
Stays inside effectively, without degrading transfer efficiency
The amount of charge handled can be increased. And signal charge
Increases the amount of storage and transfer efficiency.
It is possible to cope with miniaturization and increase the ability to suppress dark current. Sa
In addition, since the gate insulating film has a three-layer structure of a first oxide film, a nitride film, and a second oxide film in the stacking order, oxidation of the substrate can be prevented, and after the first oxide film and the nitride film are sequentially stacked on the substrate, Since the ion implantation is performed and then the second oxide film is formed on the nitride film, the nitride film suppresses the accelerated diffusion due to oxidation during the formation of the second oxide film after the ion implantation. The impurity concentration distribution at the time is kept almost constant.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. That is, this charge transfer device is
And a buried channel region 3 formed inside the substrate 1 and a gate insulating film 2 formed on the surface of the substrate 1. The gate insulating film 2 has a three-layer structure including an oxide film 2a whose example is a silicon oxide film, a nitride film 2b whose example is a silicon nitride film, and an oxide film 2c whose example is a silicon oxide film. .

The peak value of the impurity concentration distribution in the buried channel region 3 is located inside the substrate 1 as shown in FIG. In this figure, 5 is an impurity concentration distribution,
6 is a distribution on the substrate 1 other than the buried channel region 3, and 7 is a signal charge distribution. FIG. 1 (c) shows the potential distribution, 8 is the potential distribution when there is no signal charge, and 9 is the potential distribution when there is signal charge. Incidentally, V _G is the voltage applied at the time of transfer of charge.

Next, in the method of manufacturing the charge transfer device, after the gate insulating film 2 is formed on the substrate 1, ions are implanted to form the buried channel region 3 in the substrate 1. That is, first, an oxide film 2a and a nitride film 2b for forming a gate insulating film 2 are formed on a P-type substrate 1, and then phosphorus is selectively ion-implanted at an acceleration voltage of 160 KeV and a dose of 2E12 cm ^-2 to be embedded. After forming an N-type region constituting a channel region 3 and further forming an oxide film 2c of a gate insulating film 2, a polysilicon electrode 4 is formed.
Are selectively formed.

According to this embodiment, the gate insulation is provided on the substrate 1.
After the film 2 is formed, ions are implanted into the substrate 1.
Buried channel was formed in the gate insulating film 2
History during formation of silicon no longer affects impurity concentration distribution
And the impurity concentration distribution of the buried channel region 3.
Has a negative correlation with the thickness of the gate insulating film 2
Become like That is, (a) in FIG.₁), (B₁) Is
Charge transfer devices having different thicknesses of the gate insulating film 2 are compared.
It is. And (a) of FIG._Two) Is (a)₁)
Pure substance concentration distribution diagram, (a_Three) Is (a)₁) Device charge
Potential distribution diagram in the absence of (b)_Two) Is (b)₁)
(B)_Three) Is (b)₁) Equipment
FIG. 4 is a potential distribution diagram in a state where there is no signal charge. Figure
2 (b ₁As shown in FIG.₁)
If it is thicker, the buried channel region 3 is formed shallower.
Figure 2 (a₁If the thickness of the insulating film 2 is small as shown in FIG.
The channel region 3 is formed deep. Therefore, Ion
Important for CCD characteristics when the injection acceleration voltage is constant
The potential of the gate insulating film 2 is (b)₁) Thick as
As the depth increases, the depth increases, but the buried channel region 3 becomes shallow.
If it becomes, the potential will be shallow and it will be offset
(B_Three)become that way. Conversely, the gate insulating film 2
(A ₁The potential becomes shallow when it is thin like)
However, since the buried channel region 3 becomes deeper,
Is deepened and offset by the figure (a_ThreeLike)
Figure (a)_Three), (B_Three) Voltage of each potential distribution
αV and βV are α ≒ β.

As described above, even if the gate insulating film 2 fluctuates due to fluctuations in the manufacturing process, fluctuations in the potential are suppressed in a self-controlling manner, so that the potential can be kept constant and stabilized. Therefore, the voltage can be further reduced. Further, as shown in the impurity concentration distribution in FIG. 1, a buried channel region 3 having a concentration peak at a depth (for example, about 0.1 μm) deeper than the interface between the gate insulating film 2 and the substrate 1 is obtained. This peak position can be determined with good controllability by the acceleration voltage. As described above, since the peak position of the impurity concentration of the buried channel is formed inside the substrate 1, as shown in FIG. 1B, the center of the signal charge distribution coincides with the impurity concentration distribution even if the charge increases. I do. As a result, the accumulation of signal charges is effectively kept inside the substrate, so that it is possible to increase the signal amount at which the transfer efficiency starts to deteriorate as compared with the conventional example, and to increase the handled charge amount without deterioration of the transfer efficiency. In addition, since it is possible to increase both the amount of accumulated signal charges and the transfer efficiency, it is possible to cope with the miniaturization of CCDs.

In addition, this charge transfer device can reduce the N-type impurity concentration at the interface between the gate insulating film 2 and the substrate 1 as compared with the conventional structure, so that the pinning phenomenon (interface When the potential at the gate electrode becomes the same as the P-type potential of the channel stopper, the supply of holes starts, and even when the gate voltage is set in the negative direction, the potential of the interface is fixed and the profile of the channel potential is fixed. And the effect of reducing the dark current increases.

Further, in the manufacturing process, after the oxide film 2a and the nitride film 2b are sequentially laminated on the substrate 1, phosphorus ions are implanted, and thereafter, the oxide film 2c is formed on the nitride film 2b, whereby the gate insulating film 2 is formed. Therefore, even if a step of forming an oxide film after ion implantation is performed, the accelerated diffusion due to oxidation is suppressed by the nitride film 2b, so that the impurity concentration distribution at the time of ion implantation is kept substantially constant, and the substrate 1 Oxidation is prevented.

Also, in the case where the P-type region forming the channel stopper is formed by ion implantation after forming the gate insulating film 2, the heat treatment is reduced as compared with the conventional case, and the lateral diffusion of the P-type region of the channel stopper is suppressed. And effective C
Since the channel width of the CD increases, the amount of charges handled increases. In the present invention, the acceleration voltage at the time of ion implantation may be 100 to 300 KeV.

[0022]

【The invention's effect】

[0023]

According to the method of manufacturing a charge transfer device of the first aspect, a buried channel is formed by ion implantation.
Therefore, the thermal history during the formation of the gate insulating film depends on the impurity concentration distribution.
No longer affect the embedded channel area
Depth of impurity concentration distribution is negative with respect to gate insulating film thickness
And the potential change due to manufacturing process fluctuations.
Movement can be controlled by itself,
And keep it stable, while lowering the voltage.
Becomes possible. Also, the impurity concentration of the buried channel
The peak position can be determined with good controllability by the acceleration voltage.
And impurities in the buried channel after ion implantation
Concentration reaches a maximum inside the surface of the buried channel
At the center of the distribution of signal charge, even if the charge increases.
The signal charge accumulates on the substrate
Stays inside effectively, without degrading transfer efficiency
The amount of charge handled can be increased. And signal charge
Increases the amount of storage and transfer efficiency.
It is possible to cope with miniaturization and increase the ability to suppress dark current. Sa
In addition, since the gate insulating film has a three-layer structure of a first oxide film, a nitride film, and a second oxide film in the stacking order, oxidation of the substrate can be prevented, and after the first oxide film and the nitride film are sequentially stacked on the substrate, Since the ion implantation is performed and then the second oxide film is formed on the nitride film, the nitride film suppresses the accelerated diffusion due to oxidation during the formation of the second oxide film after the ion implantation. The impurity concentration distribution at the time is kept almost constant.

[Brief description of the drawings]

FIG. 1A is a sectional view of an embodiment of the present invention;
(B) is an impurity concentration distribution diagram, and (c) is a potential distribution diagram.

FIG. 2 (a)₁), (B₁) Is the mutual of the gate insulating film
Sectional views of examples with different film thicknesses, (a) _Two), (B_Two) Is an impurity
Concentration distribution diagram, (a_Three), (B_Three) Is the potential distribution map
It is.

3A is a cross-sectional view of a conventional example, FIG. 3B is an impurity concentration distribution diagram, and FIG. 3C is a potential distribution diagram.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate insulating film 3 Embedded channel

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/14-27/148 H01L 29/762-29/768

Claims (1)

(57) [Claims] 1. A method of manufacturing a charge transfer device including a gate insulating film having a first oxide film, a nitride film, and a second oxide film, wherein the first oxide film and the nitride film are sequentially formed on a substrate. After lamination, a buried channel is formed by ion implantation so that the impurity concentration of the buried channel after the ion implantation has a maximum value inside the surface of the buried channel, and then the second oxide film is formed. A method of manufacturing a charge transfer device.