JP3101030B2 - Priority encoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a priority encoding circuit for determining a multi-level priority in an information processing apparatus.

[0002]

2. Description of the Related Art In an information processing apparatus, a priority, which is a signal for determining the priority of operation of each device such as a processor and input / output devices such as a magnetic disk, a printer, a display, and a keyboard, is used. A circuit for decoding this priority and recognizing the priority of the device is a priority encoding circuit.

Conventionally, priority encoding circuits up to about 16 or 32 levels existed.
There were no 28 or 256 level priority encoding circuits. This is because, in the past, many such levels were not specifically required by the system. However, with the development of workstations and computer communications, the number of devices included in the entire system tends to increase due to the use of magnetic disks and printers shared by multiple processors. , The number of priority levels must also be increased. If a priority encoding circuit of 256 levels is configured as an extension of the conventional technology in order to respond to such a demand, a circuit as shown in FIG. 2 is obtained.

FIGS. 2 and 3 are explanatory diagrams of a configuration example of a prior art priority encoding circuit. In this figure, it is assumed that the order of priority increases from a small number to a large number. The circuit shown in the figure provides input data through signal lines DT1 to DT255, and outputs a value obtained by encoding the number of the signal line having the highest priority among the input data values "1" (valid) as 8 bits of PDT0 to PDT7. Is what you do. In the figure, the lines with DT2 to DT254 above the lines are the inverse of DT2 to DT254 (negative).
Means input. This circuit is configured to determine the priority by creating a logic in which the bit information of the code value of the encoding result becomes "1", and when there is an input of a higher priority than an input of a certain level And logical sum (AND) elements 21 to 25 for calculating the logical sum of the input condition group whose end data is "1".

[0005] The OR element 26 generates a condition that the most significant bit PDT7 of the encoding result becomes "1". The value of PDT7 is "1" if at least one of DT255 to DT128 is "1". The OR element 27 generates a condition that the upper second bit PDT6 of the encoding result becomes “1”. The value of PDT6 is “1” if any one of PDT255 to DT195 is “1” (implemented by AND elements 21 to 22).
Becomes As described above, the priority encoding from the 256 levels to the 8-bit code is performed by sequentially realizing up to the least significant code bit PDT0 using the signal input with the higher priority as a mask condition.

[0006]

However, the above-mentioned prior art has the following problems. That is, as an extension of the conventional technique, a multi-input logic gate having as many inputs as practically possible (128 inputs for 256-level encoding) is required. Further, when the multi-input logic gate is replaced with a logic gate having an appropriate number of inputs, the number of logic gates increases. In addition, there are many problems such as an extremely large total number of logic gates. SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide an excellent priority encoding circuit capable of reducing the total number of logic gates without using multiple input gates. .

[0007]

SUMMARY OF THE INVENTION A priority encoding circuit according to the present invention divides a plurality of request signals into a plurality of blocks and inputs the plurality of blocks, and also comprises a plurality of block request signals formed by a logical sum of a plurality of request signals in each block. Input, and after outputting a plurality of block request signals, when a block instruction signal indicating the block with the highest priority is input, divided input means for outputting a plurality of request signals in the block indicated by the block instruction signal, When a plurality of block request signals are input from the divided input means, the block having the highest priority is determined, a block instruction signal is output to the divided input means, and a plurality of request signals in the block designated by the divided input means are input. Then, priority encoding means for determining a request signal with the highest priority from among the plurality of request signals is provided. Is shall.

[0008]

In the priority encoding circuit of the present invention, the division input means receives a large number of request signals indicating operation requests of a large number of devices in units of blocks and outputs a block request signal for each block. The priority encoding means receives a plurality of block request signals, selects a specific block having the highest priority, and outputs a block instruction signal. The division input means outputs a plurality of request signals in the corresponding block based on the block instruction signal. When receiving the plurality of request signals, the priority encoding means selects a request signal having a high priority.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the priority encoding according to the present invention. This diagram illustrates the present invention.
Here is an example of the case where the priority is set to 56 levels. The illustrated circuit includes divided input means 4 and priority encoding means 5. OR elements 1 to 3 are connected to the divided input means 4. The priority encoding means 5 serves both as inter-block priority encoding and intra-block priority encoding.

The OR elements 1 to 3 are 16-input OR elements and divide input data DT0 to DT255 into 16 blocks.
It is used to detect whether any one of the blocks is "1". The division input means 4 is a selector for selecting one from 17 types of inputs having a 16-bit width. The condition of the selector is as follows: a signal from the control unit 7;
It is determined by a signal from the holding register 6. In the initial state, the B input is selected by a signal from the control unit 7, and the output data of the OR elements 1 to 3 is output to DO0 to DO15. The signal is input to the priority encoding means 5 which outputs a 4-bit code from the 16th level, and outputs a 4-bit code indicating which block of the input data DT0 to DT255 divided into blocks is higher. This allows
The priority encoding means 5 decodes the inter-block priority between the blocks divided by the division input means 4, and selects a specific block.

After the output result of the priority encoding unit 5 is determined, the control unit 7 instructs the sample of the holding register 6 and the change of the divided input unit 4 to the Axx input.
As a result, the division input unit 4 outputs the 16-bit data of the highest-order block to the priority encoding unit 5. The priority encoding means 5 encodes the most significant bit position in the 16-bit data and outputs it. Thereby, the priority encoding means 5 decodes the priority of the input level in the specified block and selects a specific input level. Finally, the 4-bit codes PDT0 to PDT3 and the 4-bit codes PDT4 to PD output from the holding register 6 are output.
At T7, the final result 8-bit codes PDT0 to PDT7 are obtained.

[0012]

As described above, according to the priority encoding circuit of the present invention, a large number of request signals are divided into blocks, and one priority encoding means is used.
Since the priority of the request signal between blocks and within a block is encoded, it is not necessary to make the logic gate multi-input or multi-stage, and as a result,
The total number of logic gates can be dramatically reduced.
In addition, this makes it possible to introduce a multi-level priority into an integrated circuit (LSI) having a limited number of logic gates. In addition, it is possible to cope with future multi-leveling without increasing the number of logic gates by changing the block division or using a duplex configuration of the priority encoding circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a priority encoding circuit of the present invention.

FIG. 2 is an explanatory diagram of a configuration example of a priority encoding circuit according to a conventional technique.

FIG. 3 is an explanatory diagram of a configuration example of a priority encoding circuit according to a conventional technique.

[Explanation of symbols]

 1-3 OR element 4 divided input means 5 priority encoding means 6 holding register 7 control unit

Claims (1)

(57) [Claims] A plurality of request signals are divided into a plurality of blocks and input, and a plurality of block request signals formed by a logical sum of a plurality of request signals in each of the blocks are input, and the plurality of block request signals are input. After the output, when a block instruction signal indicating the block with the highest priority is input, the divided input unit that outputs the plurality of request signals in the block indicated by the block instruction signal; and the plurality of blocks from the divided input unit. When the request signal is input, the block having the highest priority is determined, the block instruction signal is output to the divided input means, and when the plurality of request signals in the designated block are input from the divided input means, Priority encoding means for determining a request signal having the highest priority from among a plurality of request signals. Code circuit.