JP3101311B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus that executes an editing process on image data.

2. Description of the Related Art A document image is photoelectrically read to form image data, and various image processes are performed on the image data in accordance with an editing instruction of an operator, and the image is edited on a recording material such as paper. There have been proposed various digital copiers for reproducing an image.

Recently, digital copying machines for replacing color images have been proposed, and along with this, various and various editing processes have been executed.

Therefore, in order to execute such various editing processes,
A plurality of processing circuits for various processes are provided.

FIG. 5 shows a configuration example of an image processing apparatus having such a plurality of processing circuits.

Numerals 70 to 73 denote processing circuits for performing processing on the image data, respectively. The processing circuits 70 to 73 are connected in series, and have a configuration in which the image data processed by the preceding circuit is processed by the subsequent circuit. The processing circuits 70 to 73 execute editing processing according to the editing signals A to D, respectively.

Now, assume that four edit signals A to D are simultaneously supplied to the same pixel. However, the four processing circuits 70-
73 cannot simultaneously process the same pixel, so it is necessary to supply four edit signals for the same pixel to the corresponding processing circuits at different time zones.

For this purpose, three delay circuits 74 to 76 are provided for each of the three processing circuits 74 to 76, and the edit signals BD are delayed by the delay circuits 74 to 76, respectively. It is configured to supply.

[Problems to be Solved by the Invention] However, in the conventional technique shown in the configuration of FIG. 5, it is necessary to provide a dedicated delay circuit suitable for the circuit configuration of each processing device. When there is a change in the characteristics or the characteristics, it is necessary to adopt a new delay circuit configuration.

The present invention is to eliminate the above-described disadvantages of the prior art, an edit signal for editing instructions output from the delay means to a plurality of processing means for performing a plurality of image processing, comprising a plurality of bits of data, A plurality of delay means are provided corresponding to each of the plurality of bits, and the delay amount of each of the plurality of delay means can be set independently, so that the configuration of the image processing circuit is changed, that is, Provided is an image processing apparatus that can sufficiently cope with the abolition or addition of a processing circuit or a change in characteristics or processing time without requiring a significant circuit change of a delay unit for supplying an edit signal. With the goal.

[Means for Solving the Problems] To achieve the above object, in the image processing apparatus of the present invention, a first input means for inputting image data,
A plurality of processing means for executing a plurality of image processes on the image data input by the input means, and an edit signal consisting of a plurality of bits for issuing an editing instruction to the plurality of processing means, the image data of one pixel or a plurality of pixels. A second input means for inputting in correspondence with the second input means; a plurality of delay means for independently delaying and outputting an edit signal composed of a plurality of bits input by the second input means for each bit; Setting means for independently setting a delay amount in each of the delay means, wherein each of the plurality of delay means converts an edit signal delayed based on the delay amount set by the setting means to any of the plurality of processing means. Output to

[Examples] Hereinafter, the present invention will be described using preferred examples.

FIG. 1 is a block diagram showing a configuration example of a color image processing apparatus to which the present invention is applied. FIG. 2 shows signal waveforms at various parts in FIG. The apparatus shown in FIG. 1 prints out a plurality of color original images after processing them in accordance with an instruction from an operator.

Reference numeral 10 denotes an editing device, which has a digitizer 11 for inputting coordinates and an operation unit 17 for inputting various commands. The operator can use the digitizer 11 and the operation unit 17 to perform filtering, trimming, masking, and the like for each area. The CPU 12 captures and analyzes the image editing instruction, and the CPU 12 stores the editing signal corresponding to the analyzed editing operation in the bit map memory 15 via the buffer 18 in accordance with the address control of the CPU 12.
The selector 14 selects an address to the bit map memory 15.

In this embodiment, the bit map memory 15 has a depth of 8 bits, and is the maximum size A4 which can be processed by the apparatus of this embodiment.
It is the capacity for the size. Then, an 8-bit edit signal representing a maximum of eight types of processing steps per pixel is stored corresponding to all pixels of the A4 size image. If the accuracy of the editing operation is not so required, one edit signal is made to correspond to a plurality of adjacent pixels so that the bit map memory 15 can be used.
Can be reduced. The number of bits of the edit signal can be changed by the number of processing steps for the image signal, and the depth bit of the bit map memory 15 is set according to the maximum number of processing steps. Further, when a plurality of edit signals are required for one type of processing step, the number of processing steps is smaller than the number of bits of the edit signal.

The 8-bit edit signal stored in the bit map memory 15 responds to the ON operation of the copy start key of the operation unit 17 by the operator, and performs 8-bit parallel processing using the count value from the counter 13 for counting the image clock CLK as an address. Each pixel is read out through the buffer 18 as shown in FIG. Also, in response to the ON of the copy start key, the image scanner 21 of the image processing apparatus 20 changes the color document image on the document table to blue (B),
The color is separated into three primary colors of green (G) and red (R), read photoelectrically, and output in dot sequence in synchronization with the pixel clock CLK as shown in FIG. 2 (b).

In this way, R, output from the image scanner 21,
Each of the G and B color data is an 8-bit signal capable of expressing 64 gradations, and has an empty area "X" between pixels.

The respective color data R, G, B from the image scanner 21 and the editing data M from the bitmap memory 15 are input to the synthesizing circuit 16, and the synthesizing circuit 16 edits the data corresponding to the empty area X from the image scanner 21. The data M is fitted as shown in FIG. 2 (d) and output to the image processing device 20. Image processing device
20 is provided with an edit data correction unit 33 having a one-chip configuration,
The one-chip edit data correction unit 33 includes a separation circuit 22, delay circuits 23 and 32, and a mask level matching circuit 24, which will be described later, as an integrated circuit.

The color data including the editing data M from the synthesizing circuit 16 is input to the separation circuit 22 of the editing data correction unit 33,
Then, the edit data M is separated from the input data and output as the separation circuit outputs shown in FIGS. 2 (e) and 2 (f). In FIG. 2E, the edited data M is also included in the image data R, G, and B after the edited data M is separated. This is for the purpose of, for example, transmitting an edit data to a further device when another device other than the image processing device 20 is connected and the edit instruction in the device is included in the edit data.

Image data R, G, B (M) output from the separation circuit 22
Are five processing circuits connected in series, that is, a logarithmic conversion circuit 26, a filter circuit 27, a density setting circuit 28, a density inversion circuit
29. In the trimming circuit 30, processing is sequentially performed.
The processed image data is, for example, a bubble jet type ink jet printer that generates bubbles by heat, ejects ink by the pressure to record an image on a recording material, or exposes and scans a photoconductor with a laser beam, A color image is reproduced by a printer 31 such as a laser beam printer that records an image on a recording material by a photographic process.

Filter circuit 27, density setting circuit 28, density inversion circuit 29,
The trimming circuit 30 can specify whether or not to execute the process or the type and degree of the process by an external input.For example, in the filter circuit 27, it is possible to select whether to perform the edge enhancement process or the smoothing process as the filter process. In the density setting circuit 28, it is possible to select one of a plurality of gamma correction characteristics prepared in advance by using an external input.

On the other hand, the edit data M separated by the separation circuit 22 is input to the mask level matching circuit 24 after being given a predetermined delay by the delay circuit 23, and then supplied to the corresponding processing circuit as the above-mentioned external input. Is done.

That is, each bit of the 8-bit parallel image data M is supplied to each processing circuit in accordance with the processing timing and processing level in the corresponding processing circuit.

FIG. 3 shows the configuration of the delay circuit 23. Numerals 40 to 47 denote D-type flip-flops (DF / F), each of which has 64 DF / Fs corresponding to each bit of 8-bit edit data input in parallel.
F is connected in series. The outputs of the DF / Fs 40 to 47 are input to eight selectors 50 to 57 corresponding to each bit of the 8-bit edit data.

For example, the seventh bit of the edit data is sequentially latched by 64 pixel-connected clocks to DF / Fs 47-1 to 47-64 connected in series. All 64 outputs of the 64 DF / Fs 47-1 to 47-64 are input to the selector 57. Selector 57 is CPU12
The selector operates according to the initial setting of, and selects one of the 64 inputs. Therefore, depending on which of the 64 inputs is selected, the seventh bit of the edit data M can be delayed by an arbitrary number of clocks from 1 to 64 clocks. The seventh bit of the edited data is output as edited data M '.

Similarly, one of the outputs of the 64 DF / Fs 40 to 46 connected in series is selected by the selector 50 for the other 7-bit edit data, that is, the 0th to 6th bits of the edit data.
Each bit can be individually selected by selecting
A time delay in the range of ~ 64 clocks can be provided.

Accordingly, each processing block 26 for the image data R, G, B
By operating the selectors 50 to 57 in the delay circuit 23 in accordance with the delay time of the image data due to the processing time of ~ 30, the corresponding edit data is processed in each processing with a delay corresponding to the delay of each processing circuit. Supplied to the circuit.

The number of DF / Fs is not limited to 64, and it goes without saying that the number of DFs / Fs can be set to a value that allows the delay to cover the maximum delay time of the processing circuit.

FIG. 4 shows the configuration of the mask level matching circuit 24. The 8-bit edit data after the delay from the delay circuit 23 (at this point, individual delays are made in bit units) are input to the AND gates 60-0 to 60-7, respectively. Each of the AND gates 60-0 to 60-7 is turned on / off in accordance with an instruction from the CPU 12, and a necessary bit of the 8-bit edit data is selected. By turning off all the AND gates 60-0 to 60-7, all the bits of the edit data are set to low level. For example, when the edit data included in the input image data is unknown or undefined, the edit data In this way, it is possible to prohibit all of the editing processing by the user and to prevent inadvertent editing processing from being performed.

Further, the active level differs depending on the input characteristics of the processing circuit, and there is a case where the processing is not performed when the edit data is at a high level. In such a case, a high-level signal is input from the CPU 12 to the necessary ones of the OR gates 61-0 to 61-7, and all or necessary bits of the editing data are set to the high level, whereby the editing processing by the processing circuit is performed. Ban.

In addition, the active level of each processing circuit is different,
And if you want to execute the editing process,
The 60-0 to 60-7 and the OR gates 61-0 to 61-7 input one signal to all or necessary exclusive OR gates 62-0 to 62-7 without any operation, and edit data. Of all bits or required ones are inverted and output.

As described above, the edited data M ″ delayed for the required time in the delay circuit 23 and level-corrected as necessary in the mask level matching circuit 24 is supplied to the corresponding processing circuit, and each processing circuit performs the processing as described above. And performs processing on the image data according to the input editing data.

As described above, the edit data is delayed for each bit, and the effective section of the image data in each processing circuit needs to be delayed in accordance with the delay. Therefore, an effective section signal indicating an effective section of one line of image data generated from the image effective section signal generator 25 is
In accordance with instructions from the CPU 12, the signals are delayed with a plurality of delay times to form a plurality of valid section signals for each processing circuit.

Note that the delay circuit 32 has the same structure as the delay circuit 23 described above.
A plurality of delay units capable of selecting a time delay within a range of up to 64 clocks are provided, and the plurality of delay units are operated to be delayed in accordance with the delay time of the edit data by the delay circuit 23 described above. In this way, by delaying the effective section signal to be supplied to each processing circuit together with the delay of the edited data to be supplied to each processing circuit, each processing circuit can execute each editing process on the image data satisfactorily with accurate timing. It becomes possible.

Also, a plurality of valid section signals from the delay circuit 32 can be selectively subjected to level matching processing, validating, and invalidating processing, similarly to the above-described editing data.

As described above, the delay time of the edit data and the valid section signal according to the input delay of the image data to the processing circuit is not fixed, but can be selected from a plurality of delay times.
Also, the presence or absence or the level of the output of all the edit data or the necessary bits can be set, so that the necessary edit data can be sent to the processing circuit at the necessary timing according to the configuration of the image processing circuit. It is possible to supply a large amount of editing data, even if the configuration of the image processing circuit is changed, that is, the processing circuit is abolished or added, or the characteristics or processing time is changed. It is possible to respond sufficiently without any change.

In addition, since the edit data correction unit 33 is formed as one chip, the above functions can be easily added to devices having various circuit configurations by using the chips.

In the above description, the image data and the edit data are input to the image processing apparatus 20 in a combined form. However, the present invention is not limited to this, and the image data and the edit data are input separately. It goes without saying that the present invention can be applied to the time delay of the edit data in the configuration.

In this embodiment, the editing data is stored in the bitmap memory 15 and read out therefrom.
Depending on the speed of the image processing, the editing data formed by the CPU 12 may be transmitted to the synthesizing circuit 16 or the image processing apparatus via a small-capacity line memory or the like without passing through the bit map memory.
It is also possible to use a configuration in which the number is supplied to 20.

The image data to be edited is not limited to R, G, B color image data, but may be other color image data such as yellow Y, magenta M, cyan C color image data, or only color image data. Alternatively, it is possible to perform editing processing on monochrome image data.

[Effects of the Invention] As described above, according to the present invention, an edit signal for an edit instruction output from a delay unit to a plurality of processing units that execute a plurality of image processes is constituted by a plurality of bits of data,
A plurality of delay means are provided corresponding to each of the plurality of bits, and the delay amount of each of the plurality of delay means can be set independently, so that the configuration of the image processing circuit is changed, that is, There is an effect that it is possible to sufficiently cope with the abolition or addition of the processing circuit, or the change of the characteristic or the processing time without the necessity of a large circuit change of the delay means for supplying the edit signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of the configuration of an image processing apparatus to which the present invention is applied, FIG. 2 is a diagram showing components and signals of the apparatus shown in FIG. 1, FIG. FIG. 4 is a diagram showing a configuration example of a mask level matching circuit, FIG. 5 is a diagram showing a conventional configuration example, 15 is a bit map memory, 16 is a synthesis circuit, 21 is an image scanner, 22 is a separation circuit, 23 is a delay circuit, and 24 is a delay circuit. It is a mask level matching circuit.

Claims (4)

(57) [Claims] A first input unit for inputting image data; a plurality of processing units for executing a plurality of image processes on the image data input by the first input unit; and an edit to the plurality of processing units. A second input unit for inputting an edit signal consisting of a plurality of bits for issuing an instruction in correspondence with image data of one pixel or a plurality of pixels; and an edit signal consisting of a plurality of bits input by the second input unit. A plurality of delay means for delaying and outputting the bits independently, and a setting means for independently setting a delay amount in each of the plurality of delay means, wherein each of the plurality of delay means is the setting means Outputting an editing signal delayed based on the delay amount set by the processing means to any of the plurality of processing means. 2. The apparatus according to claim 1, wherein said plurality of delay means selectively enable or disable all or a required signal of a plurality of bits of the edit signal inputted by said second input means. The image processing device according to item (1). 3. The apparatus according to claim 2, wherein said plurality of delay means selectively level-converts all or a necessary signal of a plurality of bits of the edit signal inputted by said second input means and outputs the result. The image processing apparatus according to item (1). 4. The apparatus according to claim 1, wherein a signal indicating an effective section of an image is delayed and output to any one of said plurality of processing means in accordance with a delay operation by said plurality of delay means. The image processing device according to the item 1).