JP3102829B2 - Digital PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL (phase locked loop) circuit, for example, a signal transmission device and a LAN.
This is applicable to a timing extraction circuit in a receiving circuit such as a (local area network).

[0002]

2. Description of the Related Art When signals transmitted and received between two devices are digital signals, they are generally encoded. To reproduce an encoded digital signal, it is necessary to extract a carrier and its timing information according to the encoding method. Conventionally, as a timing extraction circuit in such a case, (1) a circuit utilizing a resonance phenomenon (eg, a tank circuit, a filter element) (2) a circuit applying a PLL circuit (eg, an analog PLL circuit, a digital PLL circuit) ) was there.

In an analog PLL circuit, a VCO
Also, an analog element is used for a loop filter.
On the other hand, a digital PLL circuit is mainly configured with the following element technologies of a digital VCO and a loop filter (see the following document).

Digital VCO: A digital VCO that adds or removes a pulse from a fixed-period pulse output and then divides the frequency. Alternatively, two different fixed-period pulse outputs are
The frequency is selected by a control signal and then divided.

[0005] Loop filter: N-Before-M
A filter or a random walk filter. These filters are of the type in which the binary phase comparison output of +1 and -1 first outputs the one that reaches N times, then resets, and repeats the operation.

Reference "PLL control circuit casebook", Published by Trikeps Co., Ltd., pp. 29-34, 61-67.
Page, December 1987 "

[0007]

However, in the case of a device utilizing the resonance phenomenon, there is a wealth of data on characteristics and applications, but it is difficult to eliminate adjustment, components are likely to be large, no adjustment, and miniaturization. This has the disadvantage of being expensive.

In addition, the analog PLL circuit has a drawback that it is difficult to design a circuit that satisfies the desired characteristics, and that is stable and free from adjustment.

Further, in the digital PLL circuit, although no adjustment is possible, information on characteristics, applications and specific circuits is limited. For this reason, for example, it was unclear whether the short-time pull-in characteristic such as packet transfer or the operation at the time of low-level input can be put to practical use.

The present invention has a digital P which has a short-time pull-in characteristic, operates well even at a low level input, and has no adjustment.
It is intended to provide an LL circuit.

[0011]

In both the first and second embodiments of the present invention, the phase comparison means obtains a phase difference signal between the input signal and the periodic signal output from the VCO means or its divided signal. The loop filter means makes a transition to a new control state in accordance with the phase difference signal and the immediately preceding control state, and forms a control signal for phase adjustment and gives the control signal to the VCO means to provide the VCO means. It is assumed that a digital PLL circuit that adjusts the phase of a sex signal is used.

According to a first aspect of the present invention, the phase difference signal indicates "lag", "coincidence" or "advance", and the loop filter means controls the "synchronous state" or "asynchronous state". Then, a transition is made from the "asynchronous state" to the "synchronous state" according to the backward protection method, and in the backward protection state, the control signal for phase adjustment given to the VCO means is "no phase adjustment". .

According to a second aspect of the present invention, the phase difference signal indicates "delay", "coincidence" or "advance", and the loop filter means controls the "synchronous state" or "asynchronous state". Then, a transition is made from the "synchronous state" to the "asynchronous state" according to the forward protection function, and in the forward protection state, the control signal for phase adjustment given to the VCO means is "no phase adjustment". .

[0014]

According to the first and second aspects of the present invention, the state transition for phase control performed by the loop filter means of the digital PLL circuit uses the backward protection or forward protection technique employed for frame synchronization of a transmission device or the like. By applying this, even if the stability of the input signal to the digital PLL circuit is low, the digital PLL circuit can operate satisfactorily by its protection function.
The LL pull-in time can be made appropriate.

[0015]

【Example】

(A) First Embodiment Hereinafter, a digital PLL circuit according to a first embodiment of the present invention will be described in detail with reference to the drawings. Here, FIG. 2 is a block diagram showing the overall configuration, and FIG. 3 is a block diagram showing the configuration of the loop filter unit (synchronous search type filter unit) 6.

The digital PLL circuit of the first embodiment is
This is applied as a timing extraction circuit for extracting a timing information signal timO from an encoded input signal input, and the input signal input is a CM.
This is the case of an I (Coded Mark Inversion) code.

In FIG. 2, the digital PL of the first embodiment is shown.
The L circuit includes a change point extraction unit 1, a VCO counter unit 2, a phase comparison unit 3, an active period detection unit 4, a decode / latch unit 5, and a loop filter unit 6.

In this embodiment, since the input signal input is a CMI code, if the minimum interval time between change points is T, the interval between change points in the code is one of T, 2T, and 3T. This digital PLL circuit is used to detect a phase in which the minimum interval time T between the transition points is one cycle.

The change point extraction unit 1 has an input signal input
In addition, a high-frequency clock CLK1 whose period shown in FIG. 4A is ΔT (= T / 8) is provided. The change point extracting unit 1 generates the data at any of the intervals T, 2T, and 3T in FIG.
Input signal input (CMI code) as shown in (C)
Is to extract the change point in FIG.
As shown in (D), the timing at which the extraction output becomes significant is delayed by the time required for the extraction processing (for example, T / 4) as compared with the change point. The extracted output is provided to the phase comparison unit 3 and the active period detection unit 4.

The VCO counter 2 is supplied with a high-frequency clock CLK1 as a clock for updating the count, and receives a control signal forc from the loop filter 6.
e is given. The control signal force takes three types of states f, n, and b, as shown in FIG. 5, which represents the states of the input signal and the output signal of the loop filter unit 6, and the state f is “phase is ΔT (for example, T / 8 ), State n is “maintain phase (do nothing)” and state b is “phase is ΔT
(Eg, T / 8). " The VCO counter unit 2 calculates T based on the high-frequency clock CLK1.
The count value is cyclically updated at / 8 intervals. For example, it is basically configured to use a hexadecimal counter that takes 0 to 15 as an octal counter that cycles through 0 to 7, and uses the next value of the count value 7 as the control signal fo.
As shown in FIG. 4B, selection is made according to the states f, n, and b of the rc.

When the control signal force is in the state f, the count value is set to the count value 1 next to the count value 7, and then the count value 7
(T−ΔT). Also, the control signal for
When ce is in the state n, the count value is set to the next count value 0 after the count value 7, and the cycle until the next count value 7 is taken is set to eight predetermined times of the high frequency clock CLK1 (T). Further, when the control signal force is in the state b, the count value is set to the next count value 15 after the count value 7, and the cycle until the next count value 7 is taken is set to 9 of the high frequency clock CLK1.
It is lengthened as an individual (T + ΔT).

The count value of the VCO counter unit 2 whose value changes as described above is given to the phase comparison unit 3, the active period detection unit 4, and the decode / latch unit 5.

The VCO counter unit 2 also has two low-frequency clocks CLK21 and CLK22 shown in FIGS. 4G and 4H whose period changes between T + ΔT and T−ΔT based on the change in the count value. The clocks CLK21 and CLK22 are supplied to the loop filter unit 6. Note that each edge of the clock CLK21 is delayed by T / 4 from each edge of the clock CLK22.

The phase comparing section 3 compares the phase of the change point extraction output of the input signal input with the phase of the count value (referred to as VCO count value) from the VCO counter section 2. As shown in FIG. 6, the phase comparison unit 3 sets the VCO count value at the significant timing of the change point extraction output to “0, 1,
A comparison result phase representing a "matching state c" at "7, 15", a "lagging state b" at "2, 3", and a "leading state f" at "4, 5, 6" is created. To the loop filter unit 6.

Based on the VCO count value and the change point extraction output of the input signal input, the active cycle detector 4 determines whether there is a change point in one cycle of the VCO counter 2 as shown in FIG. 6 (state a). A signal act indicating whether or not (state e) is formed and output to the loop filter unit 6. Here, one cycle of the VCO counter unit 2 is, for example, a period from the time when the count value changes from a large value (7 or 15) to a small value (0 or 1) to the next similar change time. (See ranges B, C, D in FIG. 4).

As described above, the high frequency clock CLK1 and the VCO count value are given to the decode / latch unit 5. The decode / latch unit 5 decodes and latches the VCO count value, thereby obtaining the input signal inp.
A timing information signal timO as shown in FIG. 4I, which is adjusted in phase according to the phase of ut and equivalent to dividing the frequency of the high-frequency clock CLK1, is formed and output. For example, the timing information signal timO that rises at the falling edge of the high-frequency clock CLK1 when the VCO count value is “2” and falls at the falling edge of the high-frequency clock CLK1 when the VCO count value is “6”.
To form

The rising phase of the timing information signal timO thus formed (timing J, K, L in FIG. 4)
Is the optimal punching timing of the input signal input consisting of the CMI code.

The loop filter unit 6 determines the VC signal based on the output signal phase from the phase comparison unit 3, the output signal act from the active period detection unit 4, and the control state immediately before.
Control signal for phase adjustment given to O counter 2
To form The low-frequency clocks CLK21 and CLK22 supplied from the VCO counter unit 2 are used for timing definition such as a latch process and are not directly related to the formation of the phase adjustment control signal force.

As described above, the loop filter unit 6
It has the detailed configuration shown in FIG. That is, it is composed of four counter units 7 to 10, a state transition logic circuit 11, and a D flip-flop group 12. The counter unit 9 is composed of, for example, one JK flip-flop.
In this case, it should be called a register circuit, but in this specification, it is called a counter section.

Each of the counters 7, 8, 9, and 10 counts a count value (register value) Ct1, a register value by a significant edge (rising edge) of the low-frequency clock CLK21.
Ct2, Ct3, and Ct4 are changed. This change may be caused by a load operation or an increment operation. The count values of the respective counter units 7, 8, 9, 10 have the meanings as shown in the table of FIG.

The count value Ct1 of the counter unit 7 (hereinafter, referred to as a protection stage number counter unit) means the value of the current protection stage number for multi-stage protection or the like, and its maximum value is a value p or q described later. Is the larger value of The multi-stage protection (backward protection and forward protection) will be described later. The count value Ct2 of the counter unit 8 (hereinafter, referred to as a synchronous / asynchronous counter unit) indicates whether the state is a synchronous state or an asynchronous state. The count value Ct3 of the counter unit 9 (hereinafter, referred to as a leading / lag managing counter unit) indicates whether the state is in the leading tendency state or the retarding state. The count value Ct4 of the counter unit 10 (hereinafter, referred to as an empty cycle management counter unit) means the number of consecutive empty cycles and the like. Here, the VCO without the change point of the input signal input
The cycle of the counter unit 2 is called an “empty cycle”.

The state transition logic circuit 11 is, for example, a combination of logic gates having no flip-flop for speeding up processing. That is, it is configured in hardware. Its functions are the control state immediately before the VCO counter unit 2 and the output signal phas from the phase comparison unit 3.
In order to form the next control state for the VCO counter unit 2 based on e and the output signal act from the active cycle detection unit 4, it is not always necessary to use a hardware configuration. The state transition logic circuit 11 causes the counter units 7, 8, 9, and 10 to change states according to conditions while following a predetermined order. In this sense, the loop filter unit 6 constitutes a sequential circuit. be able to.

The state transition logic circuit 11 outputs a signal to the above-described counters 7 to 10 and a control signal force to the VCO counter 2. In addition,
These signals are latched by a predetermined D flip-flop of the D flip-flop group 12, and then applied to the corresponding processing unit. Each flip-flop of the D flip-flop group 12 uses the clock CLK22 as a latch clock. The signals to the counter units 7, 8, and 10 are data to be loaded and control signals such as a counter load command and an enable signal. The signal to the counter unit (JK flip-flop) 9 is a signal for presetting (a signal for the J input terminal and a signal for the K input terminal).

FIG. 8 shows the timing conditions in the loop filter section 6. The output signal p from the phase comparison unit 3 and the active period detection unit 4 shown in FIG.
“hase” and “act” are given in synchronization with the low-frequency clock CLK21 shown in FIG. A signal formed by the logic circuit 11 in accordance with these signals phase and act, for example, a control signal force shown in FIG.
Are latched by the D flip-flop group 12 at the timing when the time required for the formation is sufficiently ensured in accordance with the clock CLK22 shown in FIG. Among the latch signals, the signals for the counter units 7 to 10 are shown in FIG.
Are taken into the counter units 7 to 10 in synchronization with the low frequency clock CLK21 shown in FIG.
Is continuously input to the logic circuit 11 for one cycle of the low-frequency clock CLK21 from that timing.

As described above, the loop filter section 6 has a VC of a period ΔT (= T / 8) with a period substantially equal to time T.
The phase state of the O counter unit 2 is being reviewed.

Next, the function of the state transition logic circuit 11 (transition of the control state), that is, the function of the loop filter section 6, will be described in more detail.

Here, FIG. 1 shows the active period detecting section 4.
FIG. 9 is a state transition diagram in the case where the output signal act from the VCO counter 2 has the content “a” which means that there is an input change point in one cycle of the VCO counter unit 2. On the other hand, FIG.
FIG. 10 is a state transition diagram in the case of content “e” meaning that there is no input change point in one cycle of the VCO counter unit 2.

In FIGS. 1 and 9, white circles represent state nodes (hereinafter, simply referred to as nodes).

The nodes can be classified into two based on the phase leading / lagging tendency, and can be classified into two based on synchronous / asynchronous. Eventually, the nodes are advanced synchronization state nodes B0 to Bq and C1 to Cq, delayed synchronization state nodes E0 to Eq and F1 to Fq, advanced asynchronous state nodes A0 to Ap, and delayed asynchronous state. The state nodes D0 to Dp can be classified into four types. Each state node A0,
..., Ap, B0, ..., Bq, C1, ..., Cq, D0,
, Dp, E0, ..., Eq, F1, ..., Fq, the count value Ct1 of the protection stage counter 7 and the synchronization /
The count value Ct2 of the asynchronous counter unit 8 and the advance /
The count value Ct3 of the delay management counter 9 has a value as shown in FIG. Note that the count value Ct4 of the idle cycle management counter section 10 becomes “0” after the state transition when the output signal act from the active cycle detection section 4 has the content “a” indicating that there is an input change point.

In the prior art, there has been no classification of the states into the leading tendency state and the lagging tendency state. However, in this embodiment, it is better to classify the loop filter section 6 by the combination of the logic gates in this way. In consideration of easy configuration, easy application of a rear protection procedure and a front protection procedure, which will be described later, the classification is made in this way.

In FIGS. 1 and 9, curves with arrows connecting nodes represent state transition links (hereinafter, simply referred to as links).

In FIG. 1, among the symbols x / y given in connection with the link, “x” is the content of the output signal phase of the phase comparator 3 and “y” is the control signal force.
It is the contents of.

On the other hand, in FIG. 9, the symbols α, β or γ given in connection with the links represent the conditions and operations shown in FIG. That is, when the current cycle is an empty cycle (act = e) and the count value Ct4 of the empty cycle management counter unit 10 is one of 0 to 2, the symbol α indicates the count value Ct4 in the next cycle. Is incremented by one from now, and the symbol β represents the next cycle when the current cycle is an empty cycle (act = e) and the count value Ct4 of the empty cycle management counter unit 10 is 3. And the symbol γ indicates that the next cycle is a free cycle (act = e) regardless of the value of the count value Ct4 of the free cycle management counter unit 10 if the current cycle is a free cycle (act = e). Represents that the count value Ct4 in the cycle of is set to 0. Note that, even in this case (act = e), the values of the count values Ct1 to Ct3 are uniquely determined by the transition destination state as shown in FIG. Also, in this case (act = e), the control signal for
The content of ce is "do nothing (n)", whatever the transition.

Next, referring mainly to FIGS. 1 and 9, the state of the loop filter section 6 and the control signal force will be described.
The following describes how the content changes.

In FIGS. 1 and 9, the initial state of the loop filter section 6 (when there is no input signal input) is in the asynchronous state A0 or D0.

In this embodiment, the input signal inpu
Since t is a CMI code, the interval between the extracted change points takes T, 2T, or 3T even during the period in which the input signal input is arriving, and the output signal act from the active period detection unit 4 changes. Pointless (e), in other words, may indicate an empty cycle. However, since the maximum change point interval is also 3T, the condition relating to the symbol α or the condition relating to the symbol β or γ in FIG. 11 is not satisfied with respect to the idle cycle during the arrival of the input signal input. In other words, in the idle period during the arrival of the input signal input, only the state transition related to the symbol α is executed, and as is apparent from FIG. 9, the state is the same after transition and before transition. .

Therefore, hereinafter, the description of the state transition while the input signal input is arriving will be made only for the cycle in which the change point is extracted.

For example, in the initial state A0 in the leading direction, the input signal input starts to be inputted, and the phase comparison output signal phase (= f or b) containing the phase mismatch of the leading and lag is inputted to the loop filter section 6. Then, the state is maintained at A0, but the control signal force to the VCO counter unit 2 has the content f to advance the phase. Similarly, in the initial state D0 in the delay direction, the input signal input starts to be input, and the phase comparison output signal phase (= f
Or, if b) is input, the state maintains D0, but V
The control signal force to the CO counter unit 2 has the content b for delaying the phase.

Thus, the cycle of the VCO counter unit 2 is adjusted from T by ΔT (for example, ΔT = T / 8) in the leading direction or the lagging direction. Such an initial state A0 or D0
Is maintained until the phase of the input signal input matches the phase of the count value of the VCO counter unit 2 (phase = c). Is T / ΔT times (for example, 8 times)
Until this occurs, the phases of the input signal input and the count value of the VCO counter unit 2 match.

When a change point is extracted in the situation where the phases match in this way (phase =
c, act = a), as shown in FIG. 1, the state shifts from A0 (or D0) to A1 (or D1), and the control signal force becomes the content (c) in which the phase is not shifted.
Phase matching continues. Therefore, every time a change point is extracted (phase = c, act = a), the states are A1, A2,
, Ap (or D1, D2,..., Dp), and the control signal force repeats the content (c) in which the phase is not shifted. During the change from the state A0 to Ap (or during the change from D1 to Dp), if the phase comparison output signal phase indicates the advance (f) or the delay (b) of the phase, the state becomes the asynchronous initial state. State A0 or D
Returning to 0, the control signal force at that time has the content (f or b) of the phase adjustment.

According to the above-described multi-stage protection method, when the phase of the input signal input and the count value of the VCO counter unit 2 continuously (p + 1) times in the asynchronous state, the basic state of the synchronous state B0 (or E0)
Move to That is, the state shifts to the synchronous state by the backward protection procedure of the protection stage number p + 1.

In the conventional digital PLL circuit, there is no loop filter using a backward protection procedure. However, in this embodiment, even if the stability of the input signal input is low, the protection function can be effectively performed by the protection function. The rear protection procedure is adopted in consideration of operability, appropriate selection of the PLL pull-in time by selecting the number of stages of rear protection, and the like.

In the synchronization reference state B0 (or E0), the same state B0 (or E0) is maintained as long as the phase comparison output signal phase indicates the content (c). A control signal force (= n) that does not change the phase is output.

Regardless of the synchronization reference state B0 or E0, the phase comparison output signal phase is the input signal input.
When the leading phase of t is indicated (f), the state is shifted to the state B1, and at the same time, the control signal force (= f) for leading the phase is advanced.
Is output. Similarly, when the phase comparison output signal phase indicates the delay phase of the input signal input (b), the control signal fo shifts to the state E1 and at the same time delays the phase.
rc (= b) is output.

From the synchronization reference state B0 or E0 to the state B1
(Or E1), the synchronization state continues thereafter, and the phase comparison output signal ph having the content (c) as the phase coincidence
If ase continues q times, the states are B2, B3,..., Bq
(Or E2, E3,..., Eq) and the synchronization reference state B0
Alternatively, the process returns to E0, and the value of the control signal force relating to each state transition also takes the content (n) for maintaining the phase.

As described above, during the return from the state B1 on the advancing tendency side to the synchronization reference state B0 via the states B2, B3,..., Bq, that is, when the state B1 is in any state Bi from the state B1 to the state Bq When the phase comparison output signal phase having the advanced content f is input, the state shifts to the state Ci. In this case, the control signal force also has no phase adjustment (n). Similarly, during the return from the state E1 on the delay tendency side to the synchronization reference state E0 via the states E2, E3,..., Eq, that is, when the state is one of the states Ei from the state E1 to the state Ei, the delay contents b When the phase comparison output signal phase is input, the state shifts to state Fi. The control signal force also has no phase adjustment (n) in this case. That is, before returning to the synchronization reference state B0 or E0, the advance content f is performed once more.
Alternatively, generation of the phase comparison output signal phase of the delay content b is allowed.

The protection structure for such a synchronous state is as follows.
This is because there is an unavoidable time lag in the timing design from the occurrence of the allowable phase difference to the completion of the tracking of the VCO counter unit 2. That is, a mismatch input is added to the loop filter unit 6 (phase = f or b),
Even if the follow-up control is performed immediately, it takes time to complete. During that time, the mismatch may be re-detected.

.., Bq−
1, the phase comparison output signal phase of the delay content b
Are input, as shown in FIG. 1, the state shifts to the state E2,..., Eq on the delay tendency side. At this time, the control signal force having the content of (b) to be delayed is output. When the phase comparison output signal phase of the advance content f is input in the states E1,.
.., Bq, the control signal force having the content of (f) to proceed is output.

The state transition and the like when the phase comparison output signal phase having the content of the phase match (c) is given after the state has departed from the synchronization reference state B0 or E0 are as follows.

(1) The control signal force has no phase adjustment (n). (2-1) The state before transition is Xi (X is B, C, E or F, and i is 1 to q-1). ), The state after the transition is X
i + 1 (2-2) If the pre-transition state is Bq or Cq, the post-transition state is B0. (2-3) If the pre-transition state is Eq or Fq, the post-transition state is E0. The front protection structure prevents accidental loss of synchronization. In the forward protection of this embodiment, the phase comparison output signal p of the phase mismatch content (f or b) input in the synchronization reference state B0 or E0
Hase is not considered to be an error, and it can be seen that protection is performed once for the phase mismatch that is input thereafter. In other words, even if there are two phase mismatches in the same direction, if there are q phase matches, the original synchronization reference state B0
Or it is returned to E0. Synchronization protection is in place. The number of stages related to front protection in this embodiment is referred to as front protection stage number 2 / q.

The above-described rear protection and front protection correspond to determining the following items as characteristics of the digital PLL circuit.

The above-described rear protection requires that the determination of phase coincidence be continued until the state of synchronization is reached and phase tracking is performed. Therefore, the number of protection stages (p + 1) determines the synchronization pull-in time and the pull-in range.

In the forward protection, the number of times of phase matching is required to be q in order to cancel the state of phase mismatch occurring during synchronization. However, even if the phase mismatch occurs again, it has an allowable range depending on the state.
Therefore, the value q in the protection stage number 2 / q determines the lock range.

As described above, when the output signal act from the active cycle detecting section 4 indicates a cycle other than the idle cycle (act
= A) has been described. Hereinafter, a state transition when the output signal act from the active cycle detection unit 4 indicates an idle cycle (act = e) will be described.

As described above, when the input signal input is CM
In the case of the I code, there is a vacant cycle in which there is no change point even with a normal input, and in that cycle, the output signal act indicates the vacant cycle (e). Further, even in a non-signal state such as before a packet arrives or after a packet ends, the output signal a
ct indicates an empty cycle (e). Therefore, it is necessary to identify these cases. Therefore, in this embodiment, as described above, the number of consecutive free cycles is managed (see FIGS. 7 and 11). Then, in the idle period, as shown in FIGS. 9 and 11, the state transition is made in consideration of the number of consecutive idle periods.

In FIG. 9, a cycle (a
ct = a), the idle period (ac
It is assumed that t = e). Here, the transition source state Xx in this idle cycle is represented by (i) the asynchronous reference state A0 or D0 (ii) other states A1 to Ap, B0 to Bq,.
1 to Fq.

When the transition source state Xx is (i), FIG.
, And transits to the same state A0 or D0 as shown in FIG. That is, when an idle cycle occurs in the asynchronous reference state (initial state),
Maintain that state. By this transition, the count values Ct1, Ct2 and Ct4 become 0, and the count value Ct
3 is the same as the previous state.

When the transition source state Xx is (ii), it can be further classified into two types indicated by symbols α and β in FIG.

(A) The case indicated by the symbol α is a case where an empty period occurs when the count value Ct4 is 0, 1, or 2, and the state transits to the same state as shown in FIG. That is, in this case, there is no change point, but the input signal inpu
This is the case where it can be determined that t continues normally, and therefore the state is maintained. Depending on the transition process at this time, the count values Ct1, Ct2, and Ct3 maintain the previous state, and the count value Ct4 is incremented by one.

(B) The case indicated by the symbol β is a case where an idle period occurs when the count value Ct 4 is 3, and as shown in FIG. 9, the asynchronous reference state (initial state) A0 or D0 Transition. The fact that the count value Ct4 is 3 indicates a protection state with respect to an empty cycle (act = e). At this time, if a signal act having an input change point (a) is generated, it follows the above-described FIG. When the transition is executed and the signal act having the content of the idle period (e) is generated, the state transits to the asynchronous reference state (initial state) A0 or D0 as described above. In short, if the interval between the changing points of the input signal input is an interval that appears when the code is normal or is within its protection range (T, 2T, 3T), the state other than the initial state is maintained. State A0 or D0
It returns to. When the state transits to the initial state A0 or D0, the count values Ct1, Ct2 and Ct4 become 0.
And the count value Ct3 becomes the same as the previous state.

FIG. 2 described above shows a timing extraction circuit to which the digital PLL circuit of the first embodiment is applied. In the preceding stage of this timing extraction circuit, transmission data from another network node is received. A bus receiver is provided. If the transmission distance between another network node and the network node is long, attenuation due to the cable is increased, and the output of the bus receiver is disturbed due to deterioration of the transmission data waveform. Therefore, the timing information signal timO from the digital PLL circuit is disturbed, and an error occurs in the received data. This is mainly due to the small DC bias provided at the input of the bus receiver. The DC bias is provided to prevent the output level from becoming unstable when there is no signal input, but this DC bias causes disturbance in the rising and falling phases when the input waveform is degraded, and the digital PLL circuit Erroneous timing playback.

Therefore, the input signal input is input to the digital PLL circuit of the first embodiment applied as a timing extraction circuit via a fixed equalizer for reducing disturbance of the output phase of the bus receiver. Like that.

According to the first embodiment, since the loop filter section 6 performs the state transition according to the backward protection method and the forward protection method, the above-described protection function can be performed even at the time of low level input. Thereby, the entire digital PLL circuit can be favorably operated.

Further, according to the first embodiment, the loop filter unit 6 performs state transition according to the backward protection method and the forward protection method, and the number of protection stages can be appropriately selected. Even in the case where characteristics are required, the characteristics can be satisfied by appropriately selecting the number of protection stages, and a short-time pull-in characteristic can be realized.

The number of backward protection stages p is 6, and the number of forward protection stages q of 2 / q is selected to be 7, the cable length between the network nodes (transmission devices) is about twice the specification, and the rear stage of the bus receiver. The state where a fixed equalizer is provided and a reception signal is input to the timing extraction circuit according to the first embodiment is set to 3
An experiment was conducted to transmit 700 packets, and the result was that the number of error packets was 0, thus confirming the effect described above.

Further, in the first embodiment, the state is appropriately classified to suppress the type of signal and the number of bits, and furthermore, since it is constituted by a counter, a flip-flop and a logic gate, it is easy to implement an LSI. Yes, this realizes high-density mounting and no adjustment, leading to mass production and low cost.

At the stage of trial manufacture, the digital PLL circuit of the first embodiment has an L level as a part of the timing extraction circuit.
The digital PLL circuit part was realized by SI and could be realized by a 0.85K gate. This LSI includes a CMI codec and a CPU peripheral circuit, and was realized as a single 132-pin PGA package with a 1.0 μm gate array.

(B) Other Embodiments (B-1) In the first embodiment, the input signal input
Is CMI-coded, but may be Manchester-coded or AMI-coded.

Input signal inpu according to Manchester code
In the digital PLL circuit to which t is input, the loop filter unit determines the idle period (act = e)
The state transition and the like may be executed according to the conditions and the like shown in FIG. 12 instead of FIG. 11 according to the first embodiment. In the case of the Manchester code, the value s in FIG.

Although the description of the Manchester code itself is omitted, the Manchester code is very similar to the above-mentioned CMI code. Is different. Therefore, the conditions and operations in the above-described state transition diagram of FIG. 9 relating to the idle cycle are changed according to the intervals of the change points that can actually occur, that is, according to the number of times of the maximum idle cycle when the input is valid. As shown in FIG.
Operation can be performed almost in the same manner as in the embodiment.

In the digital PLL circuit to which the input signal input according to the AMI code is input, the change point extracting unit (see reference numeral 1 in FIG. 2) has a different configuration from that of the first embodiment, and its loop filter unit is Empty cycle (ac
Regarding t = e), not in FIG. 11 according to the first embodiment,
It is necessary to execute state transition and the like according to the conditions and the like shown in FIG. In the case of the AMI code, the value s in FIG. 12 is (the maximum allowable number of consecutive 0s) +1.

As shown in FIG. 13, the AMI code takes one of three levels, which is different from the CMI code that takes one of two levels.
A CMI code can directly detect a change point between two levels, but an AMI code cannot do so. Therefore, for example, after a positive polarity input and a negative polarity input are obtained by a half-wave rectifier circuit for each polarity (not shown), each is input to the leading edge differentiating units 13 and 14 shown in FIG. The leading edge thus extracted is output as a change point extracted through the OR gate 15. In the change point extraction circuit shown in FIG. 14, even if the mark ratio of the AMI code is 100%, about 50% (FIG. 13B)
Indicates the case of 60%). In the latter case, a change point can be extracted by applying a positive polarity input and a negative polarity input to one leading edge differentiator after passing through an OR gate. In this case, the leading edge differentiator is Since only one is required, the configuration is simplified. If the mark rate is not 100%, the timing information signal (t
imO), the decoding conditions of the decode / latch unit (5) need to be adjusted.

In the AMI code, 0s may be continuous, and if 0s are continuous for a long time, phase information is lost. Therefore, the allowable number of consecutive 0s is determined. When determined in this way, the maximum interval between transition points when the input is normal is the maximum allowable zero continuous period. Therefore, as described above, the loop filter unit performs the idle cycle (act
= E), it is necessary to execute a state transition or the like according to the conditions and the like shown in FIG. 12 instead of FIG. 11 according to the first embodiment.

(B-2) The use form and application of the above embodiment are not limited, but they can be used as follows. The timing extraction circuit using the digital PLL circuit according to the first embodiment is used by being mounted on an interface board of a company LAN. Such a corporate LAN is
The ACK (acknowledge) method handles packets with flags before and after, and when the packet arrives, the digital PLL circuit of the first embodiment is used to extract the timing for taking in data.

A timing extraction circuit having a digital PLL circuit relating to Manchester codes and AMI codes is used by being mounted on an interface board for continuous transmission of data. As in the previous case, it is used for extracting timing for capturing data. Note that this type of device is called a transmission terminal device. In addition to the above, the present invention can be applied to a reading circuit of a magnetic tape or a magnetic disk, which needs to extract timing, or a receiving circuit including frequency fluctuation due to the Doppler effect from an artificial satellite.

(B-3) The digital PLL circuit according to the present invention may be used for purposes other than timing extraction. For example, the present invention can be applied to a case where signals of different frequencies following a certain signal are formed. Depending on the application device, a change point phase is always input, and the loop filter unit of the digital PLL circuit applied to such a device may not have the state transition execution function shown in FIG. Therefore, the change point extraction unit, the active period detection unit, and the like may not be provided by the digital PLL circuit.

(B-4) In the above embodiment, the case where the forward protection is 2 / q is shown, but r / q (r is arbitrary 3 or more)
May be forward protection. Further, the loop filter section may employ only one of the front protection and the rear protection.

[0088]

As described above, according to the present invention, in the state transition for phase control performed by the loop filter means, the backward protection or forward protection method employed in the frame synchronization circuit or the like of the transmission device or the like is used. Since the present invention is applied, even if the stability of the input signal to the digital PLL circuit is low, the protection function can be operated satisfactorily, and the pull-in time can be appropriately set by selecting the number of stages of the rear protection or the front protection. .

[Brief description of the drawings]

FIG. 1 is a diagram (part 1) illustrating a state transition by a loop filter unit according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of a digital PLL circuit according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a loop filter unit according to the first embodiment.

FIG. 4 is a timing chart of each part of the digital PLL circuit of the first embodiment.

FIG. 5 is a table showing definitions of input / output signals of a loop filter unit according to the first embodiment.

FIG. 6 is a table showing an input / output relationship of the phase comparison unit of the first embodiment.

FIG. 7 is a table showing the meaning of a counter in a loop filter unit according to the first embodiment.

FIG. 8 is a timing chart of each part of the loop filter unit of the first embodiment.

FIG. 9 is a diagram (part 2) illustrating a state transition by the loop filter unit of the first embodiment.

FIG. 10 is a table illustrating a relationship between a control state of a loop filter unit and a count value according to the first embodiment.

FIG. 11 is a table showing conditions and the like in an idle cycle of the loop filter unit of the first embodiment.

FIG. 12 is a table showing conditions and the like in an empty cycle of a loop filter unit according to another embodiment.

FIG. 13 is an explanatory diagram showing an AMI code.

FIG. 14 is a block diagram illustrating a change point extraction unit for an AMI code.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Change point extraction part, 2 ... VCO counter part (VCO means), 3 ... Phase comparison part (phase comparison means), 4 ... Active cycle detection part (active cycle detection means), 5 ... Decode / latch part, 6 ... Loop filter unit (loop filter means), A0: Reference state in the asynchronous state of the leading tendency state, A1 to Ap: Asynchronous state of the leading tendency state, B0: Reference state in the synchronized state of the leading tendency state, B1 to Bq , C1 to Cq: a synchronized state in a state of a tendency to advance, D0: a reference state in an asynchronous state of a state of a tendency to delay, D1 to Dp: an asynchronous state in a state of a tendency to delay, E0: a reference state in a synchronized state of a state of a tendency to delay , E1 to Eq, F1 to Fq: Synchronous states in a state of a tendency to delay.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-234420 (JP, A) JP-A-2-170722 (JP, A) JP-A-5-316383 (JP, A) JP-A-2- 149127 (JP, A) JP-A-63-280591 (JP, A) JP-A-5-218858 (JP, A) JP-A-62-73819 (JP, A) JP-A-2-174432 (JP, A) JP-A-6-309406 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7/06 H04L 7/033

Claims (6)

(57) [Claims] The phase comparison means obtains a phase difference signal between an input signal and a periodic signal output from the VCO means or a frequency-divided signal thereof, and provides the phase difference signal to a loop filter means. In a digital PLL circuit for making a transition to a new control state in accordance with the immediately preceding control state and forming a control signal for phase adjustment and giving the control signal to the VCO means to adjust the phase of the periodic signal, The signal indicates “delay”, “coincidence” or “advance”, and the loop filter means takes a “synchronous state” or “asynchronous state” as a control state, and changes from “asynchronous state” to “synchronous state”. The phase shift is performed according to the rearward protection method, and in the rearward protection state, the control signal for phase adjustment given to the VCO means is "no phase adjustment". LL circuit. 2. The phase comparison means obtains a phase difference signal between an input signal and a periodic signal output from the VCO means or a frequency-divided signal thereof and supplies the phase difference signal to a loop filter means. In a digital PLL circuit for making a transition to a new control state in accordance with the immediately preceding control state and forming a control signal for phase adjustment and giving the control signal to the VCO means to adjust the phase of the periodic signal, The signal indicates “delay”, “coincidence” or “advance”, and the loop filter means takes a “synchronous state” or “asynchronous state” as a control state, and changes from a “synchronous state” to an “asynchronous state”. In the forward protection state, the control signal for phase adjustment given to the VCO means is "no phase adjustment". LL circuit. 3. The digital PLL circuit according to claim 2, wherein the loop filter means receives the “lag” or “lead” phase difference signal in a reference state of “synchronization state”. , Output a control signal for phase adjustment of “delay” or “advance” to the VCO means and activate the forward protection function,
A digital PLL circuit that performs any one of the operations (i) to (iii). (i) When the number of times of “match” is (q−r) times (r <q) out of the q consecutive times of input of the phase difference signal after activation of the forward protection function, “synchronization state” And the control signal for phase adjustment given to the VCO means is "no phase adjustment". (ii) Without waiting for the q consecutive input of the phase difference signal after the activation of the forward protection function, first, the difference between the number of input of the phase difference signal of “delay” and “advance” is r1 (however, r1 ≤
r), and thereafter, when the “lag” or “advance” phase difference signal becomes r2 times (where r2 ≦ r),
The state is shifted to the “asynchronous state” and the control signal for phase adjustment given to the VCO means is “delayed” or “advanced”. (iii) The number of input of the phase difference signal after the activation of the forward protection function becomes (q−r) while the number of times of the input of the phase difference signal of “delay” and “advance” is less than r 1. Or the number of times the difference has reached r 1, and then the number of inputs of the “lag” or “advance” phase difference signal is r
If the number of times of input of the phase difference signal after activation of the forward protection function reaches q times in less than two times, the reference state of the “synchronous state” is returned and the control signal for phase adjustment given to the VCO means is returned. "No phase adjustment". 4. The digital PLL circuit according to claim 1, wherein each of the “synchronous state” and the “asynchronous state” controlled by the loop filter means is advanced from the aspect of phase tendency. The loop filter means shifts to another state of the same phase tendency when shifting between the "synchronous state" and the "asynchronous state". Digital PLL circuit. 5. The digital PLL circuit according to claim 1, wherein each of the “synchronous state” and the “asynchronous state” controlled by the loop filter means is advanced from the phase tendency. The loop filter means is classified into “synchronous state” or “asynchronous state” in “leading state”.
When the above-mentioned phase difference signal of “delay” is given, the state is shifted to “synchronous state” or “asynchronous state” of “state of delay”, and “synchronous state” of “state of delay” Or "asynchronous state"
Wherein when the phase difference signal of “advance” is given, the phase shifts to a “synchronous state” or an “asynchronous state” of a “progressive state”. 6. The digital PLL circuit according to claim 1, wherein the input signal input to said phase comparison means has a phase reference point for comparison in a current processing cycle. An active period detecting means for detecting whether or not the phase reference point is detected, wherein the loop filter means performs the process according to any one of claims 1 to 5 when "there is a phase reference point"; In the case of "None" and the number of consecutive times is less than s, it stays in the "synchronous state" or "asynchronous state" immediately before, and in the case of "No phase reference point" and the number of consecutive times is s A digital PLL circuit which shifts to a reference state of "asynchronous state" when the number of times is equal to or more than one.