JP3103174B2 - Memory access device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device connected to a bus connecting a central processing unit and a memory device and capable of accessing the memory device independently of the central processing unit. Improve the performance and reliability of the entire computer system by forcibly terminating or suspending the address pipeline when there is a request from inside or outside to stop or terminate memory access by address pipeline control. Memory access device capable of

[0002]

2. Description of the Related Art In recent years, the operating frequency of a memory access device such as a microprocessor has been considerably increased, and a higher speed of memory access is also required. As an external memory, if it is a static RAM (hereinafter abbreviated as SRAM), there is a memory having a response speed that satisfies the operating frequency of a high-speed memory access device. In such a case, it is inappropriate as a main storage device and can only be used as a cache memory or a local small-capacity memory at present.

Therefore, a dynamic RAM (hereinafter abbreviated as DRAM) is used as a main storage device, these are divided into independently operable modules called banks, and the main storage device is operated in parallel by all banks. It is common practice to employ an interleave scheme that improves the effective speed of the interleave.

FIG. 13 shows four banks BANK as an example.
1 shows a configuration diagram of a memory device 3 divided into 0 to BANK3. For example, if the lower two bits of the address information from the memory access device 101 indicate the bank and the upper bits indicate the address in each bank, if the address of the upper bit is sent to the address latch of each bank at the same time, Operate in parallel to access the contents of consecutive addresses within one memory cycle, and a speed four times as high can be obtained.

[0005] As a means for improving the performance of a computer system, an address pipeline method for speeding up memory access by advancing addresses by a predetermined number without waiting for a data response signal from an external memory. There is.

FIG. 14 is a timing chart of an address pipeline for prefetching four addresses in the memory device 3 of FIG. It is assumed that the memory device 3 requires four clocks as an access time for one data, and after four clocks elapse after each bank address is determined by the address output from the memory access device 101 and four clocks elapse. The address data is obtained.

In this case, an address is continuously output from the memory access device 101, and after four clocks elapse, data of the corresponding address can be obtained continuously. As described above, the address pipeline is a technique for making the bank-divided DRAM having a relatively low access speed appear faster to shorten the access time, and is generally used as an extremely effective technique.

FIG. 15 shows an example of a system configuration in which the memory access device 101 for performing such address pipeline control and the central processing unit 2 (hereinafter abbreviated as CPU) are connected on the same bus. In FIG. 1, the system includes a memory access device 101, a CPU 2, and a memory device 3, and these components are connected to a bus 5.

The memory access device 101 is a device capable of accessing the memory device 3 like the CPU 2,
For example, a device corresponding to a bus slave when the CPU 2 is a bus master, specifically, an arithmetic processor or the like. Since the CPU 2 and the memory access device 101 use the same bus 5, when the memory access device 101 wants to access the memory device 3, it issues a bus right request to the CPU 2 and returns a bus signal when a response signal to the request is returned. The access to the memory device 3 is performed assuming that the right has been acquired. In FIG. 15, HREQ # (Hold Request) is a bus right request signal output from the memory access device 101 to the CPU 2, and HACK # (Hold Acknowledge).
ege) is a response signal to it.

When the memory access device 101 recognizes that it has acquired the bus right, it normally performs the necessary memory access continuously. During that time, the memory access device 101 continuously acquires the bus right, and performs memory access by address pipeline control.

FIG. 16 is a timing chart for explaining this operation. This example is an example of an address pipeline that precedes four addresses, and shows a data read cycle of eight bus accesses.

In FIG. 1, CLK is a clock signal for driving the system, Address (O) is an address output of the memory access device 101, R / W # (O) is a read / write signal, and Data (I) is a memory access device 10.
DC # (I) is a signal output from the memory side and is an access response signal indicating that data access is completed. As a signal notation, a signal with a # added to the signal name is a negative logic signal, and “I” in parentheses indicates an input signal, and “O” indicates an output signal.

First, when the memory access device 101 is a CPU
2 to output a bus right request signal HREQ # (O) to request a bus right, and a response signal HACK in response to the request.
When # (I) is asserted, access to the memory device 3 is started. That is, the address output Address (O)
, A1, A2,... Are output successively, and after four clocks, the data of each address is output as D1, D2,... On the data input Data (I).

As shown in FIG. 16, the operation of the address pipeline is roughly divided into the following three processes. Address advance processing Address output and data input / output processing Data input / output processing The address pipeline is normally assumed to be accessed continuously, and high performance can be realized by performing continuous access. However, in the following cases, it is necessary to forcibly end or interrupt the address pipeline. However, the conventional memory access device 101 does not have such a function, and as a result, the entire computer system This leads to a decrease in the performance and reliability of the device. (1) When the CPU 2 Needs to Use the Bus 5 Immediately The CPU 2 in recent years is provided with a cache and a store buffer as means for improving performance, and usually accesses these. Proceed with the process. Therefore,
Even if the other memory access device 101 has secured the bus right of the bus 5 and the CPU 2 cannot acquire the bus right, the CPU 2 performs the processing for the cache and the store buffer, so that the processing of the CPU 2 waits. There is no.

However, if the cache write control method is write-through control in which the block to be written is always in both the cache and the memory device 3 when the block to be written is in the cache, when the CPU 2 rewrites the contents of the cache, In order to maintain consistency between the contents of the cache and the contents of the memory device 3, the rewritten contents in the cache must be immediately written to the memory device 3. Further, even in the copy-back control in which the content of the memory device 3 is updated by transferring the block data to the memory device 3 when the updated block is to be replaced and written only in the cache, Is replaced by the memory device 3
Must be written to Furthermore, even when the store buffer of the CPU 2 becomes full, such information must be stored in the memory device 3.

If the CPU 2 cannot access the memory device 3 as described above, the CPU 2 waits for the next process until the CPU 3 can access the memory device 3. That is, in such a case, the CPU 2 outputs a bus right request signal GBR # (Global Bus Request) for memory access, but the memory access device 10 performing the address pipeline.
If 1 has no means for receiving this signal and no means for forcibly releasing the bus 5, the CPU 2 keeps outputting the bus right request signal GBR # and waits for the next processing. Making the CPU 2 wait in this manner leads to a decrease in the performance of the entire system. (2) Bus right response signal HACK # due to malfunction of bus 5
Is negated when the memory access device 101 has acquired the bus right when the bus right request signal HREQ # (O) is asserted and the response signal HACK # (I) is asserted in response to the assertion. When both signals are asserted, the memory access device 101 can execute the bus access assuming that the bus right has been acquired.

However, the memory access device 101
Has acquired the bus right, the bus right response signal H
When ACK # (O) is negated, the response signal HACK # (I) is not asserted even though the bus right request signal HREQ # (O) is asserted.
It must be recognized that "the bus has not been acquired." If the memory access device 101 has no means for promptly interrupting the address pipeline, the bus access will be continued even though the device does not have the bus right. It is expected to cause a bus conflict with the signal, resulting in a decrease in the reliability of the system. (3) When an exception occurs in the memory access device 101 For example, when the memory access device 101 performs an operation such as a floating point internally in parallel with the memory access operation and stores the result in the memory device 3 That is, when an exception such as overflow or invalid operation occurs during the operation.

In this case, the address pipeline should be interrupted promptly and the CPU 2 must be notified that an exception has occurred.
Without such means, the bus access will be continued while an exception has occurred, and the notification of the occurrence of the exception to the CPU 2 will be delayed, and the error recovery processing will be delayed.
Continuing the process while the exception has occurred as described above leads to a decrease in the reliability of the system. (4) When the Memory Access Device 101 Performs Address Translation For example, the translation table TLB (Tran) for the memory access device 101 to translate a logical address into a physical address
slation Look aside Buffer), that is, when a DLB (Dynamic Address Translation) function is provided, when a TLB miss occurs, the address pipeline is interrupted to update the translation table TLB. Some means for performing the entry cycle is required. (5) When a Bus Exception Occurs For example, when the memory access device 101 is performing a bus access, an external circuit detects an abnormality such as a bus timeout, a parity error, or an access request to a prohibited device. In that case, the address pipeline must be terminated immediately. Continuing processing with an exception occurring reduces the reliability of the system.

[0019]

As described above, in the conventional memory access device, (1) when the CPU must immediately use the bus (2) a bus right response signal due to a malfunction of the bus Is negated. (3) When an exception occurs inside the memory access device. (4) When the memory access device performs address conversion. (5) When a bus exception occurs, the address pipeline is forcibly terminated. Alternatively, the computer system cannot be interrupted, and as a result, there is a problem that the performance and reliability of the entire computer system are reduced.

The present invention solves the above problems,
An object of the present invention is to provide a memory access device capable of forcibly terminating or interrupting an address pipeline when a request for interruption or termination of memory access by address pipeline control is received from inside or outside the memory access device. .

[0021]

[Means for Solving the Problems] In order to solve the above-mentioned problems
First, a first feature of the present invention is that a central processing unit and a memory device are provided.
And connected to the central processing unit via the bus
The central processing unit according to a bus right request signal (HREQ #).
Returns a bus right response signal (HACK #) from the
To address pipeline control by address advance
Memo for performing memory access to the memory device
In the reaccess device, an address for memory access
Address generating means for generating the address, and the generated address.
Address control means for outputting an address to the bus;
A bus request signal (BRL #) output from the processor and
At the completion of memory access to one address
Access response signal (DC #) output from the memory device
And the bus right request signal (BRL #) and the
Access response signals (DC #) are all asserted
Detected, the data corresponding to the number of address advance
After the data input / output processing is completed,
Bus to the central processing unit
Control means for negating the right request signal (HREQ #)
It is to be.

According to a second feature of the present invention, in the memory access device according to the first aspect, the control means includes
During memory access by address pipeline control,
Bus right response signal (HACK #) from the central processing unit
Is negated due to a malfunction of the bus,
After completing the data input / output processing according to the number of
Interrupt memory access by address pipe control
A bus right request signal (HREQ #) to the central processing unit
This is to have control means for negating.

[0023] A third aspect of the present invention, a memory access device according to claim 1, wherein the memory access instrumentation
Detects an internal exception and generates an internal exception signal (IERRX)
Output exception detecting means, and the control means
During memory access by dress pipeline control,
When an internal exception signal (IERRX) is received,
After completing the data input / output processing according to the number of
Memory access by the address pipeline control
The bus request signal (HRE) to the central processing unit is terminated.
Q #) is negated.

According to a fourth feature of the present invention, in the memory access device according to claim 1, the address generating means is provided.
Is a translation table that translates logical addresses into physical addresses.
And a memory access by the conversion table.
Address and generate the address in the conversion table.
Entry request when there is no physical address to be translated to
And outputs a signal (TLBREQX).
During memory access by address pipeline control
Receives the entry request signal (TLBREX)
Data input / output processing according to the number of address advance
After the completion of the
Suspending re-access and requesting bus right to the central processing unit
Negating the signal (HREQ #).

According to a fifth feature of the present invention, in the memory access device according to the first aspect, the control means includes one control unit.
When the memory access to the address of
Access response signal (DC #) output from the
Bus error signal output from the bus when an exception occurs
(BERR #) and the address pipeline
During the memory access by control, the bus error signal
(BERR #) is asserted,
Immediately when the response signal (DC #) is detected at the time of assertion,
Memory access by the address pipeline control
Is provided.

[0026]

[0027]

[Action] In the memory access device of the first aspect of the present invention, as shown in FIG. 1, the control means 14, address pipelining
From the central processing unit 2 during memory access by
Of the access right signal DC #
Received at the time of assertion,
After completing the data input / output processing according to the number,
Interrupt memory access by pipeline control and
Negates the bus request signal HREQ # to the logical device 2
I am trying to do it.

Therefore, the central processing unit 2 immediately switches the bus 5
When it is necessary to use the bus right request signal B
Address pipeline without waiting while outputting RL #
Can be forcibly interrupted and proceed to the next process.
As a result, the performance of the entire system can be improved.

Further, in the memory access device according to the second feature of the present invention, as shown in FIG. 1, the control means 14 controls the bus right response signal HACK # from the central processing unit 2 during the memory access by the address pipeline control. Is a malfunction of bus 5
If negated by
After completing the corresponding data input / output processing, the address pipeline
In this case, memory access due to in is interrupted.

Therefore, a bus right response occurs due to a malfunction of the bus 5.
If the signal HACK # is negated, the address
The pipeline can be forcibly interrupted,
Access to signals output from other devices on the bus 5
It does not cause bus contention and consequently
It is possible to improve the reliability of the system .

In the memory access device according to the third feature of the present invention, as shown in FIG. 1, the control means 14 controls the internal exception signal during the memory access by the address pipeline control.
No. IERRX is received.
After completing the data input / output processing according to the number,
End memory access by pipeline control, and
Negates the bus request signal HREQ # to the logical device 2
I am trying to do it.

Therefore, in the memory access device 101,
Forcing an address pipeline if an exception occurs
Can be terminated automatically and the bus
Error recovery processing due to continued access
Does not occur, and as a result, the reliability of the system can be improved.

In the memory access device according to the fourth aspect of the present invention, as shown in FIG. 1, the control means 14 controls the conversion table 15 during the memory access by the address pipeline control.
Receives the entry request signal TLBREQX for
Data input / output processing according to the number of address advance
After completion, memory access by address pipeline control
To suspend the process.

Therefore, when the memory access device 1
When performing the conversion, the physical address to be converted is stored in the conversion table 15.
Force address pipeline if no dress
Can be interrupted.

In the memory access device according to the fifth aspect of the present invention, as shown in FIG. 1, the control means 14 controls the bus from the bus 5 during the memory access by the address pipeline control.
The access signal indicates that the error signal BERR # is asserted.
If the response signal DC # is detected when asserted,
Memory access by address pipeline control
It is going to end .

Therefore, when a bus exception occurs,
The dress pipeline can be forcibly terminated,
It is possible to improve the reliability of the system.

[0037]

[0038]

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before concretely describing an embodiment according to the present invention, a control method adopted by the memory access device of the present invention for the five cases pointed out as problems of the prior art will be described. .

As a premise, the memory access device 1 according to the present invention has, for example, a system configuration as shown in FIG.
It is assumed that the same address pipeline control as that of the conventional memory access device 101 is performed. In FIG. 1, the system includes a memory access device 1, a central processing unit 2 (hereinafter referred to as C
PU) and a memory device 3, and these components are connected to a bus 5.

When the memory access device 1 wants to access the memory device 3, it requests the CPU 2 for a bus right with a bus right request signal HREQ #, and when the response signal HACK # is returned, returns the bus right. The access to the memory device 3 is performed assuming that it has been acquired.

The control method adopted by the memory access device 1 for performing the address pipeline for the five problems will be described below. (1) When the CPU 2 has to use the bus For example, the contents of the cache in the CPU 2 and the memory device 3
When transferring the block data to the memory device 3 and updating the content of the memory device 3 in order to maintain consistency with the content of the memory device 3, the CPU 2 requests the bus right request signal GBR # (Global Bus Request) to acquire the bus right. ) Is asserted. At this time, the memory access device 1 must receive the signal GBR #, temporarily suspend the address pipeline, and release the bus right. Therefore, first, the memory access device 1 transmits the bus right request signal GBR # to the bus right release signal B
An input terminal for receiving as RL # (Bus ReLease) is required.

It should be noted that when releasing the bus right, the bus right should not be simply released just because the bus request signal GBR # is detected to be asserted. The address pipeline is a mode in which an address is advanced, and data processing for the advanced address must always be performed. In other words, from the memory device 3 side, the access response signals DC # remain asserted for the number of accessed data. Therefore, when releasing the bus right, the response of the data to the first-mentioned address must be performed. You have to wait for the signal
Correspondence between the number of output addresses and the number of data to be processed cannot be maintained, which causes a malfunction.

Accordingly, the bus right release signal BRL # is detected when the access response signal DC # is asserted,
That is, if the bus right release signal BRL # is asserted when the access response signal DC # is asserted,
Perform the processing of (1) to (4). As can be seen from FIG. 16, the cycle in which the access response signal DC # is asserted is the cycle of address output, data input / output processing (in the figure), and data input / output processing (in the figure) in the address pipeline operation. It is. (1) The assertion of the bus right request signal GBR # is detected by the bus right release signal BRL #. (2) When it is detected that the bus right release signal BRL # is asserted and the access response signal DC # is asserted, (a) if the cycle is for address output and data input / output processing, the address output is immediately performed. The operation is suspended, and the process transits to the data input / output processing cycle.

(B) If the cycle is a data input / output processing cycle, no operation is performed because no address has been output. (3) When the access response signal DC # of the last data corresponding to the address advance is detected, the address pipeline is interrupted and the bus right request signal HREQ # is negated. (4) Even if the bus right release signal BRL # is negated, if there is still a memory access request, the bus right is requested again by the bus right request signal HREQ #, and a response signal HACK # is returned. Resume bus access. (2) When the bus right response signal HACK # is negated due to a malfunction of the bus Even when the bus right response signal HACK # is negated for some reason during the bus access, the address is also the same as in (1). The address pipeline may be interrupted after the processing of the preceding data is completed. Therefore, also in this case, the bus right response signal HACK # is detected together with the access response signal DC #, and the same processing as (1) is performed.

However, the difference from (1) is that the bus right request signal HREQ # is not negated even when the last data access response signal DC # is detected. The reason for this is that the bus right response signal HACK # is negated due to some malfunction and is not negated because the CPU 2 wants to use the bus 5. However, the bus right response signal HACK # is negated, so that the bus right is released. If the bus right request signal HREQ # is kept asserted, the bus access can be immediately resumed when the bus right response signal HACK # is asserted again. (3) When an Exception Occurs Inside the Memory Access Device 1 In this case, it is meaningless to perform a bus access while the exception has occurred internally, so the address pipeline must be terminated immediately. Must.

In this case, as in (1) and (2), it is necessary to make the correspondence between the number of output addresses and the number of data corresponding to the output addresses. End the pipeline processing. That is, the end is when the access response signal DC # corresponding to the last data is detected.

The difference from (1) and (2) when an internal exception occurs is that the internal exception can occur at any time irrespective of the external bus access. Irrespective of whether signal DC # is asserted or not.

That is, it may occur not only in the cycle of the address output and data input / output processing (see FIG. 16) but also in the cycle of the address advance processing (see FIG. 16). In this case, it is necessary to terminate the output of the address even in the cycle in which the address is advanced, and to process the data for the number of the advanced addresses. Therefore, in this case, the address advance cycle (FIG. 16)
) To data input / output processing cycle (see FIG. 16).
Will be transitioned to

After detecting the access response signal DC # corresponding to the last data, the bus right request signal HREQ # is negated because there is no need to acquire the bus right. That is, in this case, the bus is not restarted because the occurrence of the exception is the cause of the forced termination. (4) In the case where the memory access device 1 performs an address conversion When a TLB miss occurs in the conversion table TLB for converting a logical address to a physical address, there is no address to be output, and thus the conversion table TLB is used.
Must be interrupted to obtain an entry address to the translation table TLB from the external memory device 3 in order to update.

In this case as well, the TLB miss is an internal process in the memory access device 1 and may occur at any time. Therefore, as in (3), the transition from the address advance cycle to the data input / output cycle is performed. There can be.
The difference from the case (3) is that after the entry into the translation table TLB is completed, the address pipeline is restarted again.

In this case, since a series of bus access operations is performed, the bus right may be obtained, and the bus right request signal HREQ # is not negated. (5) When a Bus Exception Occurs For example, when the memory access device 1 is performing a bus access, an external circuit detects an abnormality such as a bus timeout, a parity error, or an access request to a prohibited device. In that case, the address pipeline must be terminated immediately. As means for detecting the occurrence of these bus exceptions, a bus error signal BERR # (Bus Erro
r) Input terminal is provided.

The bus error signal BERR # is detected when the access response signal DC # from the memory device 3 is asserted. This bus exception is an exception response to the memory access device 1 and has nothing to do with the advance of the address. Therefore, if a bus exception occurs,
The bus access may be immediately terminated without waiting for the data processing for the first address. The reason is that if a bus error occurs, the memory side will no longer assert DC.

To summarize the above, in order to interrupt or terminate the address pipeline, it is necessary to (a) send the bus right release signal BRL # in (1) or the bus right response signal HACK # in (2) from the CPU side. Regarding the external factors described above, these signals may be detected together with the access response signal DC # in a cycle for detecting the access response signal DC # so that the memory access address and the number of data coincide. (B) An internal response such as an internal exception in (3) or a TLB entry request in (4)
In the cycle for detecting C #, it is necessary to detect only these factors together with the access response signal DC #, and in the cycle for address advance processing, only these factors are required. (C) An external factor from the memory device 3 such as the bus exception in (5) may be detected in a cycle for detecting the access response signal DC #.

Next, an embodiment according to the present invention employing the above-described control method will be described with reference to the drawings. FIG. 3 is a configuration diagram of a memory access device according to one embodiment of the present invention.

In the figure, the memory access device 1 of the present embodiment includes a bus access request unit 21 and an internal exception generation unit 3
1, a timing sequencer 41, a bus right control unit 51, an address control unit 61, and a data control unit 71.

In FIG. 3, the memory access device 1
Is expressed as --X. That is, the bus right request signal HREQ # is HREQX, the bus right response signal HACK # is HACKX, and the bus right release signal BRL.
# Is BRLX, access response signal DC # is DCX, and bus error signal BERR # is BERRX. Also, IB
RX is a bus access request (Internal Bus Request) signal, IERRX is an internal exception (Internal ERRor) signal, T
LBREQX is a TLB entry request (TLB REQuest) signal.

Hereinafter, each component will be described. (A) Bus Access Request Unit 21 FIG. 4 shows a circuit configuration diagram of the bus access request unit 21.

Since the operand length differs for each instruction,
The number of bus accesses also changes for each instruction processing. The bus access request unit 21 holds the number of times of bus access in the bus access number register 22. The basic operation of the bus access request unit 21 is that after the flip-flop 27 is set by an instruction or a start request signal START from a predetermined register. Until the bus access becomes 1, the bus access request signal IB which is the output of the flip-flop 27
Assert RX. This bus access request signal IB
When RX is asserted, each component of the memory access device 1 is activated.

As described above, the number of bus accesses held in the bus access number register 22 is usually set to a value indicating that the address output from the address control unit 61 has been performed each time the decrementer 23 performs the bus access. It is decremented by one by the access signal AOUT, and immediately before the end of the bus access (decrementer 2
3 outputs = 1), the output of the comparator 24 is asserted,
The flip-flop 27 is reset to negate the bus access request signal IBRX.

The flip-flop 27 is activated by the internal exception signal IERRX when the internal exception generator 31 detects an internal exception, and by the bus error signal BERRX when the access response signal DCX is asserted when a bus exception occurs. Reset the bus access request signal I
BRX is negated. In the case where the CPU 2 has to use the bus or in the case of an entry request to the conversion table TLB, the bus access is resumed after these processes are completed, so that the bus access request signal IBR
Do not negate X. (B) Internal Exception Generating Unit 31 FIG. 5 shows a circuit configuration diagram of the internal exception generating unit 31.

The internal exception signal IERRX is applied to each of the arithmetic units 32-1 to 32-32 such as an adder, a multiplier and a divider.
An exception generated in n, for example, a floating-point operation exception such as division by zero detected by the divider or an invalid operation detected by each operation unit, and the like are ORed by the gate circuit 33.
The state of the internal exception signal IERRX is held in the latch 34 until the next start, that is, until the bus access request signal IBRX is output. (C) Timing Sequencer 41 In the timing sequencer 41, a portion corresponding to the bus access state of each memory access device 1 is configured by a latch, and the transition condition is generated and controlled by a logic circuit. In this case, it is assumed that an address pipeline is used to advance four addresses.
, Ie, address advance processing (P
A), address output and data input / output processing (PA
D) and the data input / output processing (PD), the state of the bus access of the memory access device 1 is PA1 to PA
4, PAD, PD1 to PD4, and conversion table TLB
Entry state TLBE and idle state Ti
have. As described above, the number of states of the address advance processing PA and the data input / output processing PD coincide with the number of addresses advance. Timing sequencer 41
6 is shown in FIG. In the figure, LTi, L
PA1 to LPA4, LPAD, LPD1 to LPD4, and LTLBE are states Ti, PA1 to PA4, respectively.
Latches for holding PAD, PD1 to PD4, and TLBE, ti, pa1 to pa4, pd1 to pd4, and tl
be is a latch LTi, LPA1 to LPA4, respectively.
Output signals of LPD1 to LPD4 and LTLB, CL1
CL22 to CL22 are condition determination logic circuits, and OR1 to OR6 are OR circuits.

As described above, the state machine includes the latches LTi, LPA1 to LPA1 corresponding to the bus access state.
4, LPAD, LPD1 to LPD4, and LTLBE are prepared, the transition conditions COND1 to COND8 are created by the condition generation logic circuit 42, and the respective condition determination logic circuits CL1 to CLD8 are prepared.
The state is determined by CL22, and the state (latch) to be changed is determined depending on whether the condition is satisfied or not. Therefore, the latch of each state in the state machine always operates only by the clock signal CLK, and a certain latch LTi, LPA1 to LPA4, LPAD, LPD1 to LPD1.
LPD4 and output ti, pa1 to pa of LTLBE
4, pd1 to pd4, and tlbe are state signals, and when these signals are asserted, the buses remain in their states Ti, PA1 to PA4, PAD, PD1 to PD
4 and TLBE.

The transition conditions of the control signals COND1 to COND7 generated by the condition generation logic circuit 42 are generated under the following conditions. To simplify the notation, symbols （(indicating that the signal is asserted), ● (indicating that the signal is negated), and (logical product) are used.

COND1 = BUSGX ○ COND2 = IBRX ○ and IERRX ● and TLBREQX ● COND3 = DCX ○ and IBRX ○ and BRLX ● and HACKX ○ and IERRX ● and TLBREQX ● and BERRXD. And COND6 COND6 = DCX and BERRX COND7 = DCX and BERRX COND8 = TLBREQX First, the idle state T when no bus access is performed.
i is repeated, and the memory access device 1 takes the bus right to start the bus access, that is, the bus right control unit 51
Is asserted, the control signal COND1 for the condition determination logic circuit CL1 is asserted, and the state transits to the state PA1.

In the state PAi (i = 1 to 4), when there is no internal exception, there is no entry request of the conversion table TLB, and when the bus access request signal IBRX is asserted, the control signal COND2 is asserted and the state PAi is asserted. PA
The state transits to i + 1 (PAD in the case of PA4). Otherwise, the state transits to the state PDi.

In state PAD, access response signal DCX
Is negated, or the access response signal DC
Even if X is asserted and the bus access request signal IBRX is asserted, if the causes of the problems (1) to (5) do not occur, the control signals COND4 and COND
D3 is asserted and the state PAD is repeated. When the access response signal DCX is asserted and the bus error signal BERRX is asserted, the control signal COX
ND6 is asserted and transits to the idle state Ti. Further, under conditions other than the above, the control signal CON
D5 is asserted and transits to state PD4.

In state PDi, access response signal DCX
Is negated, the control signal COND4 is asserted, the state PDi is repeated, and the access response signal DCX is asserted and the bus error signal BERR is asserted.
When X is negated, the control signal COND7 is asserted and transits to the state PDi + 1. When the access response signal DCX is asserted and the bus error signal BER
When RX is asserted, the control signal COND6 is asserted and transits to the idle state Ti.

In other words, if an internal exception or a translation table TLB entry request occurs during the cycle of the address advance processing, it is necessary to immediately proceed to the data input / output processing cycle. Data input / output processing cycle status PD corresponding to the number
Transition to i. Also, for example, when the number of bus accesses is smaller than that of the address advance, the bus access request signal IBRX becomes negated during the cycle of the address advance processing. The state transits to the state PDi of the data input / output processing cycle.

In the cycle of address output and data input / output processing, the bus access request signal IBR is normally
While X is asserted, the state is repeated, and when the bus access request signal IBRX becomes negated, the process proceeds to the cycle of data input / output processing.
Even if BRX is asserted, the cycle (state PA
In D), when it is detected that the bus right response signal HACKX is negated or the bus right release signal BRLX is asserted, the state immediately transits to the data input / output processing cycle (state PD4).

In the cycle of address output and data input / output processing (state PAD) and the cycle of data input / output processing (state PDi), when the access response signal DCX is asserted, the bus error signal BERRX is asserted. In this case, a transition is made to the idle state Ti that does nothing. (D) Bus Right Control Unit 51 FIG. 7 shows a circuit configuration diagram of the bus right control unit 51.

The bus right control unit 51 includes a flip-flop 58, and asserts / negates the bus right request signal HREQX by set / reset. Further, the gate circuit 59 calculates the logical product of the bus right request signal HREQX and the bus right response signal HACKX to obtain the bus right request signal HACKX.
If the bus right response signal HACKX is asserted during REQX assertion, it is considered that the bus right has been acquired, and the bus right acquisition signal BUSGX is generated to be asserted.

The condition for asserting the bus right request signal HREQX is that the bus access request signal IBRX is asserted when the bus right release signal BRLX is negated and the bus right response signal HACKX is negated.

The condition for negating the bus request signal HREQX is that the bus access request signal IBRX is asserted when the access response signal DCX is asserted and the state signal pd1 representing the last cycle output by the timing sequencer 41 is asserted. When the bus release signal BRLX becomes asserted, or when an internal exception is detected and the internal exception signal IERRX is asserted, or the state signals pda and pa1 to pa4 output from the timing sequencer 41 are asserted. That is, when the memory access device 1 is in the state of detecting the access response signal DCX, the access response signal DCX is asserted and the bus error signal BERRX is asserted.

The bus release signal BRLX is thus obtained.
Is the bus request signal HREQ by assert / negation.
X is negated / asserted, but the bus right response signal HA
CKX is asserted when the bus right response signal HACKX is negated when the bus right request signal HREQX is asserted.
The bus request signal HREQX is not negated. (E) Address Control Unit 61 FIG. 8 shows a circuit configuration diagram of the address control unit 61.

The address control unit 61 normally stores the logical address set in the logical address register 81
The adder 83 adds the value to the offset value of the offset register 82 and the result is used as an intermediate address in the register 84
Is converted to a physical address in the conversion table TLB, or set as it is in the physical address register 87 as a physical address, and is selected by the selector 63 and output to the bus as an address output Address (O).

At this time, the output of the output unit 64 is controlled by the state signal group CON2 or P from the timing sequencer 41.
a1 to Pa4 and the access response signal DCX. When the output address is ready, the state signals PA1 to PA4 and the access response signal DCX are asserted in the address advance processing cycle, and the state signal P is output in the address output and data input / output processing cycle.
Address output is performed by assertion of AD and access response signal DCX.

When a TLB miss occurs in the conversion table TLB at the start of or during bus access, the TLB entry request signal TLBREQX is asserted to notify the timing sequencer 41 to interrupt the address pipeline. . When entering the TLB entry cycle (state TLBE), the address conversion table 8
6 to the memory device 3 where the address to be entered in the conversion table TLB is stored, that is, TL
A B entry address is generated, a bus access is performed in the same manner, and the contents of data corresponding to the address are entered into the conversion table TLB via the data bus.

At this time, the output of the output unit 64 is controlled by the state signal tlbe from the timing sequencer 41, and the address is output by asserting the state signal tlbe. (F) Data Control Unit 71 As shown in FIG. 9, the circuit configuration of the data control unit 71 includes an input unit 72 and an output unit 73, and is controlled by the state signal group CON3 and the access response signal DCX from the timing sequencer 41. Have been. The state signal group CON3 includes a state signal pad indicating an address output and a data input / output cycle and state signals pd1 to pd4 indicating a data input / output cycle.

Next, operations performed by the memory access device 1 in the memory access device 1 of the present embodiment for the above-mentioned five problems (1) to (5) will be described. (A) Regarding external factors from the CPU side, such as the bus right release signal BRL # in (1) and the bus right response signal HACK # in (2), the operation when the CPU 2 has to use the bus FIG. 10 shows a timing chart to be described.

In this case, the access response signal DC # is always detected in a cycle for detecting the access response signal DC # so that the memory access address matches the number of data.
These signals are detected together with #. At this time, if the cycle is the cycle of the address output and the data input / output processing, the address output is immediately interrupted and the process transits to the cycle of the data input / output processing. When the access response signal DC # of the last data D5 for the address advance is detected, the address pipeline is interrupted and the bus right request signal HREQ #
To negate. Even if the bus right release signal BRL # is negated, if there is still a memory access request,
The bus right is again requested by the bus right request signal HREQ #, and the bus access is resumed when the response signal HACK # is returned.

Also, when the bus right response signal HACK # is negated due to a malfunction of the bus, after detecting the final data access response signal DC #, the bus right request signal HREQ # is not negated. It is. FIG. 11 shows a timing chart for explaining the operation when an exception occurs in the memory access device 1 (b) Internal exceptions such as (3) internal exception and (4) TLB entry request.

The figure shows a case where it is detected that the internal exception signal IERRX (inside) is asserted in the address advance processing cycle. In this case, the address advance is interrupted immediately and the last data D2 is output. After detecting the corresponding access response signal DC #, the bus right request signal HRE
Negate Q #. That is, in this case, the bus is not restarted because the occurrence of the exception is the cause of the forced termination.

Also, when the memory access device 1 performs address translation, it is necessary to restart the address pipeline again after the entry into the translation table TLB is completed and to not negate the bus right request signal HREQ #. And so on. FIG. 12 is a timing chart for explaining an operation when a bus exception occurs, such as (c) a bus exception in (5) relating to an external factor from the memory device 3 side.

In this case, the bus error signal BERR # is detected in the cycle for detecting the access response signal DC #. This bus exception is an exception response to the memory access device 1 and is irrelevant to the advance of the address or the like.
The bus access is immediately terminated without waiting for the data processing for the first address.

[0086]

As described above , the first feature of the present invention is as follows.
According to the memory access device , the address pipeline
During memory access by
A bus request signal is received when the access response signal is asserted.
In the event of a break, the control
After completing the data input / output processing according to the number,
Interrupt memory access by pipeline control and
The bus right request signal to the
Therefore, the central processing unit keeps outputting the bus request signal.
Without waiting, the address pipeline of the memory access device
Can be forcibly interrupted and proceed to the next process.
As a result, a memory access device capable of improving the performance of the entire system can be provided.

According to the memory access device of the second aspect of the present invention, the bus right response signal from the central processing unit is generated during the memory access by the address pipeline control.
If the bus is negated due to a malfunction of the bus,
Data input / output processing according to the number of address advance
Memory access by the address pipeline after
The bus access.
Bus contention with signals output from other devices on the bus
As a result, it is possible to provide a memory access device capable of improving the reliability of the system without causing any problem .

According to the memory access device of the third aspect of the present invention, when an internal exception signal is received during memory access by the address pipeline control ,
The control means inputs data according to the number of address advance.
After finishing output processing, by address pipeline control
Terminate memory access and bus to central processing unit
An exception occurs because the right request signal is negated
Error recovery by continuing bus access
It is possible to provide a memory access device that does not cause a delay in the read process and that can improve the reliability of the system as a result .

Further, according to the memory access device of the fourth aspect of the present invention, during the memory access by the address pipeline control , the entry request signal to the conversion table is transmitted.
When received, the address is first sent out by the control means.
After completing the data input / output processing according to the number of
Interrupting memory access by pipeline control
Therefore, it is possible to provide a memory access device capable of forcibly interrupting the address pipeline .

According to the memory access device of the fifth aspect of the present invention, the bus error signal from the bus is asserted during the memory access by the address pipeline control.
Is detected when the access response signal is asserted
The address pipeline system immediately by the control means.
Memory access was terminated.
The dress pipeline can be forcibly terminated,
A memory access device capable of improving system reliability can be provided.

[0091]

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a system configuration diagram of a computer system according to the present invention.

FIG. 3 is a configuration diagram of a memory access device according to one embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a bus access request unit of the memory access device of the present invention.

FIG. 5 is a circuit configuration diagram of an internal exception generation unit of the memory access device of the present invention.

FIG. 6 is a circuit configuration diagram of a timing sequencer of the memory access device of the present invention.

FIG. 7 is a circuit configuration diagram of a bus right control unit of the memory access device of the present invention.

FIG. 8 is a circuit configuration diagram of an address control unit of the memory access device of the present invention.

FIG. 9 is a circuit configuration diagram of a data control unit of the memory access device of the present invention.

FIG. 10 is a block diagram of a memory access device according to the present invention;
6 is a timing chart illustrating an operation when U has to use a bus.

FIG. 11 is a timing chart illustrating an operation of the memory access device according to the present invention when an exception occurs inside the memory access device.

FIG. 12 is a timing chart illustrating an operation when a bus exception occurs in the memory access device of the present invention.

FIG. 13 is a configuration diagram of a memory device having four banks.

FIG. 14 is a timing chart of an address pipeline control for preliminarily outputting four addresses.

FIG. 15 is a system configuration diagram of a conventional computer system.

FIG. 16 is a timing chart of memory access by ordinary address pipeline control in a conventional memory access device.

[Explanation of symbols]

1, 101: memory access device 2: central processing unit 3: memory device 5: bus 11: address generation unit 12: address control unit 13: exception detection unit 14: control unit 15: conversion table GRB #, BRL #, BRLX Bus right request signal DC #, DCX ... access response signal HREQ #, HREQX ... bus right request signal HACK #, HACKX ... bus right response signal IERRX ... internal exception signal TLBREQX ... entry request signal BERR #, BERRX ... bus error signal 21 ... Bus access request unit 31 Internal exception generation unit 41 Timing sequencer 51 Bus right control unit 61 Address control unit 71 Data control unit Address (O) Address Data (I / O) Data IBRX Bus access request signal BUSGX: Bus right acquisition signal A UT bus access signal CON1 to CON3 state signal group START start request signal 22 bus access number register 23 decrementer 24 comparator 25, 26, 33, 35, 52 to 57, 59 gate circuits 27, 58 Flip-flops 32-1 to 32-n Arithmetic unit 34 Latch PA1 to PA4, PAD, PD1 to PD4 Bus access state TLBE Entry state of conversion table TLB Ti ... Idle state LTi, LPA1 to LPA4, LPAD, LPD1 ~ L
PD4, LTLBE Latch ti, pa1 to pa4, pd1 to pd4, tlbe State signal CL1 to CL22 Condition determination logic circuit OR1 to OR6 Logical OR circuit 62 Address conversion unit 63 Selector 64 Output unit 81 Logical address Register 82 Offset register 83 Adder 84 Intermediate address register 85 Conversion table 86 Address conversion table 87 Physical address register 88 TLB entry address register 72 Input unit 73 Output unit CLK Clock signal R / W # (O): Read / write signal

Continuation of front page (56) References JP-A-4-343151 (JP, A) JP-A-3-1663638 (JP, A) JP-A-2-110646 (JP, A) JP-A 64-32365 (JP) , A) JP-A-58-75260 (JP, A) JP-A-58-9970 (JP, A) US Patent 5,695,553 (US, A) European Patent Application 550976 (EP, A2) (58) (Int.Cl. ⁷ , DB name) G06F 9/38 G06F 12/00 G06F 12/02 G06F 12/04 G06F 12/06 G06F 13/00 G06F 13/16 G06F 13/28

Claims (5)

(57) [Claims] 1. A central processing unit, a memory device, and a bus.
Bus request signal sent to the central processing unit
Bus right from the central processing unit according to the HREQ #
When the response signal (HACK #) is returned, the address
Memory by address pipeline control
MEMORY ACCESS DEVICE FOR MEMORY ACCESS TO DEVICE
In the address raw to generate an address for memory access
And address control for outputting the generated address to the bus.
And a bus request signal (BR) output from the central processing unit.
L #) and completion of memory access to one address
Access response signal output from the memory device at times
(DC #) and receives the bus right request signal (BRL).
#) And the access response signal (DC #)
Number of address advance when detecting that it is a assert
After completing the data input / output processing according to
Interrupts memory access by CPU control
Negate the bus request signal (HREQ #) to the device
Memory access device having control means
Place. 2. The control means according to claim 1 , wherein
During the memory access by the in-control, the central processing unit
Bus right response signal (HACK #) from the
When the address is negated,
After completing the same data input / output processing, the address pipe
Interrupting the memory access by the control and the central processing unit
To negate the bus right request signal (HREQ #)
2. The memory device according to claim 1, further comprising:
Access device. 3. Detecting an exception inside the memory access device.
Exception detection that issues an internal exception signal (IERRX)
Means, wherein the control means is based on the address pipeline control.
During memory access, the internal exception signal (IERRX)
Received, the data according to the number of address advance
After completing the input / output processing, the address pipeline control
To terminate the memory access by
Control means for negating a bus right request signal (HREQ #)
2. The memory access device according to claim 1, wherein
Equipment. 4. The method according to claim 1, wherein said address generating means is a logical address.
The has a conversion table to convert the physical address, the variable
Address for memory access by the conversion table
Physical to be generated and converted into the conversion table
If there is no address, the entry request signal (TLBRE)
QX), and the control means controls the address pipeline control.
During the memory access, the entry request signal (TLBR)
EQX) according to the number of address advance
After completing the data input / output processing, the address pipeline
The central processing by interrupting memory access by
Negate the bus request signal (HREQ #) to the device
2. The memory access device according to claim 1, wherein: 5. The control means according to claim 1, wherein said control means is adapted for one address.
Output from the memory device when the memory access is completed.
Access response signal (DC #)
Bus error signal (BERR #) output from the bus
Receiving and memory by the address pipeline control
During access, the bus error signal (BERR #) is
The access response signal (DC #)
Address is detected when asserted, the address
Control means for terminating memory access by pipeline control
2. The memory access device according to claim 1, wherein
Equipment.