JP3104050B2 - Raster graphics system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer graphics system for generating an output image by a raster system, and more particularly to a raster graphics system capable of improving the effective processing capability of the computer system. System.

[0002]

2. Description of the Related Art Recently, the field of computer graphics includes a high-performance microprocessor (Micro Processor).
) And the development of inexpensive high-density memory devices have made remarkable progress. In particular, research on animation of three-dimensional objects and real-time simulation has been actively promoted. . A system that supports high-performance 3D graphics is called Transformation.
Work that changes position and size) and cut (Clippi
ng: Geometry engine that supports the process of removing image parts outside the boundaries of the display screen from computer graphics, and Rasterization
It is composed of a raster engine that is in charge of

[0003] The raster engine uses scan conversion.
Many operations and frequent accesses to the frame buffer memory create bottleneck phenomena due to ting and hidden surface removal and shading or rendering. However, with the recent development of high performance engines (or processors), the access time to the frame buffer memory rather than the computing power of the engine is a major cause of the bottleneck phenomenon in the graphics pipeline. Therefore, high-speed rasterization (High spead rasteriza
Research) has been conducted in the direction of processing a large number of pixels in parallel at the same time. Conventional systems employ a pixel cache memory to improve system performance and processing speed.

FIG. 5 shows a conventional raster graphics system.
FIG. 1 shows a system in which a pixel cache memory 20 is added between a scan converter 10 for generating data related to each pixel and the like and a frame buffer memory 30 for storing pixel data. I have. The pixel cache memory 20 has a smaller capacity than the frame buffer memory 30, but the access time is much faster (usually about 5 to 10 times faster).
The interface between the frame buffer memory 30 and the pixel cache memory 20 is transferred in units of many words (or blocks) at a time, so that the interface between the frame buffer memory and the pixel cache memory can be transferred. Not only could the bandwidth of the system be substantially improved, but the locality of reference shortened the system's work time.

FIG. 6 shows a frame buffer memory FB0.
-Normal pixel map between FB3 and screen (Pi
xel map). The pixel cache memory typically forms a tile, such as a square or a plurality of pixels arranged in a straight line. Therefore, the number of pixels updated per cycle (Tile Size) varies depending on the Tile Size. Large tiles guarantee high performance by updating many pixels, etc. per memory cycle of frame buffer memory, but also increase the price of pixel cache memory. The number varies depending on the operation type performed in the tile structure. In vector drawing and wireframe (Wireframe: a computer graphic that shows the shape of an object in a collection of many lines to show the shape of a three-dimensional object to show the shape of a three-dimensional object), A square tile structure (eg 4x4) updates more pixel groups (Ca
che hit) so that it can be filled with polygons (Polygo
n fill) and shading, or horizontal vector drawing, are arranged in a line along the X axis (eg, 16
× 1) can update more pixel groups. In this specification, a pixel cache memory in which 8 × 8 pixel tiles are used will be described as an example for easy understanding.

The operation of the conventional system will be described in more detail with reference to FIGS. 7, 8 and 9. FIG. 7A shows a state where the scan converter 10 stores the pixel data in the pixel cache memory. Pixel cache memory,
If both of the frame memories are in the clear state, the pixel data is temporarily stored in the pixel cache memory and then transferred to a predetermined area of the frame buffer memory as shown in FIG. Stored and this pixel cache memory is cleared.

However, when pixel data is stored in the same block or tile of the frame buffer memory, the pixel data that has already been stored in the frame buffer memory is not stored. In order to prevent damage, as shown in FIG. 8C, the previously stored pixel data is first read out and stored in the pixel cache memory. Subsequently, the scan converter, as shown in FIG.
New pixel data is added to the pixel cache memory and stored. In the case of a cache miss, the pixel data is temporarily stored in the pixel cache memory and then transferred to and stored in the frame buffer memory as shown in FIG.
This pixel cache memory is cleared.

[0008]

However, the above-mentioned raster graphics system has the following problems. Scan converter with polygons (polygo
When shading n) or constructing a wire frame, after reading out pixel data already stored in the frame buffer memory and storing it in the pixel cache memory, new pixel data is stored in the pixel cache memory. Store in memory. The reason is that, for example, the tile of the pixel cache memory storing the pixel data of the new vector is transferred to the area of the frame buffer memory storing the existing pixel data by the vector in the above-described vector drawing. This is to prevent the existing pixel data described above from being cleared. However, in the case of a cache failure, the pixel data is once stored in the pixel cache memory and then transferred to the frame buffer memory and stored therein, as described above.
This pixel cache memory is cleared.

That is, the conventional raster graphics
When new pixel data is provided from the scan converter, the system reads pixel data stored in the frame buffer memory and stores the pixel data in the pixel cache memory every time a pixel cache failure occurs. The new pixel data is added to the pixel data and stored, and then the pixel data is collectively stored in the frame buffer memory. This load of data transfer to the cache memory reduces the effective processing capacity of the system. SUMMARY OF THE INVENTION In view of the above problems, the present invention reduces a data transfer load between a pixel cache memory and a frame buffer memory by a graphics system having a master control logic for efficiently accessing the frame buffer memory. It is another object of the present invention to provide a raster graphics system capable of improving the above-described effective processing capability.

[0010]

In order to solve the above-mentioned problems, the present invention has the following means. (1) A scan converter for generating pixel data, and a pixel converter for temporarily storing the pixel data sequentially provided from the scan converter
In a raster graphics system including a cache memory and a frame buffer memory including a plurality of small areas for transferring the pixel data to a screen, a connection is provided between the pixel cache memory and the frame buffer memory. And the pixel
Data detection means for detecting data in the flash memory;
The pixel key detected by the data detecting means.
If the data in the cache memory is all 0,
Frame / buffer memo of the above small area to be replaced
And mask control logic means for keeping the pixel data stored in the frame buffer memory intact without damaging the pixel data without damaging the pixel data. Even if a cache miss occurs,
A raster graphics system wherein pixel data already stored in the frame buffer memory need not be read out to the pixel cache memory each time. (2) The mask control logic means includes:
A logic gate for negating the pixel data in the pixel cache memory to which no data is added by the scan converter;
The output of each of the NOT logic gates is ANDed with each of the write enable signals enabling the storage in the frame buffer memory, and the result is written to the frame buffer memory as a new write enable signal. It includes a respective aND gate providing said data detection hand
The pixel cache memory detected by the stage
If all the data of the pixel cache memory is 0, the above-mentioned area is masked to mask a new area other than the above-mentioned pixel data to be added to and stored in the frame buffer memory from the entire area of the above-mentioned pixel cache memory. Each AND gate
Rewrite target by controlling each write enable signal
Rewriting the frame buffer memory of the above small area
Raster graphics system as set forth in the preceding paragraph (1) which is example to suppress like the.

[0011]

When the scan converter transfers new pixel data to the frame buffer memory via the pixel cache memory and stores it, the pixel
This new pixel stored in the cache memory
Since the write enable is masked for each pixel of data and stored redundantly in the frame buffer memory, pixel data already stored in the frame buffer memory is not cached. Need not be read and stored in the pixel cache memory each time.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing the system of the present invention, and FIG. 2 is a block diagram specifically showing the mask control logic in FIG. In the present embodiment, a pixel cache memory in which 8 × 8 pixels are converted into one tile as described above will be described as an example. Note that such a configuration is an example of a pixel cache memory, and the size and arrangement are changed in consideration of a cache hit ratio (for example, 4 × 4). , 16 × 16, 16 × 1, 64 × 1,...).

In FIG. 3A, in order to draw an oblique line segment (12 pixels) on the screen, the scan converter 10 first clears the pixel cache memory 20 and then stores it in the pixel cache memory 20.
The pixel data of the vector corresponding to the above-mentioned line segment is sequentially filled and stored one by one. In FIG. 3B, 12 pixels are stored in the pixel cache memory.
When a cache failure occurs after all the data has been filled, the pixel data of this vector, which has already been stored in the pixel cache memory, is stored in the frame cache.
This pixel is transferred and stored in the buffer memory.
The cache memory is cleared.

Subsequently, in FIG.
The converter uses other vector drawing (Vector dra
wing)).
Store in cache memory. Further, in FIG. 4D, if a cache failure occurs in drawing the next figure, the pixel data in the pixel cache memory is transferred to the frame buffer memory and stored therein.
After clearing the pixel cache memory, the above process is repeated to draw the next figure or the like.

Here, suppose that the format of the pixel data transferred to the frame buffer memory is always in the form of a data tile which is data of a size corresponding to the entire area of the pixel cache memory, as in the above-described conventional example. If so, the frame corresponding to this data tile
The entire area of the buffer memory is updated, and the pixel data previously stored in this area is lost. Therefore, in FIG. 1, the mask control logic 40 of the present embodiment is additionally provided, and the previously stored pixel data is duplicated by the above-described data tile stored thereafter. Overlap) so that they are not erased.

FIG. 2 is a block diagram specifically showing the mask control logic. Since the pixel cache memory 20 is cleared in the initial state, the pixel cache memory 20 for transferring to the frame buffer memory 30 is stored.
In the storage area where no data exists, each pixel is all 0
Has been cleared. That is, when data is transferred to the frame buffer memory 30, pixel data for which there is no data to be transferred and stored (for example, pixel data
If the data is 8 bits, it is 0000 0000. ) Is input to each of the NOR gates 41, 42, 43, and 44, the outputs thereof are all set to 1.

The output of each NOR gate all set to 1 permits data to be stored in the frame buffer memory 30 and is independent of the state of the write enable signal (WE #) which is valid at a logical zero. Each output WE # 0 of each OR gate 45, 46, 47, 48 for a logical zero
WE # 1, WE # 2, WE # 3 are all set to 1,
Each frame buffer memory FB0, FB1, FB2,
All FB3s are deactivated. As a result, each frame buffer memory FB0, FB1, FB
2, and the respective pixel data stored in the FB 3 are maintained without being deleted without being overlapped by new pixel data. The present invention is not limited to the above-described embodiment. For example, each of the NOR gates described above may be a NAND gate, and can be realized by other gate means or the like depending on the logical and hardware characteristics of the system. Needless to say, various changes can be made without departing from the gist of the present invention, for example, a mask control logic means or the like suitable for various systems can be configured.

[0018]

As described above, the present invention has the following effects. When the scan converter transfers and stores new pixel data to the frame buffer memory, the data previously stored in the frame buffer memory does not need to be read out to the pixel cache memory each time. Thus, the load required for data transfer between the pixel cache memory and the frame buffer memory is reduced by half, and the processing speed of the effective system can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram for explaining an embodiment of the present invention.

FIG. 2 is a configuration diagram specifically showing a mask control logic in FIG. 1;

FIG. 3 is an explanatory diagram for explaining the operation of the graphics system in FIG. 1;

FIG. 4 is an explanatory diagram for explaining the operation of the graphics system.

FIG. 5 is a schematic configuration diagram of a conventional raster graphics system.

FIG. 6 is an explanatory diagram for explaining a pixel map between a general screen (Screen) and a frame buffer memory.

FIG. 7 is an explanatory diagram for explaining the operation of the graphics system in FIG. 4;

FIG. 8 is an explanatory diagram for explaining the operation of the graphics system.

FIG. 9 is an explanatory diagram for explaining the operation of the graphics system.

[Explanation of symbols]

10 Scan converter 20 Frame buffer memory
memory) 30 pixel cache memory
memory) 40 Mask control logic
ntrol logic) 41, 42, 43, 44 NOR gate 45, 46, 47, 48 OR gate

Claims (2)

(57) [Claims] A scan for generating pixel data.
A pixel cache memory for temporarily storing the pixel data sequentially provided from the scan converter; and a frame buffer memory including a plurality of small areas for transferring the pixel data to a screen. In a raster graphics system, a data connection between the pixel cache memory and the frame buffer memory for detecting data in the pixel cache memory.
Data detection means, and the pixels detected by the data detection means.
If the data in the cache memory is all 0,
The frame buffer memory of the small area to be rewritten
A mask control logic means for keeping the pixel data stored in the frame buffer memory in an unrewritable state so that the pixel data can be maintained without being damaged; A raster graphic system characterized in that pixel data already stored in the frame buffer memory does not need to be read out to the pixel cache memory each time a cache failure occurs. System. 2. The logic circuit according to claim 1, wherein said mask control logic means comprises: a negated logic gate for negating the pixel data in the pixel cache memory to which data is not added by the scan converter; Of each of the above and each of the write enable signals enabling the storage in the frame buffer memory, and providing each of the logical products to be provided to the frame buffer memory as new write enable signals A gate, and the pixel detected by the data detection means.
If the data in the cache memory is all 0,
In order to mask a region other than the new pixel data to be added to and stored in the frame buffer memory from the entire region of the pixel cache memory.
Controls each write enable signal of each AND gate
Frame buffer of the small area to be rewritten
Claim 1 wherein rewriting of the memory is suppressed .
A raster graphics system as described in 1.