JP3108331B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (Thi
n Film Transistor) .

[0002]

2. Description of the Related Art LCDs (Liquid Cr
In recent years, the development of the active matrix system from the simple matrix system has been active. The active matrix system includes a TFT type in which a thin film transistor is provided for each pixel and a diode type in which a non-linear diode is provided. Among them, the TFT type uses the switching characteristics and the pixel capacitance to hold the voltage applied during the selection period until the next scan, and can easily obtain a large capacitance and high contrast and halftone. it can.

However, this TFT type LCD is
There is a problem that a leakage current occurs during the so-called OFF period of the TFT that holds the applied voltage. Therefore, in order to reduce the leakage current, a transistor having an LDD structure is employed. Various methods of manufacturing a transistor having an LDD structure have been proposed. In order to simplify the process, a technique of forming the transistor in a self-aligned manner is disclosed in, for example, JP-A-4-1043.
No. 4 (H01L21 / 336).

This prior art will be described with reference to FIGS. Step A (see FIG. 19): insulating substrate (for example, quartz glass)
A polycrystalline silicon film 52 is formed on 51, and in order to use the polycrystalline silicon film 52 as an active layer of a thin film transistor, the polycrystalline silicon film 52 is processed into a predetermined shape by a photolithography technique and a dry etching technique by an RIE method. I do.

On the polycrystalline silicon film 52, a reduced pressure C
A silicon oxide film as the gate insulating film 53 is deposited by using the VD method. Step B (see FIG. 20): After a polycrystalline silicon film is deposited on the gate insulating film 53 by a low pressure CVD method, an impurity is implanted into the polycrystalline silicon film, and a heat treatment is performed to activate the impurity. .

Next, after a silicon oxide film 54 is deposited on the polycrystalline silicon film by a normal pressure CVD method, the polycrystalline silicon film and the silicon film are formed by a photolithography technique and a dry etching technique by an RIE method. The oxide film 54 is processed into a predetermined shape. The polycrystalline silicon film is used as a gate electrode 55. Next, by using the gate electrode 55 and the silicon oxide film 54 as a mask, low-concentration impurities are implanted into the polycrystalline silicon film 52 by a self-alignment technique to form a low-concentration impurity region 56a.

Step C (see FIG. 21): After a thin silicon oxide film is deposited on the gate insulating film 53 and the silicon oxide film 54 by a low pressure CVD method, the silicon oxide film is anisotropically etched back to form the gate. A side wall 57 is formed on a side wall of the electrode 55. And the sidewall 5
7 is used as a mask, high-concentration impurities are implanted into polycrystalline silicon film 52 to form high-concentration impurity regions 56b.

Thus, LD as source / drain
An impurity region 56 having a D structure is formed in a self-aligned manner.

[0009]

In the conventional example, L
By adopting the DD structure, the leakage current at the time of OFF can be reduced. However, in order to apply the device to an increasingly higher performance device such as an LCD in the future, it is necessary to suppress this leakage current as much as possible. The present invention has been made in view of the above problems, and provides a thin film transistor having a small leakage current when turned off.

[0010]

A thin film transistor according to claim 1 is provided.
The method of manufacturing a star is to form a polycrystalline silicon film on an insulating substrate.
And the gate isolation on this polycrystalline silicon film.
Forming a gate electrode through an edge film;
Forming a first sidewall on at least a side wall of the electrode;
And using the first sidewall as a mask,
Implanting a low concentration of impurities in the polycrystalline silicon film
And resisting the gate electrode and the first sidewall.
Covering with a mask and using the resist as a mask
Implanting a high concentration of impurities into the crystalline silicon film.
It is a thing.

Further , the manufacturing of the thin film transistor according to claim 2
Method for forming an amorphous silicon film on an insulating substrate
And heat-treat this amorphous silicon film to form polycrystalline silicon.
Forming a film, and forming a gate on the polycrystalline silicon film.
Forming a gate electrode through a gate insulating film;
A first sidewall on at least a side wall of the gate electrode;
Forming, and using the first sidewall as a mask
To implant a low concentration impurity into the polycrystalline silicon film.
Forming the gate electrode and the first sidewall.
A step of covering with a resist, using the resist as a mask,
Implanting high-concentration impurities into the polycrystalline silicon film
And

Further, the production of the thin film transistor according to claim 3
The method includes a heat treatment for activating the implanted impurities.
Is what you do.

In other words, in the semiconductor film (polycrystalline silicon film), sidewalls are provided not on both sides of the gate electrode but on the sidewalls of the gate electrode.
By forming the DD structure, leakage current when the transistor is turned off is reduced.

[0013]

1 to 1 show an embodiment of the present invention.
8 will be described. Step 1 (see FIG. 1): An SiO ₂ film 1a having a thickness of 3000 to 5000 ° is formed on a substrate 1 such as quartz glass or non-alkali glass at a formation temperature of 350 ° C. by a normal pressure or reduced pressure CVD method.

The thickness of the SiO ₂ film 1a is such that impurities in the substrate 1 are
_{2 It} is necessary to have a thickness that does not diffuse through the film to the upper layer,
The range of 1000-6000Å is appropriate, and 2000-60
When the angle is set to 00 °, the diffusion preventing effect is good, and among them, the case of 3000 to 5000 ° is most suitable. Further, a SiN film may be used instead of the SiO ₂ film 1a,
In this case, the film thickness is suitably in the range of 1000 to 5000 °, and the diffusion prevention effect is good when the film thickness is 2000 to 5000 °, and among them, the case of 2000 to 3000 ° is most suitable.

Step 2 (see FIG. 2): the insulating thin film 1a
The amorphous silicon film 2a (thickness: 500 °) is formed on the substrate. When the amorphous silicon film 2a is used as an active layer of a TFT, if the active layer is too thick, the off current of the polycrystalline silicon TFT increases, and if it is too thin, the on current decreases. The thickness of the crystalline silicon film 2a is suitably in the range of 400 to 800 °, and is in the range of 500 to 700 °.
The characteristics are good when Å is selected.
The case of 0 ° is most suitable.

The method of forming the amorphous silicon film 2a is as follows. Method using low-pressure CVD: In order to form a silicon film by low-pressure CVD, thermal decomposition of monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. When monosilane is used, it becomes amorphous at a processing temperature of 550 ° C. or lower, and becomes polycrystalline at a processing temperature of 620 ° C. or higher. At 550 to 620 ° C., the amount of amorphous containing microcrystals increases, and the lower the temperature, the closer to amorphous and the number of microcrystals decreases. Therefore, the amount of microcrystals in the amorphous silicon film 2a can be adjusted only by changing the temperature condition.

Method using plasma CVD method: In order to form an amorphous silicon film by plasma CVD method, thermal decomposition of monosilane or disilane in plasma is used.
In an actual process, the above-described method is employed to form an amorphous silicon film containing no microcrystal under the conditions of gas used: monosilane, temperature: 350 ° C. Step 3 (see FIG. 3): The surface of the amorphous silicon film 2a is scanned with a XeCl excimer laser beam having a wavelength of λ = 308 nm to perform an annealing process.
is melt-recrystallized to form a polycrystalline silicon thin film 2.

The laser conditions at this time are as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature: room temperature to 600 ° C.
Irradiation energy density: 100 to 500 mJ / cm ² , scanning speed: 1 to 10 mm / sec (actually, 0.1 to 1
(Scanning is possible at a speed in the range of 00 mm / sec). Step 4 (see FIG. 4): In order to use the polycrystalline silicon film 2 as an active layer of a thin film transistor, the polycrystalline silicon film 2 is processed into a predetermined shape by a photolithography technique and a dry etching technique by an RIE method.

Then, on the polycrystalline silicon film 2,
Using a low pressure CVD method, an LTO film (Low Temperature Oxide: silicon oxide film) 3 (thickness: 1000 °) is formed as a gate insulating film. Step 5 (see FIG. 5): An amorphous silicon film (thickness: 2000 Å) 4 is formed on the gate insulating film 3 by a low pressure CVD method.
a is deposited. The amorphous silicon film 4a is doped with impurities (arsenic or phosphorus for N-type and boron for P-type) at the time of its formation, but may be deposited in a non-doped state and then implanted with impurities.

Next, tungsten silicide (WSi ₂ ) is formed on the amorphous silicon film 4a by sputtering.
A film 4b (thickness 1000 °) is formed. In the sputtering method, a W silicide alloy target is used. Then, after a silicon oxide film 5 is deposited on the W silicide film 4b by a normal pressure CVD method, a photolithography technique and a dry etching technique by an RIE method are used.
The polycrystalline silicon film 4a, the W silicide film 4b and the silicon oxide film 5 are processed into a predetermined shape. The amorphous silicon film 4a is used as the gate electrode 4 having a polycide structure together with the W silicide film 4b.

Incidentally, the gate electrode 4 may be formed of polycrystalline silicon alone. Step 6 (see FIG. 6): A silicon oxide film is deposited on the gate insulating film 3 and the silicon oxide film 5 by a normal pressure CVD method, and this is anisotropically etched back to form the gate electrode 4. Then, a sidewall 7 (thickness 1500 °) is formed on the side of the silicon oxide film 5.

Then, by using the sidewall 7 as a mask, the polycrystalline silicon film 2 is applied to the polycrystalline silicon film 2 by the self-alignment technique under the conditions of an acceleration voltage of 80 KeV and a dose of 3 × 10 ¹³ cm ⁻² .
Phosphorus (P) ions are implanted as impurities to form low-concentration impurity regions 6a. Step 7 (see FIG. 7): The side walls 7 and the silicon oxide film 5 are covered with a resist 8, and the polycrystalline silicon film 2 is again formed by a self-alignment technique using the resist 8 as a mask.
Under the conditions of an acceleration voltage of 80 KeV and a dose of 3 × 10 ¹⁵ cm ⁻² , phosphorus (P) ions are implanted as impurities to form a high-concentration impurity region 6 b, thereby forming an LDD (Light).
A source / drain region 6 having a ly-doped drain structure is formed.

Step 8 (see FIG. 8): In this state, RTA
(Rapid Thermal Annealing) method. At this time, the RTA conditions are as follows: heat source: xenon arc lamp, temperature: 800 to 900 ° C. (pyrometer), atmosphere: N ₂ , time: 1 to 2 seconds. Heating by the RTA method uses a high temperature, but can be completed in a very short time, so that there is no fear that the substrate 1 is deformed. In particular, such lamp annealing is suitable for activating impurities since the temperature of the amorphous portion is further increased.

At this time, in order to easily absorb the heat of the RTA, a thin amorphous silicon film may be formed on the device surface before the RTA. By this rapid heating, the impurities in the source / drain regions 7 are activated and the amorphous silicon film 4a is polycrystallized. Further, the polycrystalline silicon film 4a and the W silicide film 4b
As a result, the sheet resistance of the gate electrode 4 having the polycide structure is reduced to about 22 Ω / □.

Also, the sheet resistance of the activated source / drain regions 6 is 1.5 kΩ / □ for N-type and 1.2 kΩ / □ for P-type, and is a high-temperature heat treatment using a diffusion furnace used in a high-temperature process. Is equivalent to Incidentally, the impurity is diffused by this activation, and the source / drain region 6 is diffused.
May also spread slightly below the sidewalls 7. Therefore, the term “both sides of the sidewall” in the present invention also includes a state in which impurities are diffused and spread below the sidewall.

Through the above steps, the thin film transistor (T
FT: Thin Film Transistor (A) is formed. In the present embodiment, as described above, a unique L
Since a thin film transistor having a DD structure is formed, the thin film transistor has an OFF-state compared to a thin film transistor having a conventional LDD structure.
The leakage current at the time can be greatly reduced.

According to the experiment conducted by the present inventors, the gate width W / gate length L = 400/3.
5, drain voltage VD = -12V, gate voltage VG = -1
When set to 6 V, the leakage current I _OFF of the conventional thin film transistor was 100 pA, but the leakage current I _OFF of the thin film transistor of the present invention was 10 pA,
It has decreased to 1/10.

Step 9 (see FIG. 9): After removing the resist 8,
Plasma oxide film (2000mm thick) on the entire surface of the device
Silicon oxide film (film thickness 2000)
Å) to form an interlayer insulating film 9 having a laminated structure. Subsequently, in an electric furnace, in a hydrogen (H ₂ ) atmosphere, at a temperature of 45 ° C.
Heat at 0 ° C. for 12 hours, and further perform a hydrogen plasma treatment. By performing such a hydrogenation treatment, hydrogen atoms are bonded to crystal defect portions of the polycrystalline silicon film, the crystal structure is stabilized, and the field effect mobility is increased.

After that, photolithography technology, RIE
A contact hole 10 for contacting the source / drain region 6 is formed in the interlayer insulating film 9 by using a dry etching technique by a method. Step 10 (see FIG. 10): A wiring layer having a laminated structure of Ti / Al—Si alloy / Ti is deposited by magnetron sputtering, and the source / drain electrodes are formed by photolithography and dry etching by RIE. Process as 11.

Step 11 (see FIG. 11): A silicon oxide film 1 as a protective film is formed on the entire surface of the device by CVD.
2 (which may be a silicon nitride film) is deposited thinly. Step 12 (see FIG. 12): SOG (Sp
(In-On-Glass) film 13 is applied three times to flatten the unevenness on the device surface. Step 13 (see FIG. 13): Since the SOG film 13 has poor resist strippability and easily absorbs moisture, a silicon oxide film 14 (silicon) is further formed on the SOG film 13 by a CVD method as a protective film. (It may be a nitride film).

Step 14 (see FIG. 14): A contact leading to the source / drain electrode 11 is made to the silicon oxide film 12 / SOG film 13 / silicon oxide film 14 using a photolithography technique and a dry etching technique by RIE. A hole 15 is formed, and an ITO film 16 as a pixel electrode is sputter-deposited on the entire surface of the device. Step 15 (see FIG. 15): Finally, in order to process the ITO film 16 into an electrode shape, after forming a resist pattern on the ITO film 16, first, by an RIE method using hydrogen bromide gas (HBr). When the ITO film 16 is etched and the silicon oxide film 14 starts to be exposed, the gas is switched to chlorine gas (Cl ₂ ) and the etching is continued as it is.

Step 16 (see FIG. 16):
After forming the TFT substrate on one side of D, the common electrode 1
The pixel portion of the LCD is completed by making the transparent insulating substrates 18 on which the layers 7 are formed face each other and sealing liquid crystal between the substrates 1 and 18 to form a liquid crystal layer 19. FIG. 17 is a block diagram of an active matrix type LCD according to this embodiment.

In the pixel section 20, each scanning line (gate wiring) G1
... Gn, Gn + 1 ... Gm and each data line (drain wiring) D1
Dn, Dn + 1 ... Dm are arranged. Each gate line and each drain line are orthogonal to each other, and a pixel 21 is provided at the orthogonal portion. Each gate wiring is connected to a gate driver 22 so that a gate signal (scanning signal) is applied. Further, each drain wiring is connected to a drain driver (data driver) 23 so that a data signal (video signal) is applied. A peripheral drive circuit 24 is configured by these drivers 22 and 23.

An LCD in which at least one of the drivers 22 and 23 is formed on the same substrate as the pixel section 20 is generally a driver integrated type (driver built-in type).
It is called LCD. Note that the gate driver 22 may be provided at both ends of the pixel unit 20 in some cases. Further, the drain driver 23 may be provided on both sides of the pixel unit 20 in some cases.

FIG. 18 shows a gate wiring Gn and a drain wiring Dn.
4 shows an equivalent circuit of a pixel 21 provided in a portion orthogonal to FIG. The pixel 21 includes a TFT (same as the thin film transistor A) as a pixel driving element, a liquid crystal cell LC, and a supplementary guide C.
Consists of S. The gate of the TFT is connected to the gate wiring Gn, and the drain of the TFT is connected to the drain wiring Dn. A display electrode (pixel electrode) of the liquid crystal cell LC and an auxiliary capacitance (storage capacitance or additional capacitance) CS are connected to the source of the TFT.

The liquid crystal cell LC and the auxiliary capacitance CS constitute a signal storage element. The voltage Vcom is applied to the common electrode (the electrode on the opposite side of the display electrode) of the liquid crystal cell LC. On the other hand, in the auxiliary capacitance CS, a constant voltage VR is applied to the electrode on the side opposite to the side connected to the source of the TFT. The common electrode of the liquid crystal cell LC is an electrode which is literally common to all the pixels 21. Further, a capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. Incidentally, in the auxiliary capacitance CS,
The electrode on the side opposite to the side connected to the source of the TFT may be connected to the adjacent gate line Gn + 1 in some cases.

In the pixel 21 configured as described above,
When a positive voltage is applied to the gate of the TFT by setting the gate line Gn to a positive voltage, the TFT turns on. Then, the capacitance of the liquid crystal cell LC and the auxiliary capacitance CS are charged by the data signal applied to the drain wiring Dn. Conversely, when the gate line Gn is set to a negative voltage and a negative voltage is applied to the gate of the TFT, the TFT is turned off, and the voltage applied to the drain line Dn at that time changes the capacitance and the auxiliary capacitance of the liquid crystal cell LC. And CS. As described above, by supplying a data signal to be written to the pixel 21 to the drain wiring and controlling the voltage of the gate wiring, the pixel 21 can hold an arbitrary data signal. The liquid crystal cell L according to the data signal held by the pixel 21
The transmittance of C changes, and an image is displayed.

Here, important characteristics of the pixel 21 include a writing characteristic and a holding characteristic. What is required for the writing characteristics is that a desired video signal voltage is sufficiently written to the signal storage elements (the liquid crystal cell LC and the auxiliary capacitance CS) within a unit time determined from the specifications of the pixel unit 20. Is that it can be done. What is required for the holding characteristic is whether or not the video signal voltage once written in the signal storage element can be held for a required time.

The reason why the auxiliary capacitance CS is provided is to increase the electrostatic capacity of the signal storage element to improve the writing characteristics and the holding characteristics. That is, the liquid crystal cell LC
However, due to its structure, there is a limit to the increase in capacitance. Therefore, the shortage of the capacitance of the liquid crystal cell LC is compensated for by the auxiliary capacitance CS. The above embodiment may be modified as follows, and the same operation and effect can be obtained in such a case.

1) In step 2, an amorphous silicon film is formed by a low pressure CVD method using, for example, a monosilane gas.
Deposit at a temperature of 580 ° C. Thereby, the amorphous silicon film 2a becomes a film containing microcrystals. By polycrystallizing an amorphous silicon film containing microcrystals by a solid-phase growth method, the crystal grain size is reduced, but the mobility is slightly reduced, but the crystal growth can be completed in a short time.

2) In the step 2, the amorphous silicon film 2
a is normal pressure C regardless of the reduced pressure CVD method or the plasma CVD method.
VD method, photo-excited CVD method, vapor deposition method, EB (Electron Bea
m) It is formed by any one of a group consisting of a vapor deposition method, an MBE (Molecular Beam Epitaxy) method, and a sputtering method. 3) A portion corresponding to the channel region of the polycrystalline silicon film 2 is doped with an impurity to control the threshold voltage (Vth) of the polycrystalline silicon TFT. In a polycrystalline silicon TFT formed by the solid-phase growth method, the threshold voltage of an N-channel transistor tends to shift in the depletion direction, and the threshold voltage of a P-channel transistor tends to shift in the enhancement direction. Further, when the hydrogenation treatment is performed, the tendency becomes more remarkable. In order to suppress the shift of the threshold voltage, the channel region may be doped with an impurity.

4) The following steps are performed in place of the step 3. Step 3a: By performing heat treatment in a nitrogen (N ₂ ) atmosphere at a temperature of about 600 ° C. for about 20 hours using an electric furnace,
The polycrystalline silicon film 2 is formed by solid-phase growth of the amorphous silicon film 2a. 5) In the polycrystalline silicon film 2 formed in the step 3a, there are many defects such as dislocations in the crystal constituting the film, and there is a possibility that an amorphous portion may remain between the crystals. There is much fear.

Therefore, after the step 3a, the substrate 1 is rapidly heated by the RTA method or the laser annealing method to improve the film quality of the polycrystalline silicon film 2. In the embodiments 4) and 5), when the laser beam is not used, the S
The iO ₂ film 1a is not particularly required. 6) The electric furnace takes a longer time than the laser irradiation, but can process a large amount of substrates at a time, so that the steps 4) and 5) have substantially higher throughput. Therefore, a subsequent heat treatment for, for example, activating the impurity region
A laser beam annealing method may be used instead of the RTA method. The RTA method has an advantage that the process can be completed in a short time, and the laser annealing method has an advantage that the sheet resistance can be reduced because the temperature of the impurity region can be increased.

7) In step 5, P other than the sputtering method
The W silicide film 4b is formed by using a VD method (a vacuum deposition method, an ion plating method, an ion beam deposition method, a cluster ion beam method, or the like). 8) As an alternative to W silicide, MoSi ₂ , T
iSi _2, TaSi _2, refractory metal silicide such as CoSi _2, other, W, Mo, Co, Cr , Ti, may be used a high-melting metal such as Ta.

9) The present invention is applicable not only to a planar type but also to a polycrystalline silicon TFT having any structure such as an inverted planar type, a staggered type and an inverted staggered type. 10) The invention is applied not only to polycrystalline silicon TFTs but also to insulated gate semiconductor devices in general. In addition, photoelectric conversion elements such as solar cells and optical sensors, bipolar transistors, and static induction transistors (SITs)
or) for any semiconductor device using a polycrystalline silicon film.

11) Instead of the resist 8, a sidewall made of an insulator such as a silicon oxide film or a silicon nitride film is used. The formation method is the same as that of the side wall 7.

[0047]

According to the present invention, it is possible to provide a high-performance thin film transistor having a small leakage current at the time of OFF.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 8 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 10 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 11 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 12 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 13 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 14 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 15 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 16 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 17 is a block diagram of an active matrix type LCD.

FIG. 18 is an equivalent circuit diagram of a pixel.

FIG. 19 is a cross-sectional view for explaining a manufacturing process of a conventional example.

FIG. 20 is a cross-sectional view for explaining a manufacturing process of a conventional example.

FIG. 21 is a cross-sectional view for explaining a manufacturing process of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 insulating substrate 2a amorphous silicon film 2 polycrystalline silicon film 3 gate insulating film 4 gate electrode 6a low concentration impurity region 6b high concentration impurity region 6 source / drain region 7 sidewall (first sidewall) 8 resist

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-7-140485 (JP, A) JP-A-6-84944 (JP, A) JP-A-5-258991 (JP, A) JP-A-5-25991 241201 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (3)

(57) [Claims] A polycrystalline silicon film is formed on an insulating substrate.
And a gate insulating film on the polycrystalline silicon film through a gate insulating film.
Forming a first electrode on at least a side wall of the gate electrode.
Forming the polycrystalline silicon layer using the first sidewall as a mask.
Implanting a low-concentration impurity into the silicon film; and forming the gate electrode and the first sidewall with a resist.
Covering the polycrystalline silicon film using the resist as a mask.
And a step of implanting high-concentration impurities . 2. An amorphous silicon film is formed on an insulating substrate.
And heat treating the amorphous silicon film to form a polycrystalline silicon film.
Forming step and forming a gate on the polycrystalline silicon film via a gate insulating film.
Forming a first electrode on at least a side wall of the gate electrode.
Forming the polycrystalline silicon layer using the first sidewall as a mask.
Implanting a low-concentration impurity into the silicon film; and forming the gate electrode and the first sidewall with a resist.
Covering the polycrystalline silicon film using the resist as a mask.
Implanting high-concentration impurities.
Of manufacturing a thin film transistor. 3. A method for activating said implanted impurities.
The heat treatment according to claim 1 or 2, wherein the heat treatment is performed.
A method for manufacturing a thin film transistor.