JP3110100B2 - Single-chip microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-chip microcomputer.

[0002]

2. Description of the Related Art FIG. 6 shows a basic configuration of a watchdog timer of a runaway detection circuit built in a conventional single-chip microcomputer. Software runaway detection by a watchdog timer is generally performed as follows.

First, the contents to be processed by the software are divided so as to end within a predetermined time, and the watchdog timer 4 is always cleared by a clear signal S6 at the end of the processing. After setting as described above, the watchdog timer 4 is set and operated so as to output the overflow signal S4 at a time interval equal to a predetermined time of the process determined above.

In a normal software operation, the watchdog timer 4 is cleared at the end of processing, so that the overflow signal S4 from the timer 4 is not output. However, if the processing time exceeds this fixed time due to runaway of software, the watchdog timer 4 outputs an overflow signal S4. That is, the overflow signal S of the watchdog timer 4
Runaway of the software can be detected by the presence or absence of 4.

As shown in FIG. 6, a watchdog timer 4 of a conventional single-chip microcomputer divides a basic clock generated by an oscillation circuit 1 by a frequency divider 2 and counts an output signal thereof by a count clock. The watchdog timer 4 counts as S2. At this time, the overflow time of the watchdog timer 4 is determined by the division ratio of the frequency divider 2 or the count of the watchdog timer 4.
It can be changed by making the number of bits programmable.

[0006]

In the conventional single-chip microcomputer, the count clock of the watchdog timer of the built-in runaway detection circuit is constantly input, which is the basis of the runaway detection operation of software. Condition.

However, in an actual runaway of software, there is a possibility that the operation of the oscillation circuit is stopped and the count clock cannot be input to the watchdog timer for some reason. In particular, in a microcomputer having a standby function, the operation of the oscillation circuit can be stopped by software, and such a situation may occur.

[0008] When a software runaway occurs as described above, the count clock to the watchdog timer is also stopped, and this timer does not overflow, resulting in a fatal runaway detection. The problem was inherent.

[0009]

Means for Solving the Problems] single-chip microcomputer of the present invention, single-chip, which enter the count clock and clear signals have a runaway detection circuit of software having a watchdog timer to output a overflow signal in the microcomputer, the runaway detection circuit is provided for the count clock
Detects the presence or absence in response to the sheet count clock stop detection circuit for output the detection signal corresponding to the stopped state
Starting in response to the supply of the detection signal and counting
・ Replace when clock stops
Oscillator that outputs the pulse and the count clock
Supply the replacement pulse when the clock is stopped by turning on the lock
In response to this, the clock replacement pulse is conducted.
To switch the watch dog timer
And a clock selector .

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. Figure 1 is a block diagram of a reference example for explaining the actual施例of the present invention. In the single-chip microcomputer, runaway detection circuit 6 of the prior art runsaway detection circuit 6 shown in FIG.
b, a count clock stop detection circuit 3 for inputting a count clock S2 and outputting an oscillation stop detection signal S3 when oscillation stops, and a runaway detection signal S5 of a logical sum of an overflow signal S4 and an oscillation stop detection signal S3 OR
A gate 5 is additionally provided.

Next, the operation of the block will be described. The clock generated by the oscillation circuit 1 is frequency-divided through the frequency divider 2,
The count clock S2 enters the runaway detection circuit 6. The oscillation circuit 1 receives an oscillation stop signal S1 controlled by software and stops oscillation.

The watchdog timer 4 counts
It operates by counting the clock S2. If the clear signal S6 is not controlled by software, it overflows and outputs an overflow signal S4. count·
The clock S2 is also input to the runaway detection circuit 6 and the count / clock stop detection circuit 3 at the same time. When the count clock S2 stops, the circuit 3 detects the stop and supplies the oscillation stop detection signal S3 to the other input terminal of the OR gate 5 for inputting the one-terminal overflow signal S4.

Therefore, the runaway detection circuit 6 uses the overflow signal 7 of the watchdog timer 4 to detect the runaway of the software in the oscillation state, and the count / clock stop detection circuit 3 detects the oscillation stop state due to the software runaway. The oscillation stop detection signal S3 is detected, and both the OR gate 5 outputs the runaway detection signal S5.

[0014] Figure 2 is a block diagram of a real施例of the present invention. The oscillation circuit 1, frequency divider 2, count clock 3, and watchdog timer 4 are the same as the blocks of the above-described reference example.

In the block of this embodiment, when the oscillation circuit 1 stops due to runaway of software, the stop of the count clock S2 is detected by the count clock stop detection circuit 3, and the microcomputer detects the stop of the count clock S2 by the oscillation stop detection signal S3. , And the count clock selector 8 of the watchdog timer 4 switches from the count clock 2 to the oscillation stop clock S7 output from the CR oscillator 7.

Thereby, the watchdog timer 4
Can continue the count operation, and as a result, even if the oscillation circuit 1 is stopped due to the software runaway, the runaway can be detected.

[0017] FIG. 3 is a block diagram showing an example of a count clock stop detection circuit 3 in the above reference example Oyo BiMinoru施例. In FIG. 3, a count / clock stop detecting circuit 3 includes an integrating circuit 31 based on a so-called CR time constant including a resistor and a capacitor, and an intermediate level for detecting an intermediate level which is an output level of the output of the integrating circuit 31 during a normal operation. The detection circuit 32 is included. The intermediate level detection circuit 32 further has a high level detection circuit 321 and a low level detection circuit 322.

Next, the count clock stop detection circuit 3
Will be described.

FIGS. 4A and 4B are diagrams showing the input / output characteristics of the high level detection circuit 321 and the low level detection circuit 322 constituting the intermediate level detection circuit 32, respectively. As shown in FIG. 4, these high-level and low-level detection circuits do not set their respective thresholds to an intermediate value of an input standard value, which is generally an amplitude value of a count clock substantially equal to the power supply voltage, but to a consciousness. The high level detection circuit 321 is set to a higher side, and the low level detection circuit 322 is set to a lower side. By configuring the intermediate level detection circuit 32 as described above, it is possible to set a dead zone at a wide intermediate level.

FIGS. 5A, 5B and 5C show the case where the count clock S2 input to this circuit is normal, the case where the count clock S2 is stopped at a low level, and the case where it is stopped at a high level, respectively. FIG.

In FIG. 5A, the output b of the integrating circuit 31 is in the range of the intermediate level. Therefore, since both the high level detecting circuit 321 and the low level detecting circuit 322 are below the threshold value, the detection output is at the low level. Yes,
As a result, the output S3 of the intermediate level detection circuit 32 goes low.

In FIG. 5B, the output b of the integrating circuit 31 is fixed at a low level from the stop of the count clock S2. Therefore, the low level detecting circuit 322 outputs a high level detection output, and as a result, the intermediate level The output S3 of the detection circuit 32 goes high.

Similarly, in FIG. 5C, the output b of the integration circuit 31 is fixed at a high level from the stop of the count clock S2.
Outputs a high level detection output, and as a result, the output S3 of the intermediate level detection circuit 32 becomes high level.

As described above, the output of the integration circuit 31 cannot maintain the output level in the set intermediate level even if the count clock S2 is stopped at either the high level or the low level. Can be detected by the intermediate level detection circuit 32.

[0025]

As described above, according to the present invention, the count value input by the watchdog timer to the runaway detection circuit is provided.
Since the clock stop detection circuit is built in, it is possible to detect a state in which the oscillator is stopped due to runaway of software, which cannot be detected by the watchdog timer built in the conventional microcomputer.

Therefore, the restriction on the runaway detection function of software, which is required for the original watchdog timer, can be removed, and the reliability of the function can be dramatically improved.

[Brief description of the drawings]

1 is a block diagram of a reference example for explaining the actual施例of the present invention.

2 is a block diagram of a real施例of the present invention.

3 is a block diagram showing an example of a count clock stop detection circuit in reference diagram Oyo BiMinoru施例.

FIG. 4 is a characteristic diagram showing input / output characteristics of a high-level detection circuit and a low-level detection circuit shown in FIG. 3;

FIG. 5 is a time chart for explaining an operation of the count / clock stop detection circuit shown in FIG. 3;

FIG. 6 is a block diagram of an example of a conventional single-chip microcomputer.

[Explanation of symbols]

 1 Oscillator 2 Divider 3 Count clock stop detection circuit 4 Watchdog timer S1 Oscillation stop signal S2, S7 Count clock S3 Oscillation stop detection signal S4 Overflow signal S5 Runaway detection signal S6 Clear signal S7 Oscillation stop clock 5 OR gate 6, 6a Runaway detection circuit 7 CR oscillation circuit 8 Clock selector 31 Integrator circuit 32 Intermediate level detection circuit 321 High level detection circuit 322 Low level detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/00 G06F 15/78

Claims (2)

(57) [Claims] 1. A single-chip microcomputer to input count clock and clear signals have a runaway detection circuit of software having a watchdog timer to output a overflow signal, said runaway detection circuit, the count For clock supply
And count clock stop detection circuit for output the detection signals to detect the presence corresponding to the stopped state in response, the count clock is activated in response to the supply of the detection signal
Clock stop replacement pulse to be replaced when lock stops
And an oscillator for outputting the count clock during normal times.
This clock stops in response to the supply of the replacement pulse when the clock stops.
The watch pulse is switched by switching the
And a count clock selector for supplying a clock timer to the single-chip microcomputer. 2. The count clock stop detection circuit
An integration circuit configured by a resistor and a capacitor to output an average DC voltage of the count clock; and a high-level detection circuit that detects that the average DC voltage has exceeded a preset high-level threshold voltage. 2. The single chip chip according to claim 1, further comprising: an intermediate level detection circuit including a low level detection circuit for detecting that the average DC voltage has become equal to or lower than a predetermined low level threshold voltage. Microcomputer.