JP3112366B2 - Chattering elimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
The present invention relates to a chattering elimination circuit that eliminates chattering that occurs when an electrical signal is turned on and off by a mechanical contact.

[0002]

2. Description of the Related Art Heretofore, when this type of chattering elimination circuit is to be constructed, a clock signal having a constant cycle is used as a sampling signal for determining whether or not chattering has occurred in an input signal.

[0003]

However, in the prior art, since it is necessary to perform sampling until the input signal shows a certain value, a signal indicating that the input signal has actually been input into the system from the key input. It took a long time to occur. If the input signal is not stable, key input must be performed again.However, the number of samplings depends on the sampling signal cycle. If the cycle is long, a data confirmation signal is generated from key input. However, there is a problem that the time required for the chattering detection becomes longer, and the chattering detection accuracy becomes coarser.

Further, if the period is long, the accuracy of chattering detection is improved, but the number of times of sampling is increased, so that the configuration of the discriminating circuit becomes complicated. The present invention has been made in view of the above points, and has as its object to provide a chattering elimination circuit for the purpose of accurately detecting and determining chattering and simplifying a determination circuit configuration.

[0005]

According to the present invention, there is provided a chattering elimination circuit for eliminating chattering generated when an electric signal is turned on and off at a mechanical contact point. The pulse width is adjusted according to the input signal
The control means is provided so as to be variable so as to be gradually reduced as time elapses from the time and to shorten the response time.

According to a second aspect of the present invention, there is provided a first counter circuit for counting the sampling signal by a clock signal having a constant period, and a PWM circuit for inputting data of the first counter circuit and outputting a frequency modulation signal. And the above PW
It comprises a second counter circuit for counting the number of output pulses of the M circuit, and a comparator circuit for comparing the potential of the output signal of the PWM circuit with the input signal input from the mechanical contact.

Further, in claim 3, the input data of the PWM circuit is programmed using a microprocessor, and a pulse width modulation signal is output.

[0008]

According to the present invention, when a sampling signal is input, a sampling signal having a wide pulse width is output, and when the sampling signal is output several times, a sampling signal having a small pulse width is output. As a result, the time (response time) for generating a signal indicating that an input signal is present in the system after the generation of the input signal is shortened.

According to another aspect of the present invention, a first counter circuit for counting the sampling signal with a clock signal having a constant period, and a PWM circuit for inputting data of the first counter circuit and outputting a frequency modulation signal. And the above PW
Since it is composed of a second counter circuit for counting the number of output pulses of the M circuit and a comparator circuit for comparing the potential of the output signal of the PWM circuit with the input signal input from the mechanical contact, the key circuit When an input signal is generated by an input or the like, the first counter circuit operates and transfers data to the PWM circuit. The PWM circuit outputs a pulse waveform sequentially frequency-modulated by data from the first counter circuit. The input signal and the pulse waveform are sampled by a comparator circuit, and the second counter circuit outputs an output if the data is constant for a certain number of times or more.

Further, according to the present invention, the input data of the PWM circuit is programmed by using a microprocessor to output a pulse width modulation signal. , And the result of comparison between the output signal of the PWM circuit and an input signal such as a key input is fed back to the microprocessor, thereby outputting a signal from which chattering has been removed.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 show an embodiment corresponding to claim 1,
FIG. 2 shows a block diagram, which comprises an operation control resolution 1 and a sampling circuit 2. In FIG. 1, first, when a key input signal is received (see FIG. 1A), the sampling circuit 2 outputs a sampling signal having a slow cycle as shown in FIG. 1B.

When the sampling signal is output several times, a sampling signal with a fast cycle is output. The embodiment shows an operation of outputting a signal when three pulses are sampled and the values are the same (see FIG. 1C). In the conventional example shown in FIGS. 1D and 1E, it takes time to perform the same three-pulse sampling, and the time is delayed as shown in FIG.

FIG. 3 shows an example in which a hazard (see FIG. 3A) occurs during sampling. In the conventional examples shown in FIGS. 3D and 3E, even when a hazard occurs, the input signal is output even though the input signal does not maintain a stable constant value because the sampling interval is long (FIG. 3). (E)). However, in this embodiment, since the hazard is detected by sampling the third pulse (see FIGS. 3A and 3B), no output is made as shown in FIG. 3C.

(Embodiment 2) Embodiment 2 is shown in FIGS. In the present embodiment, as shown in FIG.
1, the addition counter 12, the PWM circuit 13, the flip-flop 14, the comparator circuit 15 and the like constitute a chattering elimination circuit. FIG. 5 is a timing chart in the embodiment shown in FIG.

In FIG. 4, when a key input signal is received (see FIG. 5A), the subtraction counter 11 operates and passes data to the PWM circuit 13. The PWM circuit 13 generates a D / A converted output signal according to the input data (see FIG. 5B). In the flip-flop 14 using this signal as a clock signal, a signal is output from the comparator circuit 15 by comparing the output signal when the key input is data and the H / L determination signal.

If the signal is at L level, the PWM circuit 1
3. The addition counter 12 and the subtraction counter 11 are cleared and return to the initial state. If the output signal from the comparator circuit 15 is at the H level, the subtraction counter 11 decrements the data and passes the data to the PWM circuit 13 (see FIGS. 5B and 5C). This time, the PWM circuit 13 generates an output signal having a small pulse width according to the input data (see FIG. 5B).

As described above, in the flip-flop 14 using this signal as a clock signal, a signal is output from the comparator circuit 15 by comparing the output signal when the key input is data with the H / L discrimination signal. By repeating this operation, if the signal of the comparator circuit 15 is at the H level, the PWM circuit 13 sequentially generates an output signal having a small pulse width (see FIG. 5B). At the same time, the count value of the addition counter 12 increases (see FIG. 5D), and when the count value exceeds a preset value, an output signal is generated.

In the case of the present embodiment shown in FIG. 5, a timing chart in which the set value is set to 5 is shown. (Embodiment 3) Embodiment 3 is shown in FIGS. In the present embodiment, as shown in FIG.
A chattering elimination circuit is constituted by the M circuit 22, the comparator 23, and the like. The input data of the PWM circuit 22 is programmed by using the microprocessor 21, and a pulse width modulation signal is output.

In the flowchart shown in FIG. 7, timers 1 and 2 are timer circuits inside the multiplexer 21. Timer 1 is used as a subtraction counter, and timer 2 is used as an addition counter. By operating a program according to the flowchart shown in FIG. 7, the circuit configuration can be simplified. As shown in FIG. 7, the operation of this embodiment first resets the timers 1 and 2, sends a reset signal to the PWM circuit 22, and waits for a key input signal. When a key input is made, data is set in the timers 1 and 2 and the data is transferred to the PWM circuit 22.

Then, a signal is output from the PWM circuit 22 to determine whether the H level is the L level. If the timer 2 is at the H level and the timer 2 is at full count, a signal is output. If the count is not a full count, the data of the timers 1 and 2 are updated, and the data is transferred to the PWM circuit 22.
Repeat this.

[0021]

According to the present invention, in a chattering elimination circuit for eliminating chattering generated when an electric signal is turned on and off at a mechanical contact, a pulse width of a sampling signal for determining whether or not chattering has occurred is provided. From when the input signal is input by the mechanical contact
Since the control means is provided so as to be variable so as to gradually decrease as time elapses and to shorten the response time, when a sampling signal is input, a sampling signal having a wide pulse width is output, and the sampling signal is output. When the signal is output several times, a sampling signal with a small pulse width is output, thereby shortening the time (response time) in which a signal indicating that the input signal has occurred to the system after the input signal is generated (response time). ing. As described above, it is possible to shorten the input signal determination time until chattering is removed.
This is because chattering often occurs at the moment of key input, and utilizes the fact that chattering gradually disappears with time. Conventionally, a clock signal having a constant period is used as a sampling signal for chattering elimination. Therefore, a time up to a preset number of times of sampling has not been confirmed as an input signal even if a key input signal does not cause chattering. By using this sampling signal as a frequency modulation signal, the sampling time can be reduced even with the same number of samplings, and the input signal determination time can be shortened. In addition, since the sampling interval is gradually reduced with the lapse of time, it is possible to detect a hazard or the like before the input data is determined, so that more accurate sampling can be performed.

According to a second aspect of the present invention, a first counter circuit for counting the sampling signal with a clock signal having a constant period, and a PWM circuit for inputting data of the first counter circuit and outputting a frequency modulation signal And the above PW
Since it is composed of a second counter circuit for counting the number of output pulses of the M circuit and a comparator circuit for comparing the potential of the output signal of the PWM circuit with the input signal input from the mechanical contact, the key circuit When an input signal is generated by an input or the like, the first counter circuit operates and transfers data to the PWM circuit. The PWM circuit outputs a pulse waveform sequentially frequency-modulated by data from the first counter circuit. The input signal and the pulse waveform are sampled by a comparator circuit, and the second counter circuit outputs an output if the data is constant for a certain number of times or more. Therefore, it is possible to shorten the input signal determination time until chattering is removed.

Further, according to the third aspect, the input data of the PWM circuit is programmed by using a microprocessor to output a pulse width modulation signal. , And the result of comparison between the output signal of the PWM circuit and an input signal such as a key input is fed back to the microprocessor, thereby outputting a signal from which chattering has been removed. Therefore, the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a timing chart of an embodiment of the present invention.

FIG. 2 is a block diagram of the chattering elimination circuit according to the first embodiment;

FIG. 3 is a diagram showing a timing chart when a hazard is detected in the embodiment.

FIG. 4 is a block diagram of the embodiment.

FIG. 5 is a diagram showing a timing chart of the above.

FIG. 6 is a block diagram of a third embodiment of the present invention.

FIG. 7 is a diagram showing a flowchart of the above.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Operation control part 2 Sampling circuit 11 Subtraction counter 12 Addition counter 13 PWM circuit 14 Flip-flop 15 Comparator circuit 21 Microprocessor 22 PWM circuit 23 Comparator

Continuation of the front page (56) References JP-A-55-110327 (JP, A) JP-A-5-48408 (JP, A) JP-A-4-132414 (JP, A) JP-A-63-303512 (JP) JP-A-2-170717 (JP, A) JP-A-6-224714 (JP, A) JP-A-63-127317 (JP, A) JP-A-4-86339 (JP, U) JP-A 61-133831 (JP, U) JP 4-70661 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17/70 G06F 3/02-3 / 027 H03K 5/00-5/01

Claims (3)

(57) [Claims] In a chattering elimination circuit for eliminating chattering generated when an electric signal is turned on and off at a mechanical contact, a pulse width of a sampling signal for determining whether or not chattering has occurred is determined by setting the pulse width of the sampling signal to the mechanical contact.
Gradually increases with the lapse of time since the input signal was input.
A chattering elimination circuit provided with a control means for changing the size of the chattering so as to make the response time shorter. 2. A first counter circuit that counts the sampling signal with a clock signal having a constant period, a PWM circuit that inputs data of the first counter circuit and outputs a frequency modulation signal, and a PWM circuit that outputs a frequency modulation signal. 2. The circuit according to claim 1, further comprising a second counter circuit for counting the number of output pulses, and a comparator circuit for comparing a potential of an output signal of the PWM circuit with an input signal input from the mechanical contact. Chattering elimination circuit. 3. The chattering elimination circuit according to claim 2, wherein input data of the PWM circuit is programmed using a microprocessor, and a pulse width modulation signal is output.