JP3112376B2 - Vertical semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical semiconductor device, and more particularly to a shape of a connection electrode formed on a surface.

[0002]

2. Description of the Related Art Today, a power MOSFET that handles a large amount of power by connecting a large number of fine-pattern MOSFET cells in parallel.
It has been known. Power MOSFET 30 shown in FIG.
Is a vertical FET using a semiconductor substrate as a drain. The power MOSFET 30 includes a cell forming section 20, a gate extraction electrode 7, and a source extraction electrode 26. A cell as shown in FIG. 6 is formed in the cell forming section 20.

Each cell includes a source 8, a source electrode 16, a gate PolySi layer 17, and a gate insulating film (SiO 2).
₂ ) 13 is provided. Each cell has a gate PolySi
When a voltage exceeding the threshold voltage is applied to the layer 17, a channel is formed in the channel region 14, and a current flows from the drain 2 to the source 8.

The gate PolySi layer 17 of each cell is composed of an N ⁺ type semiconductor layer, and all the gate PolySi layers 17 are connected in a grid when viewed from the substrate surface side. Therefore, the gate extraction electrode 7
Even if a predetermined threshold voltage is applied to the cell, the on-state of the cell far from the gate extraction electrode 7 is delayed in time by the voltage drop, so that the switching speed is reduced. Also, if an instantaneous peak voltage is applied before the gate of a cell far from the gate extraction electrode 7 is turned on, the number of cells in the on state is small, so that the cells concentrate on some cells. As a result, the power MOSFET 30 is destroyed.

[0005] In order to solve such a problem that the timing of turning on differs for each cell, it has been proposed to form an aluminum comb finger portion 27 as shown in FIG. Since the resistance of aluminum is smaller than that of the N ⁺ type semiconductor layer, the voltage drop can be prevented.

[0006]

However, forming the above-mentioned aluminum comb finger portion 27 has the following problems.

In order to form the comb-shaped finger part, it is necessary to make the lower part a non-provided part where no cell is provided. As a result, the number of cells formed in the power MOSFET is reduced, which causes a problem of a reduction in current capacity and an increase in ON resistance. Attempting to increase the number of cells to solve these problems results in a large power MOSFET as a whole.

Further, as shown in FIG. 7, with respect to the cell (cell near α) at the end of the cell forming portion, the comb-shaped finger portion 27 blocks the flow of current to the source extraction electrode 26. Therefore, the current concentrates on the cell in the center of the cell formation portion (cell near β), which may cause spot destruction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a vertical semiconductor device which solves the above-mentioned problems, is excellent in the degree of integration, can reduce the ON resistance, and can prevent the occurrence of current concentration breakdown.

[0010]

According to a first aspect of the present invention, in the vertical semiconductor device, an unoccupied area where the cell is not provided is discretely provided in the cell forming portion, and each cell is provided in the unoccupied area. wherein a connection electrode connecting the semiconductor conductive layer, said semiconductor conductive layer than the conductivity of high connection electrode is
And the connection electrode is connected to a first conductor of each of the cells.
Current flow from the electrode for the electric region to the second extraction electrode
From the first extraction electrode so that the second
It is characterized by being arranged in parallel to the direction toward the extraction electrode.

[0011]

[0012]

In the vertical semiconductor device according to the first aspect, an unoccupied region where the cell is not provided is discretely provided in the cell forming portion, and the semiconductor conductive layer of each cell is formed in the unoccupied region. A connection electrode for connecting the semiconductor device;
A connection electrode having higher conductivity than the conductive layer is provided. This
Thus, the semiconductor conductive layer of each cell is electrically connected by the discretely provided connection electrodes. The connection electrode, before
Since the conductivity is higher than that of the semiconductor conductive layer , it is possible to reduce a voltage drop to a cell disposed apart from the first extraction electrode. In addition, the connection electrodes are discrete
A second extraction from the first conductivity type region electrode of each cell;
In order not to interrupt the flow of current to the
Parallel to the direction from the extraction electrode to the second extraction electrode
Are located in This allows current to collect in some cells.
Spot destruction due to the inside can be prevented.

[0013]

[0014]

[0015]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a power MOSFET 1 according to the present invention. The power MOSFET 1 includes a cell forming portion 20, a gate extraction electrode 7 as a first extraction electrode, and a source extraction electrode 26 as a second extraction electrode.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of each cell formed in a cell forming section 20 is the same as in the prior art. That is, as shown in FIG. 2B, an N + type semiconductor substrate 2 used as a drain
Over, formed by epitaxial Takisharu growth N- type layer 4 is provided. In the N − type layer 4, a P type region 6 which is a second conductivity type region is formed. In the P-type region 6,
As shown in FIG. 2A, an N + type source 8 as a first conductivity type region is formed in a ring shape by double diffusion.

In this embodiment, a region outside the source 8 in the P-type region 6 is a channel region 14 in which an electric path can be formed. On the channel region 14, a gate PolySi layer 17 as a semiconductor conductive layer is formed via a gate insulating film (SiO ₂ ) 13 as an insulating film. The gate PolySi layer 17 of each cell is connected to each other, and its surface is covered with a silicon oxide film.

The gate PolySi layer 17 is electrically connected to the gate extraction electrode 7 shown in FIG.
Therefore, by applying a voltage exceeding the threshold voltage to the gate extraction electrode 7, an N channel is formed in the P ⁺ type region 14, and the conduction between the drain 3 and the source 8 is established.

The source electrodes 16 of all cells are
They are connected to each other, and a part of them is electrically connected to the source extraction electrode 26 (aluminum wiring) shown in FIG. Therefore, the sources 8 of all cells are electrically connected to the source extraction electrodes 26 (aluminum wiring).

As shown in FIG. 1, the cell forming portion 20 in which the cells are formed is provided with discrete areas where the cells are not provided. A connection electrode 37 for connecting the gate PolySi layer 17 in the formation portion is provided. The connection electrode 37 is made of a substance having high conductivity. In the present embodiment, the connection electrode 37
Was composed of aluminum wiring.

As described above, the connection electrode 37 is provided at each cell formation portion.
Are provided discretely, the cells are partially electrically connected by the connection electrodes 37. The connection electrode 37 has a higher conductivity than the gate PolySi layer 17, so that a voltage drop to a cell located away from the gate extraction electrode 7 can be reduced. Therefore, it is possible to prevent a time delay from when a predetermined threshold voltage is applied to the gate extraction electrode 7 to when a cell disposed apart from the gate extraction electrode 7 is turned on. That is, the switching speed can be improved.

Further, since the connection electrodes 37 are provided discretely in the cell formation portion, the number of cells formed in the power MOSFET can be increased as compared with the case where comb-shaped finger portions are formed. In addition, the current capacity can be increased and the ON resistance can be reduced. An equivalent power MOSFET can be provided with a smaller semiconductor device. That is, a vertical semiconductor device with a high degree of integration can be provided.

Further, since the connection electrodes 37 are discretely provided in the cell formation portion, the current to the source extraction electrode 26 is not interrupted even in the cell at the end of the cell formation portion 20. Therefore, spot destruction due to concentration of current in some cells can be prevented.

In this embodiment, as shown in FIG. 1, the connection electrode 37 is arranged in parallel with the direction from the gate extraction electrode 7 to the source extraction electrode 26. Generally, the voltage drop is caused by the gate extraction electrode 7.
It gets bigger as you get away from it. In this way, by arranging in parallel with the direction from the gate extraction electrode 7 to the source extraction electrode 26, it is possible to further reduce the voltage drop to a cell arranged away from the first extraction electrode. Thereby, the switching speed of the cell arranged at a distance from the first extraction electrode is reduced.
It can be further improved.

The arrangement of the connection electrodes 37 is not limited to the above-described embodiment. For example, as shown in FIG. 4, the connection electrodes 37 may be arranged radially in the direction from the gate extraction electrode 7 to the source extraction electrode 26. , Other, the connection electrode 3
7 may be provided as long as they are provided discretely in the cell forming section 20.

In this embodiment, the vertical MOSF
Although the description has been given using the ET1, any device may be used as long as it is a vertical semiconductor device. For example, as shown in FIG. 3, an IGBT 80 (Insulated Gate Bipolar Transistor) is used.
It may be applied to r). IGBT80 is MOSFET
Is a semiconductor device having both a high input impedance characteristic and a low saturation voltage characteristic of a bipolar transistor.
As a basic structure, the vertical MOSFET 1 has an N ⁻ -type layer 4 formed on an N ⁺ -type semiconductor substrate 2, whereas an N ⁻ -type layer is formed on a P ⁺ -type semiconductor substrate. Only the difference. Other structures are the same, and the description is omitted.

The operating principle is that when the gate-emitter voltage is set to a positive bias, the MOSFET is turned on and the PN
The base current of the P transistor is supplied, and the IGBT is turned on. The off state is established by setting the gate-emitter voltage to zero bias or negative bias.

In this embodiment, the collector extraction electrode 87 constitutes a second extraction electrode. Further, the emitter PolySi layer 89 forms a first conductivity type region electrode, and the gate PolySi layer 88 forms a semiconductor conductive layer.

Further, the present invention may be applied to an IPD (Intelligent Power Device), an IPM (Intelligent Power Module), an IPS (Intelligent Power Switch) and the like.

In this embodiment, the gate PolySi layer is used as the semiconductor conductive layer.
Polycide, silicide, or the like may be used instead of the ySi layer. Thereby, the conductivity of the semiconductor conductive layer can be further increased.

In the above embodiment, the N type is replaced by the first type.
Although the description has been made using the N-channel transistor as the conductivity type and the P-type as the second conductivity type, the invention may be applied to a P-channel transistor.

[0032]

According to the vertical semiconductor device of the first aspect,
Wherein with the non-formation regions of the cell is not provided in the cell forming part discretely provided, the non-formation regions, a connection electrode for connecting the semiconductor conductive layer of each cell, the half
A connection electrode having higher conductivity than the conductive conductive layer is provided. This
Thereby, the semiconductor conductive layer of each cell is electrically connected by the discretely provided connection electrodes. Since the connection electrode has a higher conductivity than the semiconductor conductive layer , it is possible to reduce a voltage drop to a cell arranged away from the first extraction electrode. Therefore, it is possible to prevent a time delay in turning on the ON state and improve the switching speed.

Further, the connection electrodes are discrete and each
From the electrode for the first conductivity type region of the cell to the second extraction electrode
The first extraction electrode so as not to interrupt the current flow
Are arranged in parallel with the direction from
ing. This causes the current to concentrate on some cells
Can be prevented from being destroyed. Therefore, it is possible to provide a vertical semiconductor device capable of lowering ON resistance and preventing the occurrence of current concentration breakdown.

[0034]

[Brief description of the drawings]

FIG. 1 is a plan view of a power MOSFET 1 according to the present invention.

FIG. 2 is a diagram showing a structure of a cell of a power MOSFET 1. A is a plan view and B is a cross-sectional view.

FIG. 3 is a sectional view of a main part of each cell of the IGBT 80 according to the present invention.

FIG. 4 is a plan view showing another embodiment.

FIG. 5 is a diagram showing a conventional power MOSFET 30.

FIG. 6 is a diagram showing a cell structure of a conventional power MOSFET 30.

FIG. 7 is a diagram showing a state where a comb-shaped finger portion 27 is formed in a conventional power MOSFET 30.

[Explanation of symbols]

2 ....... N ⁺ -type semiconductor substrate 4 ....... N ^- -type layer 6 ....... P-type region 7 ....... gate extraction electrodes 8 .. Source region 12 Drain extraction electrode 13 Gate insulating film 14 Channel region 16 Source electrode 17 ..Gate PolySi layer 20... Cell forming part 26... Source extraction electrode

Claims (1)

(57) [Claims] 1. A A) a first conductivity type semiconductor substrate, B) the a cell forming portion provided on the semiconductor substrate surface, the cell having the following b1) ~b 2), cells form a plurality Forming portion, b1) a second conductivity type region, b2) a first portion provided in the second conductivity type region so as to form a region where an electric path can be formed between the second conductivity type region and the second conductivity type region.
A conductive type region; C) a semiconductor conductive layer provided via an insulating film on the conductive path forming region, the semiconductor conductive layer being interconnected; and D) being provided insulated from the semiconductor conductive layer. The second
An electrode for a first conductivity type region electrically connecting each of the first conductivity type regions in the conductivity type region; E) electrically connected to the semiconductor conductive layer and formed in a region other than the cell formation portion; A first extraction electrode; F) a second extraction electrode provided on the opposite side of the first extraction electrode via the cell forming portion, the second extraction electrode being electrically connected to the first conductivity type region electrode. 2) an extraction electrode; G) a third extraction electrode provided on the back surface of the semiconductor substrate ; and H) discretely providing an unoccupied region where the cell is not provided in the cell forming portion, and in the region, a connection electrode for connecting the semiconductor conductive layer of each cell, before
Vertical type with connection electrodes with higher conductivity than the semiconductor conductive layer
A semiconductor device, wherein : I) the connection electrode is a first conductivity type region electrode of each of the cells;
Do not block the flow of current from the pole to the second extraction electrode
Thus, the vertical semiconductor device is disposed in parallel with the direction from the first extraction electrode to the second extraction electrode.