JP3115262B2 - Receive signal phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception signal phase detection circuit, and more particularly to a reception signal phase detection circuit which is used in a receiver for receiving a digital modulated wave transmitted by a plurality of modulation methods having different C / Ns. Also, the present invention relates to a reception signal phase detection circuit that detects a reception signal phase angle.

[0002]

2. Description of the Related Art A digital modulated wave, for example, 8PSK, transmitted by a plurality of modulation schemes requiring different C / Ns.
Modulation, QPSK modulation, and BPSK modulation are combined for each time, and a broadcast receiver that receives a digitally modulated wave by the hierarchical transmission scheme repeatedly transmitted for each frame is a demodulated baseband signal (hereinafter, referred to as baseband signal). A signal is also referred to as a symbol stream), a frame synchronization signal is captured, a current reception signal phase rotation angle is obtained from a signal point arrangement of the captured frame synchronization signal, and demodulation is performed based on the obtained reception signal phase rotation angle. Absolute phase conversion is performed by rotating the baseband signal in the opposite phase so that the demodulated baseband signal matches the transmission signal phase angle.

As shown in FIG. 7, a conventional reception signal phase detection circuit includes a demodulation circuit 1, a frame synchronization detection circuit 2, a frame synchronization signal generator 3, and a delay which constitutes a block for detecting a reception signal phase. Circuits 41, 42, 0 ° /
180 ° phase rotation circuit 43, cumulative averaging circuit 45, 4
6. A reception signal phase determination circuit 47 for determining the phase of the reception signal by table conversion comprising a ROM.
Here, the frame synchronization detection circuit 2 and the frame synchronization signal generator 3 correspond to frame synchronization signal capturing means for capturing the frame synchronization signal from the demodulated baseband signal, and the delay circuits 41 and 42 perform frame synchronization from the demodulated baseband signal. This corresponds to an extracting unit that extracts a symbol stream in a signal period at a timing coincident with a bit stream of a reproduced synchronization signal captured by the frame synchronization signal capturing unit.

The conventional received signal phase detection circuit shown in FIG. 7 converts the frequency of a received digital modulated wave into a predetermined intermediate frequency, and supplies the frequency-converted intermediate frequency signal to a demodulation circuit 1 for demodulation. For example, a demodulated baseband signal I (8) having a quantization bit number of 8 bits from the demodulation circuit 1,
Q (8) (the number in parentheses indicates the number of bits, and hereinafter the number of bits is omitted and simply referred to as I or Q). The demodulated baseband signals I (8) and Q (8) are, for example, B
It is also sent to the frame synchronization detection circuit 2 to capture the PSK modulated frame synchronization signal.

Here, mapping for each modulation scheme on the transmitting side will be described with reference to FIG. FIG. 8A shows a signal point arrangement when 8PSK is used as a modulation method.
The 8PSK modulation method uses a 3-bit digital signal (a, b,
c) can be transmitted by one symbol, and the combination of bits constituting one symbol is (0, 0, 0), (0, 0,
1), to (1, 1, 1). These 3-bit digital signals are converted into signal point arrangements 0 to 7 on the transmission side IQ vector plane in FIG. 8A, and this conversion is called 8PSK mapping.

In the example shown in FIG. 8A, a bit string (0,
(0,0) in the signal point constellation {0}, the bit string (0,0,
1) in the signal point arrangement {1}, the bit string (0, 1, 1) in the signal point arrangement {2}, the bit string (0, 1, 0) in the signal point arrangement {3}, and the bit string (1, 0). , 0) to signal point arrangement 〃
4}, the bit string (1, 0, 1) is assigned to the signal point arrangement {5}.
The bit string (1, 1, 1) is converted into a signal point arrangement {6}, and the bit string (1, 1, 0) is converted into a signal point arrangement {7}.

FIG. 8B shows a signal point arrangement when QPSK is used as a modulation method. In the QPSK modulation method, a 2-bit digital signal (d, e) can be transmitted by one symbol, and the symbol The combination of bits to be set is (0,
0), (0, 1), (1, 0), and (1, 1). In the example of FIG. 8B, for example, the bit string (1, 1) is assigned to a signal point arrangement {1}, the bit string (0, 1) is assigned to a signal point arrangement {3}, and the bit string (0, 0) is assigned to a signal point arrangement. 5〃
The bit string (1, 0) is converted into a signal point arrangement {7}. Note that the relationship between the signal point constellation and the constellation number for each modulation scheme is 8P
The relationship between the signal point arrangement and the arrangement number is the same on the basis of SK.

FIG. 8 (c) shows a signal point arrangement when BPSK is used as a modulation method. In the BPSK modulation method, a 1-bit digital signal (f) is transmitted by one symbol. For example, the digital signal (f) is obtained by converting (1) into a signal point arrangement {0},
(0) is converted into a signal point arrangement {4}.

Next, the frame synchronization signal will be described.
In the hierarchical transmission method, the frame synchronization signal is transmitted after being subjected to BPSK modulation requiring the lowest C / N. Assuming that the bit stream of the frame synchronization signal composed of 16 bits is (S0, S1,..., S14, S15) and is sequentially transmitted from S0, (0, 0,
0,1,0,0,1,1,0,1,0,1,1,1,
1, 0) or the latter 8 bits are inverted (0, 0,
0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0,
0, 1) are transmitted alternately for each frame. Hereinafter, the symbol stream of the frame synchronization signal is referred to as {SYNCPAT}.
{Also, the symbol stream in which the latter 8 bits are inverted is also described as {nSYNCPAT}. This symbol stream is converted into a signal point constellation {0} or {4} by the BPSK mapping shown in FIG. 8C on the transmitting side, and the converted symbol stream is transmitted.

As described above, the BPSK-mapped frame synchronization signals {SYNCPAT} and {nSYNCPA}
The symbol stream of T〃 is transmitted to the frame synchronization detection circuit 2
When it is confirmed from the demodulated baseband signal that the signal is alternately and repeatedly received at regular frame intervals, it is determined that frame synchronization has been achieved, and a frame synchronization pulse is output every frame period.

Normally, in a hierarchical transmission system in which a plurality of required modulation systems having different C / Ns are combined for each time and transmitted repeatedly for each frame, header data indicating their multiplex configuration is multiplexed. After it is determined that frame synchronization has been achieved, header data indicating a multiplex configuration is extracted from a timing signal generated by a frame synchronization pulse output from the frame synchronization detection circuit 2. As a result, processing for each modulation scheme becomes possible only when the frame multiplexing configuration is known.

In other words, the demodulation circuit 1 operates as an 8PSK demodulation circuit until it is determined that the frame is synchronized. Therefore, depending on the phase state of the demodulation carrier wave reproduced by the carrier reproduction circuit in the demodulation circuit 1, the demodulation circuit 1 does not operate. The I-axis and the Q-axis of the IQ vector plane are compared with those on the transmitting side, and θ = 4
5 ° × n (n = 0, 1, 2, 3, 4, 5, 6, 7) phase rotation. For example, in the case of a frame synchronization signal transmitted after being subjected to BPSK modulation, in FIG. 8C, bit {1} is mapped to signal point constellation {0}, and bit "
A symbol stream of a frame synchronization signal BPSK-mapped to {0} signal point constellation {4} appears in signal point constellation {0}, {4} like the transmitting side depending on the phase state of the demodulation carrier. And the signal point arrangement {1}, {5} rotated by θ = 45 °, and θ = 9
There are eight different phases in which the frame synchronization signal is demodulated, such as when the phase is rotated by 0 ° and appears in the signal point constellation {2}, {6}.

[0013] In addition, a phase rotation occurs in the same way for a signal transmitted by QPSK modulation and 8PSK modulation. Assuming that the maximum number of phases of PSK combined in each time and repeatedly transmitted in each frame is eight, that is, in the case of 8PSK modulation, there are eight kinds of received signal phases each shifted by 45 °.

However, the phase rotation angle of the received signal can be obtained by comparing the signal point arrangement of the frame synchronization signal known on the transmission side with the signal point arrangement of the received frame synchronization signal. Hereinafter, a method of obtaining the phase rotation angle will be described.

A symbol stream of a frame synchronization signal demodulated into a baseband signal by demodulation circuit 1 (see FIG. 7) has a {SYNC} composed of bits {1} or {0}.
AT〃 or {nSYNCPAT} at the sending side in BPS
A K-mapped symbol stream, and
It is clear from the signal point arrangement that the symbol phase difference for bits {1} and {0} is 180 °. Therefore, all symbols corresponding to bit {0} in the symbol stream of the received frame synchronization signal are 1
A phase rotation of 80 ° results in a stream of 16 symbols for all bits {1}.

An average value of the obtained stream is obtained, and this is set as a received signal point arrangement for bit {1}. Since the signal point arrangement for the BPSK bit {1} is {0} on the transmitting side, the received signal phase rotation angle θ can be obtained by comparing this with the received signal point arrangement.

Here, the reception signal phase rotation angle θ and the phase rotation angle signal RT (3) which is the output of the reception signal phase detection circuit.
Is defined as shown in the following equation (1).

RT (3) = θ / 45 (1) where θ = n · 45 ° and n = 0, 1, 2, 3,
One of 4, 5, 6, and 7.

A further description will be given based on the conventional example shown in FIG. Upon receiving the frame synchronization pulse output from the frame synchronization detection circuit 2, the frame synchronization signal generator 3 captures the pattern {SYNCPAT}, {nSYN} of the captured frame synchronization signal.
A bit stream of a reproduction frame synchronization signal corresponding to CPAT # is generated, and the bit stream of the reproduction frame synchronization signal is supplied to a 0 ° / 180 ° phase rotation circuit 43. The frame synchronization signal generator 3 generates a frame synchronization signal section signal based on the captured frame synchronization signal section,
The frame synchronization signal section signal is supplied to delay circuits 41 and 4
2 is supplied.

The delay circuits 41 and 42 that have received the frame synchronization signal section signal are sent from the frame synchronization signal generator 3 and the symbol stream of the frame synchronization signal multiplexed on the baseband signal demodulated by the demodulation circuit 1. The symbol stream of the frame synchronization signal multiplexed on the baseband signal is delayed so that the timing of the bit stream of the reproduction frame synchronization signal coincides with the input terminal of the 0 ° / 180 ° phase rotation circuit 43.

The baseband signals DI (8) and DQ (8) delayed by the delay circuits 41 and 42 are 0 °
/ 180 ° phase rotation circuit 43. The output gates of the delay circuits 41 and 42 are opened only in the symbol stream section of the 16-symbol frame synchronization signal by the frame synchronization signal section signal output from the frame synchronization signal generator 3. Also, a 0 ° / 180 ° phase rotation circuit 43
, The delay circuits 41, 4
The timing of the reproduced frame synchronization signal output from the frame synchronization signal generator 3 and the symbol stream of the frame synchronization signal are matched by 2.

Here, the 0 ° / 180 ° phase rotation circuit 43
Is supplied via delay circuits 41 and 42 in the case of logical {0} based on logical {0} or logical {1} of a bit in the supplied bit stream of the reproduced frame synchronization signal. The corresponding symbol in the symbol stream of the frame synchronization signal multiplexed with the demodulated baseband signal is rotated by 180 ° in phase, and in the case of logic {1}, the demodulated baseband signal supplied via delay circuits 41 and 42 And outputs the corresponding symbol in the symbol stream of the frame synchronization signal multiplexed as is without rotating the phase.

At the input of the 0 ° / 180 ° phase rotation circuit 43, a symbol stream of a frame synchronization signal multiplexed on the demodulated baseband signal and a bit stream of a reproduced frame synchronization signal sent from the frame synchronization signal generator 3 Are matched by the delay circuits 41 and 42. Further, the output gates of the delay circuits 41 and 42 are opened by the frame synchronization signal section signal sent from the frame synchronization signal generator 3, and the symbol stream DI of the frame synchronization signal output by opening.
(8) If the bit stream of the reproduced frame synchronization signal is logic {0}, the DQ (8) is rotated by 180 ° in phase and sent to the cumulative averaging circuits 45 and 46.

FIG. 9A shows the received signal phase rotation angle θ = 0 °.
FIG. 9B shows the signal point arrangement of the frame synchronization signal when received at (absolute phase).
FIG. 11 shows a state of signal point arrangement of symbol streams VI (8) and VQ (8) after being converted in phase rotation circuit 43. Symbol streams VI (8), V
Q (8) is sent to cumulative averaging circuits 45 and 46, respectively, is added and averaged in a predetermined section, and the symbol streams AVI (8) and AVQ are added and averaged in each predetermined section.
(8) is output. Here, the symbol stream VI
(8) The averaging of the VQ (8) is performed because the signal point arrangement can be stably performed even when a small phase change or amplitude change of the received baseband signal due to deterioration of the received C / N occurs. It is to be required.

The received signal points [AVI (8), AVQ (8)] of the BPSK-mapped signal for bit {1} are obtained by the cumulative averaging circuits 45 and 46. Next, the received signal points AVI (8) and AVQ (8) are input to the received signal phase determination circuit 47, and the received signal points AVI (8) and AVQ (8) correspond to the phase rotation angle defined in the equation (1) by the received signal phase determination table shown in FIG. A 3-bit phase rotation angle signal RT (3) is obtained. For example, if the received signal phase rotation angle θ = 0 °, AVI
(8) The phase rotation signal whose signal point of AVQ (8) is determined by the received signal phase determination table is {0}.
Therefore, the phase rotation angle signal RT (3) has (0, 0,
0) is sent out. Also, the received signal phase rotation angle θ = 45
In the case of °, the phase rotation signal is similarly {1}, and therefore (0, 0, 1) is sent to the phase rotation angle signal RT (3).

Therefore, digital modulated waves transmitted by a plurality of modulation methods having different C / Ns are combined for each time, and digital modulated waves by the hierarchical transmission method repeatedly transmitted for each frame. In the broadcast receiver for receiving the signal, the phase rotation angle signal RT (3) is obtained by the reception signal phase detection circuit, and the baseband signals I (8) and Q (8) are converted using the phase rotation angle signal RT (3). Absolute phase conversion is performed by rotating in opposite phase.

[0027]

However, in the case of the above-mentioned conventional reception signal phase detection circuit, it is 0 °.
When the / 180 ° phase rotation circuit is configured by table conversion, its memory capacity is 128 kbytes (= 2 ¹⁶ × 16
bit), and if the received signal phase determination circuit is configured by table conversion, the circuit scale becomes large, for example, the memory capacity needs to be 2 ¹⁶ × 3 bits, and the circuit scale becomes large when integrated circuits are formed. There was a problem.

An object of the present invention is to provide a reception signal phase detection circuit which requires a small circuit scale.

[0029]

Means for Solving the Problems Claim 1 according to the present invention.
The received signal phase detection circuit described above has 2 ^N (N is a natural number) P
Reception for detecting a reception signal phase from a reception signal of an SK modulation wave
A signal phase detection circuit, wherein frame synchronization signal capturing means for capturing a frame synchronization signal from the demodulated baseband signal; and a symbol stream for a frame synchronization signal period from the demodulated baseband signal, which is captured by the frame synchronization signal capturing means, and reproduced. Extracting means for extracting at the timing coincident with the bit stream of the reproduced synchronization signal, and a symbol stream extracted by the extracting means, and the bits in the bit stream of the reproduced synchronization signal are set to logic {1} The corresponding symbol in the symbol stream extracted by the extracting means is added at the time of, and the symbol extracted by the extracting means when the bit in the bit stream of the reproduced synchronization signal is logic {0} Subtract the corresponding symbol in the stream for a predetermined period Over and judging a received signal phase based on the output of the cumulative addition and subtraction averaging circuit and a cumulative addition and subtraction averaging circuit to average.

According to the reception signal phase detection circuit of the present invention, the frame synchronization signal is captured from the demodulated baseband signal by the synchronization signal capturing means, and the symbol stream in the frame synchronization signal period from the demodulated baseband signal. Is extracted by the extracting means at a timing coincident with the bit stream of the synchronization signal captured by the frame synchronization signal capturing means. In a cumulative addition / subtraction averaging circuit, when a bit in the bit stream of the captured synchronization signal is logic {1}, a corresponding symbol in the symbol stream extracted by the extraction means is added, and the captured synchronization signal is added. When the bit in the bit stream of the signal is logic {0}, the corresponding symbol in the symbol stream extracted by the extracting means is subtracted and averaged over a predetermined period. The phase of the received signal is determined based on the output from the cumulative averaging circuit.

According to the reception signal phase detection circuit according to the first aspect of the present invention, the conventionally used 0 ° / 180 is used.
The phase rotation circuit and the cumulative addition and averaging circuit are replaced with a cumulative addition and subtraction averaging circuit, and the 0 ° / 180 ° phase rotation circuit becomes unnecessary, and the circuit scale is reduced.

According to a second aspect of the present invention, there is provided a reception signal phase detection circuit for receiving a 2 ^N (N is a natural number) PSK modulated wave.
Received signal phase detection circuit that detects the received signal phase from the signal
A is are captured and the frame synchronizing signal capturing means for capturing a frame synchronizing signal from the demodulated baseband signal, by the previous SL frame synchronizing signal capturing means symbol stream of a frame synchronizing signal period from the demodulated baseband signals,
Extraction means for extracting at a timing coincident with the bit stream of the reproduced synchronization signal, and a symbol stream extracted by the extraction means are input, and a bit in the bit stream of the reproduced synchronization signal is set to logic 〃0
と き に, the corresponding symbol in the symbol stream extracted by the extracting means is rotated by 180 ° for output, and when the bit in the bit stream of the reproduced synchronization signal is logic {1}, 0 ° / 180 ° phase rotation means for outputting the corresponding symbol in the symbol stream extracted by the extraction means without phase rotation, and accumulation for averaging outputs from the 0 ° / 180 ° phase rotation means over a predetermined period An averaging circuit,
Output from the cumulative averaging circuit is 22.5 degrees + 45 degrees x
n (n = 0, 1, 2, 3, 4, 5, 6, 7) ６a phase rotation circuit for rotating the phase, and a phase determination circuit for determining the phase of the output of the phase rotation circuit It is characterized by having.

According to the second aspect of the present invention, the frame synchronization signal is captured by the synchronization signal capturing means from the demodulated baseband signal, and the symbol stream in the frame synchronization signal period is transmitted from the demodulated baseband signal. Is extracted by the extracting means at a timing coincident with the bit stream of the synchronization signal captured by the frame synchronization signal capturing means. Receiving the bit stream extracted by the extracting means, when the bit in the bit stream of the captured synchronization signal is logic {0}, the corresponding bit in the symbol stream extracted by the extracting means is 180 ° When the bits in the bit stream of the acquired synchronization signal are logically {1} rotated in phase and the corresponding symbols in the symbol stream extracted by the extracting means are not phase-rotated to 0 ° / 180 The output from the phase rotation means, the output from the 0 ° / 180 ° phase rotation means is cumulatively averaged over a predetermined period and output from the cumulative average circuit, and the output from the cumulative average circuit is ｛22.5
° + 45 ° × n (n = 0, 1, 2, 3, 4, 5, 6, 7
One of the values)｝ The phase is rotated by the phase rotation circuit, and the phase of the output of the phase rotation circuit is determined by the phase determination circuit.

In this case, the conventional received signal phase determination circuit constituted by a table conversion by a ROM is a 0 ° / 180 ° constituted by a multiplier and an adder.
Since the phase rotation means and the configuration are replaced by a simple phase determination circuit, the circuit scale is reduced.

According to a third aspect of the present invention, there is provided a reception signal phase detection circuit for receiving a 2 ^N (N is a natural number) PSK modulated wave.
Received signal phase detection circuit that detects the received signal phase from the signal
A is are captured and the frame synchronizing signal capturing means for capturing a frame synchronizing signal from the demodulated baseband signal, by the frame synchronizing signal capturing means symbol stream of a frame synchronizing signal period from the demodulated baseband signals,
Extraction means for extracting at the same timing as the bit stream of the reproduced synchronization signal, and the symbol stream extracted by the extraction means are input, and the bits in the bit stream of the reproduced synchronization signal are set to logic # 1.
At the time of 〃, the corresponding symbol in the symbol stream extracted by the extraction means is added, and the bit in the bit stream of the reproduced synchronization signal is a logical 〃
0}, a corresponding symbol in the symbol stream extracted by the extracting means is subtracted, and an accumulative addition / subtraction averaging circuit for averaging over a predetermined period, and an output from the accumulative addition / subtraction averaging circuit are {22.5 ° + 45 ° × n (n =
0, 1, 2, 3, 4, 5, 6, 7)｝ A phase rotation circuit for rotating the phase and a phase determination circuit for determining the phase of the output of the phase rotation circuit are provided. Features.

According to the third aspect of the present invention, the frame synchronization signal is captured from the demodulated baseband signal by the synchronization signal capturing means, and the symbol stream in the frame synchronization signal period is demodulated from the demodulated baseband signal. Is extracted by the extracting means at a timing coincident with the bit stream of the synchronization signal captured by the frame synchronization signal capturing means. In a cumulative addition / subtraction averaging circuit, when a bit in the bit stream of the captured synchronization signal is logic {1}, a corresponding symbol in the symbol stream extracted by the extraction means is added, and the captured synchronization signal is added. When the bit in the bit stream of the signal is logic {0}, the corresponding symbol in the symbol stream extracted by the extracting means is subtracted and averaged over a predetermined period. The output from the accumulative averaging circuit is {22.5 ° + 45 ° × n (n = 0, 1, 2, 3,
(One value among 4, 5, 6, and 7)｝ The phase is rotated, and the phase of the output of the phase rotation circuit is determined by the phase determination means.

According to the third aspect of the present invention, there is provided a receiving signal phase detecting circuit according to the second aspect of the present invention, wherein the 0 ° / 180 ° phase rotating means and the accumulator are used. The addition and averaging circuit is replaced by a cumulative addition and subtraction averaging circuit, and a 0 ° / 180 ° phase rotation circuit is not required, thereby further reducing the circuit scale.

In the reception signal phase detection circuit according to the third aspect of the present invention, a phase rotation circuit is provided before the extraction means, and the phase of the reception signal is determined by the phase determination circuit based on the output of the cumulative addition / subtraction averaging circuit. You may make it.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a received signal phase detection circuit according to the present invention will be described with reference to embodiments. FIG. 1 is a block diagram showing a configuration of a reception signal phase detection circuit according to one embodiment of the present invention.

The reception signal phase detection circuit according to one embodiment of the present invention comprises a demodulation circuit 1, a frame synchronization detection circuit 2, a frame synchronization signal generator 3, and a block for detecting a reception signal phase. Delay circuits 41, 4
A 2,0 ° / 180 ° phase rotation circuit 43, cumulative averaging circuits 45, 46, a 22.5 ° phase rotation circuit 48, and a phase determination circuit 49 are provided.

That is, in the received signal phase detecting circuit according to the embodiment of the present invention, the cumulative averaging circuits 45, 4
6 output AVI (8) and AVQ (8)
The phase is supplied to the phase rotation circuit 48 to rotate the phase, and the phase rotation outputs RVI (8) and RVQ (8) are
9 to obtain the phase rotation angle signal RT (3), and replaces the reception signal phase determination circuit 47 configured by a table conversion comprising a ROM in the conventional example.
A 22.5 ° phase rotation circuit 48 composed of a multiplier, an adder, and the like, and a phase determination circuit 49 composed of a determination circuit such as a comparator are replaced with those of the conventional example. Same as case.

Therefore, in the received signal phase detecting circuit according to the embodiment of the present invention, the cumulative averaging circuits 45 and 46 are used.
AVI (8) and AVQ (8) are 22.5 °
The phase is supplied to the phase rotation circuit 48, and the following equation (2) and (3)
A phase rotation of 22.5 ° is performed according to the equation. The demodulation circuit 1, the frame synchronization detection circuit 2, the frame synchronization signal generator 3, and the blocks for detecting the phase of the received signal include delay circuits 41 and 42, a 0 ° / 180 ° phase rotation circuit 43,
The operation of the cumulative averaging circuits 45 and 46 is the same as that of the conventional example, and a description thereof will be omitted.

RVI = AVI cos (22.5 °) −AVQ sin (22.5 °) (2) RVQ = AVI sin (22.5 °) + AVQ cos (22.5 °) (3)

The output of the phase rotation according to the equations (2) and (3) is input to a phase determination circuit 49, which determines the phase rotation angle and outputs a phase rotation angle signal RT (3). . The phase rotation and the phase determination by the 22.5 ° phase rotation circuit 48 and the phase determination circuit 49 will be described with reference to FIGS. Conventionally, φ = 22.5 ° + 45 ° shown in the received signal phase determination table shown in FIG.
The received signal phase angle is determined from the input (AVI (8), AVQ (8)) based on the threshold angle of × n (= 0 to 7 integer) to determine the rotational phase signal RT (3). .

However, in the received signal phase detection circuit according to the embodiment of the present invention, (AVI (8), AVQ
Since (8)) was rotated by 22.5 °, the threshold angle was similarly rotated by 22.5 °, and φ = 22.5 ° + 45.
Obviously, it can be set to ° × n (= 0 to 7). This is shown in FIG. As a result, in the phase determination circuit 49, the output (RVI,
RVQ) as an input, it is sufficient to determine where the input (RVI, RVQ) is located in the phase area shown in FIG.

Therefore, the received signal phase angle is determined without using table conversion, and the input signals (RVI, RV
Q) can be easily determined by a comparator or the like. FIG.
The determination of the first, second, third, and fourth quadrants on the IQ vector plane shown in FIG.
It is obtained from the sign of Q). Further, a 45 ° × n (n = 1, 3, 5, 7) threshold for dividing each quadrant into two, for example, the phase rotation angle signal RT (3) = 0 or the phase rotation angle signal R
To determine whether T (3) = 1, the signals (RVI, RV
Q) is obtained from the magnitude of each absolute value. From such a relationship, the determination of the phase angle illustrated in FIG. 2 can be realized by the phase determination circuit 49 that performs the determination illustrated in FIG.

As a result, the received signal phase determining circuit 47 conventionally formed by table conversion using a ROM is composed of a 22.5 ° phase rotation circuit 48 formed by a multiplier and an adder, and a phase determined by a simple determining circuit. When the integrated circuit is used instead of the determination circuit 49, the circuit scale is greatly reduced.

Next, a description will be given of a first modification of the received signal phase detecting circuit according to the embodiment of the present invention.

In a first modification of the received signal phase detecting circuit according to the embodiment of the present invention, as shown in FIG. 4, 0 ° / 180 ° in the received signal phase detecting circuit according to the embodiment of the present invention. Instead of the phase rotation circuit 43 and the cumulative addition and averaging circuits 45 and 46, a cumulative addition and subtraction and averaging circuit 45A,
46A, the output DI of the delay circuits 41 and 42
(8), DQ (8) is accumulated by addition / subtraction averaging circuits 45A and 46
A, and the bit stream of the reproduced frame synchronization signal output from the frame synchronization signal
In the case of {}, the corresponding symbols in the symbol streams output from the delay circuits 41 and 42 are added, and if the bit stream of the reproduced frame synchronization signal is logical {0}, the delay circuits 41 and 42 The corresponding symbol in the symbol stream output from is subjected to a subtraction process, an operation is performed over the section of the frame synchronization signal section signal, an averaging process is performed, and the cumulative addition / subtraction averaging circuit 45
A, output AVI (8) AVQ (8) from 46A
The signal is sent to the 2.5 ° phase rotation circuit 48.

Here, when the operation of the 0 ° / 180 ° phase rotation circuit 43 in the reception signal phase detection circuit according to the embodiment of the present invention is examined, the 180 ° phase rotation is performed by reversing the sign of each axis. equal. Therefore, the cumulative addition in each axis of the received symbol rotated by 180 ° in phase is equal to the cumulative subtraction in each axis. Therefore, the 0 ° / 180 ° phase rotation circuit 47
And the cumulative addition and averaging circuits 45 and 46 can be replaced with cumulative addition and subtraction and averaging circuits 45A and 46A. The reason why the addition and subtraction results are averaged is that the signal point arrangement can be stably obtained even when a small phase change or amplitude change of the received baseband signal occurs due to deterioration of the received C / N.

Therefore, if the 0 ° / 180 ° phase rotation circuit 47 is constituted by a table conversion using a ROM, the storage capacity of the ROM constituting the 0 ° / 180 ° phase rotation circuit 47 is 128 kbytes (= 2 ^16). × 16b
It) can be reduced, and in the first modified example, the circuit scale can be further reduced as compared with the case of the received signal phase detection circuit according to the embodiment of the present invention.

Next, a description will be given of a second modification of the received signal phase detecting circuit according to the embodiment of the present invention.

As shown in FIG. 5, in a second modification of the reception signal phase detection circuit according to the first embodiment of the present invention, the reception signal phase detection circuit according to the first modification of the first embodiment of the invention is provided. 22. The phase of the demodulated baseband signal output from the demodulation circuit 1 is changed by the 22.5 ° phase rotation circuit 48 to 22.
5 °, the phase rotation output of the 22.5 ° phase rotation circuit 48 is sent to the delay circuits 41 and 42, and the outputs of the delay circuits 41 and 42 are supplied to the accumulation addition / subtraction circuits 45A and 46A. The output from 46A is sent to the phase determination circuit 49. That is, in the second modification of the reception signal phase detection circuit according to the embodiment of the present invention, the 22.5 ° phase rotation circuit in the first modification of the reception signal phase detection circuit according to the embodiment of the present invention is used. 48 is moved to a stage preceding the delay circuits 41 and 42.

In the second modification of the received signal phase detection circuit according to the embodiment of the present invention, the configuration is as described above. Therefore, FIG. 4 shows the received signal phase detection circuit according to the embodiment of the present invention. In addition, the outputs of the cumulative addition / subtraction averaging circuits 45A and 46A in the first modification are converted to a 22.5 ° phase rotation circuit 48.
Output RVI (8), RVQ rotated by 22.5 ° at
(8) is a case where the demodulated baseband signals I (8) and Q (8) are rotated by 22.5 ° in the 22.5 ° phase rotation circuit 48, and the demodulated baseband signals are rotated by 22.5 °. It is equal to the output (AVI, AVQ) obtained by performing the cumulative addition / subtraction average operation on the frame signal rotated by 22.5 ° in the cumulative addition / subtraction averaging circuits 45A and 46A. Therefore, the 22.5 ° phase rotation circuit 48 shown in FIG. 4 may be provided before the delay circuits 41 and 42 as shown in FIG.

The demodulated baseband signals I (8), Q (8)
5 may be included in the demodulation circuit 1 shown in FIG. 5, the output of which can be used, and the configuration shown in FIG. 5 is further simplified.

According to the second modification of the received signal phase detection circuit according to the embodiment of the present invention, the conventionally used 0 ° / 180 ° phase rotation circuit 43 and the cumulative averaging circuit 4 are used.
5 and 46 are replaced by cumulative addition / subtraction averaging circuits 45A and 46A, and the 0 ° / 180 ° phase rotation circuit 43 is assumed to be a ROM.
12 when configured by the table conversion by
The storage capacity of 8 kbytes (= 2 ¹⁶ × 16 bits) can be reduced, and the circuit scale can be reduced.

The received signal phase detecting circuit according to the above-described embodiment of the present invention, the first modified example and the second modified example thereof use the 22.5 ° phase rotation circuit 48 to realize the actual received signal. Although it is exemplified that the determination can be made with a simple circuit configuration instead of the table conversion for determining the phase, the phase rotation angle is not only 22.5 ° but also 6 °.
7.5 °, 112.5 °, 157.5 °, 202.5
°, 247.5 °, 292.5 °, 337.5 °.

In this case, the phase rotation angle signal RT (3) in the reception signal phase determination circuit may be made different. The above 67.5 °, 112.5 °, 157.5 °, 202.5
FIG. 6 shows the phase rotation angle signal RT (3) when rotating by 24 °, 247.5 °, 292.5 °, and 337.5 °.

[0059]

As described above, according to the received signal phase detection circuit of the present invention, the circuit scale can be reduced,
When the reception signal phase detection circuit is integrated, an effect that the chip area can be used effectively can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a reception signal phase detection circuit according to one embodiment of the present invention.

FIG. 2 is a diagram provided for describing an operation of the reception signal phase detection circuit according to the embodiment of the present invention;

FIG. 3 is a diagram for explaining an operation of the received signal phase detection circuit according to the embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a first modified example of the received signal phase detection circuit according to one embodiment of the present invention;

FIG. 5 is a block diagram illustrating a configuration of a second modification of the received signal phase detection circuit according to the embodiment of the present invention;

FIG. 6 is a diagram for explaining an operation when the phase rotation angle of the phase rotation circuit in the reception signal phase detection circuit according to the embodiment of the present invention is set to another rotation angle;

FIG. 7 is a block diagram showing a configuration of a conventional reception signal phase detection circuit.

FIG. 8 is a signal point arrangement diagram for explaining BPSK mapping;

FIG. 9 shows 0 ° / 180 ° in a reception signal phase detection circuit.
FIG. 4 is a signal point arrangement diagram of a frame synchronization signal after passing through a phase rotation circuit.

FIG. 10 is a diagram provided for explanation of a received signal phase determination table.

[Explanation of symbols]

 Reference Signs List 1 demodulation circuit 2 frame synchronization detection circuit 3 frame synchronization signal generation circuit 41 and 42 delay circuit 43 0 ° / 180 ° phase rotation circuit 45 and 46 cumulative addition and averaging circuit 45A and 46A cumulative addition and subtraction averaging circuit 48 22.5 ° phase rotation circuit 49 Phase judgment circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-60-10855 (JP, A) JP-A-53-137657 (JP, A) JP-A-6-244877 (JP, A) JP-A-11-107 27336 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/22 H04L 27/38

Claims (4)

(57) [Claims] (1)2 ^N (N is a natural number) PSK modulated wave reception signal
Signal phase detection circuit that detects the received signal phase from the signal
So,  Capture frame synchronization signal from demodulated baseband signal
Frame synchronizing signal acquisition means;
The vol stream is transmitted by the frame synchronization signal capturing means.
And the synchronized bit stream captured and played back
Extracting means for extracting at a coincident timing; and a symbol stream extracted by the extracting means.
Input the bit stream of the reproduced sync signal
When the bit inside is logic {1},
The corresponding symbol in the extracted symbol stream
Sum and bit stream of the reproduced synchronization signal.
When the bit in the system is logic {0},
Symbol in the extracted symbol stream
Is subtracted and averaged over a predetermined period.
And a received signal level based on the output of the accumulative addition and subtraction averaging circuit.
A received signal phase detection circuit for determining a phase. (2)2 ^N (N is a natural number) PSK modulated wave reception signal
Signal phase detection circuit that detects the received signal phase from the signal
So,  Capture frame synchronization signal from demodulated baseband signal
Frame synchronizing signal acquisition means;
BolstreamBeforeThe frame synchronization signal acquisition means
And the synchronized bit stream captured and played back
Extracting means for extracting at a coincident timing; and a symbol stream extracted by the extracting means.
Input the bit stream of the reproduced sync signal
When the bit inside is logic {0},
The corresponding symbol in the extracted symbol stream
180 ° phase rotated and output, and the reproduced
If the bit in the bit stream of the synchronization signal is logical {1}
Sometimes the symbol tree extracted by the extraction means
Output the corresponding symbol in the frame without phase rotation.
The output from the 0 ° / 180 ° phase rotation means and the output from the 0 ° / 180 ° phase rotation means for a predetermined period.
A cumulative averaging circuit for performing averaging on the output, and an output from the cumulative averaging circuit is {22.5 ° + 45 ° ×
n (n = 0, 1, 2, 3, 4, 5, 6, 7)
Value)｝ A received signal phase detection circuit comprising: a phase rotation circuit for rotating the phase; and a phase determination circuit for determining the phase of the output of the phase rotation circuit. (3)2 ^N (N is a natural number) PSK modulated wave reception signal
Signal phase detection circuit that detects the received signal phase from the signal
So,  Capture frame synchronization signal from demodulated baseband signal
Frame synchronizing signal acquisition means;
The vol stream is transmitted by the frame synchronization signal capturing means.
And the synchronized bit stream captured and played back
Extracting means for extracting at a coincident timing; and a symbol stream extracted by the extracting means.
Input the bit stream of the reproduced sync signal
When the bit inside is logic {1},
The corresponding symbol in the extracted symbol stream
Sum and bit stream of the reproduced synchronization signal.
When the bit in the system is logic {0},
Symbol in the extracted symbol stream
Is subtracted and averaged over a predetermined period.
Output from the averaging circuit and the accumulative addition / subtraction averaging circuit is 22.5 ° + 45 °
×n (n= 0, 1, 2, 3, 4, 5, 6, 7
Value)｝ A received signal phase detection circuit comprising: a phase rotation circuit for rotating the phase; and a phase determination circuit for determining the phase of the output of the phase rotation circuit. (4)2 ^N (N is a natural number) PSK modulated wave reception signal
To detect the received signal phase from the signal In the signal phase detection circuit
So,  Capture frame synchronization signal from demodulated baseband signal
The frame synchronization signal capturing means and the demodulated baseband signal are converted to {22.5 ° + 45 ° × n (n
= 0, 1, 2, 3, 4, 5, 6, 7)｝ Phase
A phase rotation circuit for rotating, and a symbol for a frame synchronization signal period from an output of the phase rotation circuit.
Stream by the frame synchronization signal capturing means.
Synchronized with the captured and reproduced bit stream of the sync signal
Extracting means for extracting at a matching timing; and symbol streams extracted by the extracting means.
Input the bit stream of the reproduced sync signal
When the bit inside is logic {1},
The corresponding symbol in the extracted symbol stream
Sum and bit stream of the reproduced synchronization signal.
When the bit in the system is logic {0},
Symbol in the extracted symbol stream
Is subtracted and averaged over a predetermined period.
Phase circuit that determines the phase of the output from the
A receiving circuit phase detection circuit, comprising: