JP3116355B2 - Manufacturing method of semiconductor device and semiconductor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor substrate in which a semiconductor thin layer is formed on a substrate with an insulating layer interposed therebetween, so-called SOI (Silicon-on-insula).
tor) a semiconductor device formed on a substrate.

Further, the present invention relates to a method for producing the SOI substrate, in particular,
The present invention relates to a method for manufacturing an SOI substrate having a plurality of island-shaped semiconductor regions by bonding semiconductor substrates.

[Summary of the Invention]

According to the present invention, in a semiconductor device, among a plurality of diffusion regions formed respectively in a plurality of element formation regions separated from a lower portion to a peripheral portion by an insulating film, a resistance element is formed between lowermost diffusion regions. Electrically connected by a polycrystalline silicon wiring layer that also serves as a semiconductor device, and the wiring layer is formed below and around the element forming region, and is taken out from a portion other than the element forming region, thereby achieving high density and high density. The characteristics are improved by enabling integration and reducing the parasitic capacitance.

In addition, the present invention provides a semiconductor device in which a plurality of lateral transistors formed continuously in an element formation region surrounded by an insulating film from the lower portion to the peripheral portion are stacked via an insulating film, and each lateral transistor is formed. By electrically connecting each of the opposing base regions and emitter regions via a wiring layer penetrating the insulating film, the cell size is reduced, and an integrated circuit having a plurality of transistors is formed. With high functionality and high integration,
This is to reduce the parasitic transistor and improve the characteristics.

Further, the present invention provides a method for manufacturing an SOI substrate, wherein after selectively forming a field insulating layer on a semiconductor substrate by selective oxidation by thermal oxidation, forming an insulating film by thermal oxidation on the entire surface including the field insulating layer; Then, after bonding the semiconductor substrate and another substrate, the semiconductor substrate is polished until a plurality of island-shaped semiconductor regions separated by the field insulating layer are exposed, thereby controlling the thickness of the island-shaped semiconductor regions. In addition to being capable of performing high-accuracy and easy operations, it is also possible to reduce damage and achieve high quality and high reliability of the SOI substrate.

[Conventional technology]

As shown in FIG. 13, a conventional logic circuit, for example, a NAND circuit is a so-called TTL (transistor) which is a typical example of a saturation logic circuit.
transistor logic). That is, this NAND circuit has a single-input multi-emitter NPN transistor T
It is constituted by AND _{circuits r1} and a resistor R _1, the output portion is formed of a NOT circuit comprising an NPN transistor T _r2 resistors R _2, output obtained by inverting the output of the AND circuit is made so as to obtain . Here, the multi-emitter and connected thereto for example three input terminals phi _A of the transistor T _r1, phi _B and phi _C
A voltage inputted respectively V _A, and V _B and V _C to the output terminal φ
_Assuming that the voltage output from _out is _Vout , the operation of this NAND circuit is expressed by the following equation when expressed by a Boolean equation.

That is, when any one of V _A , V _B and V _C is at a low potential (logically “0”), V _out becomes a high potential (logically “1”), and V _A , V _B and When V _{C is} all at a high potential (logically “1”), V _out is at a low potential (logically “0”).

A conventional analog circuit using bipolar transistors, for example, a current mirror circuit, connects between the bases of two lateral PNP transistors (hereinafter referred to as LPNP transistors) LT _r1 and LT _r2 as shown in FIG. with a current mirror portion that has been made with the diode LPNP transistor LT _r1 is directly connected between its collector and base, and a switching unit including two NPN transistors T _r3 and T _r4, NPN transistor T constituting the constant current source _r5
It is composed of In addition, a DC power supply (111) is connected between the base of the NPN transistor _Tr4 of the switching unit and the ground via a terminal φ, so that the switching unit constitutes a kind of differential amplifier. Then, the direct current through the input terminal phi _in the base of the PNP transistor T _r3 supply (111) when the input potential V _in the same potential is supplied, LP
NP transistor T _r1 input current from the I _in (= I _o) flows, even when the input current I _in the output current of the same value as I _out (= I _o) flows from LPNP transistor T _r2 simultaneously. In this case, the collector of the NPN transistor T _r5, the value of the input current I _in and the output current
I _out of the current of a value obtained by adding the value _{I in + I out (= 2I} o) is supplied.

[Problems to be solved by the invention]

However, the conventional logic circuit shown in FIG. 13, for example,
In a NAND circuit, for example, an NPN transistor T
Taking _r2 as an example, as shown in FIG. 15, a P-type element isolation region (113) is selectively formed on a P-type silicon substrate (112) and is surrounded by this element isolation region (113). An N-type buried layer (115) and an N-type epitaxial layer (116) are provided in the formed element formation region (114), and an N-type collector extraction portion (117) is provided on the N-type epitaxial layer (116). ), A P-type base region (118) and N surrounded by the base region (118).
And the emitter region (119) of the
Parasitic capacitance _CCS occurs at the junction between the N-type buried layer (collector region) (115) and the P-type silicon substrate (112). This parasitic capacitance C _CS is, for example, an NPN transistor _Tr2
Due to the characteristics described above, the operation speed in the process of shifting from the cut-off region to the saturation region is delayed, for example, causing a disadvantage that the characteristics of the transistor are deteriorated as a whole.

In a conventional analog circuit such as the current mirror circuit shown in FIG. 14, for example, the LPN on the input current I _in side is used.
Taking the P-transistor LT _r1 as an example, as shown in FIG. 16, a P-type element isolation region (122) is selectively formed on a P-type silicon substrate (121). )
An N-type buried layer (1) is formed in the element formation region (123) surrounded by
24) and an N-type epitaxial layer (125), and a P-type emitter region (1) on the N-type epitaxial layer (125).
26), an N-type base extraction portion (127) and a P-type collector region (128), respectively, in the lateral direction.
Emitter region (126) and P-type element formation region (122)
A parasitic PNP transistor _UTr1 is generated between the P-type collector region (128) and the P-type element isolation region (122). Similarly, the output current I _out of the parasitic to LPNP transistor T _r2 of side P
An NP transistor UT _r2 results. Input potential V _in the DC power applied to the base of the switching transistor T _r3 (11
In the case of the same potential as 1), the LPNP transistors LT _r1 and LT _r2
Since the base voltage V _{B of} is a relatively constant negative potential,
Less is no problem, even from the DC power supply (111) touching an input voltage V _in, when it becomes a high potential, since the current value thereof is large input current I _in is in proportion to, LPNP transistor LT _r1 and the base voltage V _B becomes a negative high potential of LT _r2, based LPNP transistor LT _r1 and LT _r2, voltage V _BE1 and V _BE2 between the emitter is increased, it becomes accompanied,
There is a disadvantage that the parasitic transistors _UTr1 and _UTr2 are turned on and the current mirror circuit does not operate normally. Also, this current mirror circuit is composed of an LPNP transistor LT _r1
And LT _r2 are arranged two-dimensionally, that is, the two LPNP transistors LT _r1 and LT _r1 are separated by an element isolation region (122).
To form a T _r2, because you have to constitute between them LPNP transistors LT _r1 and LT _r2 connected by a wiring on the surface side, at least two LPNP transistors LT
The configuration area of _r1 and LT _{r2 and} the area of the element isolation region (122) are required, and there is a limit to the high integration of the current mirror circuit.

By the way, recently, development of fabricating an VLSI using a so-called SOI substrate having a thin film single crystal silicon layer formed on an insulator has been advanced. Among various SOI substrate manufacturing methods, a bonding method that is considered to have the best crystallinity and excellent characteristics is the bonding method.

FIG. 17 shows an example of a method of forming an SOI substrate by a bonding method. First, as shown in FIG. 17A, a photolithography technique such as RIE (reactive ion A step of a predetermined pattern is formed by using (etching) such that a plurality of convex portions (132) are formed. Then, an insulating film such as SiO ₂ is formed on the main surface.
A film (133) is formed, and a flattening layer, for example, a polycrystalline silicon layer (134) is formed on the entire surface to fill the steps. The surface of the polycrystalline silicon layer (134) is polished flat.

Next, as shown in FIG. 17B, another mirror surface silicon wafer (135) is bonded to the flattened polycrystalline silicon layer (134) to form a bonded wafer (137). and SiO ₂ film (133) on a polishing stopper as shown, SOI substrate is polished from the back surface of the silicon wafer (141), having a plurality of island-shaped silicon regions separated by SiO ₂ film (133) (136) (138).

As described above, in the method of manufacturing the SOI substrate shown in FIG. 17, the projection (132) for determining the film thickness of the element formation region is formed by RIE in FIG. 17A. However, since the patterning cannot be performed with high precision, the thickness t of the island-shaped silicon region (46) that governs the characteristics of the device formed in the island-shaped silicon region (46) is small.
Accurately within one wafer, between a plurality of wafers, or between lots of 20 to 50 wafers as one unit, for example, ± 3%
It is very difficult to control within an error range of the order, and there is a disadvantage that reproducibility is poor. Also, RIE
There is also concern about damage to the projection (132).

The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor device in which parasitic capacitance can be reduced and characteristics can be improved.

Further, according to the present invention, a semiconductor device capable of achieving a reduction in chip size, achieving high integration of an integrated circuit having a plurality of transistors, reducing parasitic transistors, and improving characteristics. Is to provide.

Further, according to the present invention, the thickness of the island-shaped semiconductor region can be controlled with high accuracy and easily,
It is an object of the present invention to provide a method of manufacturing a semiconductor substrate which can reduce damage and realize high quality and high reliability of an SOI substrate.

[Means for solving the problem]

According to the semiconductor device of the present invention, a plurality of diffusion regions [(6), (4), which are respectively formed in a plurality of element formation regions (2) and (3), which are separated from a lower portion to a peripheral portion by an insulating film (1). (8), (9), (11)] and [(13),
(14), (16)], the lowermost diffusion region (6)
And (16) are electrically connected by a polycrystalline silicon wiring layer (4) also serving as a resistance element, and this wiring layer (4) is formed below and around the element forming regions (2) and (3). And formed out of portions other than the element formation regions (2) and (3).

In the semiconductor device of the present invention, the emitter region (53) and the base region are continuously formed from the lower part to the peripheral part in the element forming regions (52) and (57) surrounded by the insulating films (51) and (56). (54), collector region (55), emitter region (5
8), a plurality of lateral transistors LQ ₁ and LQ ₂ formed with a base region (59) and a collector region (60) are laminated via an insulating film (61), and the lateral transistors LQ ₁ and LQ ₂ Opposing base regions (54) and (5)
9), the emitter regions (53) and (58) are
It is configured to be electrically connected via wiring layers (62) and (63) penetrating 1).

Further, the manufacturing method of the present invention is a method of manufacturing a semiconductor substrate (101) having a plurality of island-shaped semiconductor regions (100) continuously surrounded by an insulating film from a lower portion to a peripheral portion. After selectively forming a field insulating layer (95) by selective oxidation by oxidation, an insulating film (97) by thermal oxidation is formed on the entire surface including the field insulating layer (95), and the thickness of the island-shaped semiconductor region is finally adjusted. Thermal oxidation conditions are set so as to obtain a desired film thickness, and then the semiconductor substrate (9
After bonding 1) and another substrate (99), the semiconductor substrate (9
1) is polished until a plurality of island-shaped semiconductor regions (100) partitioned by the field insulating layer (95) are exposed.

[Action]

According to the configuration of the first aspect of the present invention, the plurality of element forming regions (2) and (3) are separated from each other from the lower part to the peripheral part by the insulating film (1). Parasitic capacitance between diffusion regions (11) and (16) and substrate (41)
C _CS can be substantially eliminated (C _CS 0), and the characteristics can be improved.

In addition, since the lowermost diffusion regions formed in the plurality of element formation regions are connected by a polycrystalline silicon wiring which also serves as a resistance element, it is not necessary to separately form a resistance element, so that high performance is achieved. High integration is possible.

According to a second aspect of the present invention, including so uhh of the lateral transistor LQ ₁ and LQ ₂ was set to be laminated via an insulating film (61), a plurality of transistors LQ ₁ and is substantially L
Despite the presence of Q _2, the cell size is equivalent to one transistor in plan, and a plurality of transistors LQ
The chip size of the integrated circuit constituted by ₁ and LQ ₂ can be greatly reduced, and the integration of the integrated circuit can be increased.

Opposing base regions (54) and (59) of each lateral transistor, and emitter regions (53) and (5)
8) Since the so-called active regions are electrically connected via the wiring layers (62) and (63) penetrating the insulating film (61) existing between the opposing lateral transistors,
Wiring between elements is simplified, and higher functionality and higher integration can be achieved.

Since the transistors LQ ₁ and LQ ₂ are formed in the element forming regions (52) and (57) surrounded by the insulating films (51) and (56), the parasitic transistors can be substantially eliminated. The characteristics can be improved.

According to the third manufacturing method of the present invention, since the field insulating layer (95) is selectively formed on the semiconductor substrate (91) by selective oxidation by thermal oxidation, it is surrounded by the field insulating layer (95). The approximate film thickness of the semiconductor region (which will later become an element formation region) is set, and the film thickness of the semiconductor region can be finely controlled in the next overall thermal oxidation step.
Therefore, the thickness of the finally obtained semiconductor region can be controlled with high precision and ease.

Therefore, after bonding the semiconductor substrate (91) and another substrate (99), the semiconductor substrate (91) is bonded to the field insulating layer (95).
The film thickness of the island-shaped semiconductor region (element formation region) (100) after polishing until the plurality of island-shaped semiconductor regions (100) partitioned by is exposed is within one wafer, between a plurality of wafers, or between lots. Thus, the SOI substrate (101) having high reproducibility, high quality and high reliability can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing a logic circuit according to the first embodiment, in particular, a NAND circuit having a TTL configuration. FIGS. 2 and 3 are plan views showing a case where the NAND circuit shown in FIG. FIG. 3 is a sectional view taken along line AA in FIG. 2 and FIG. 2.

This NAND circuit is a multi-emitter type NP with one input
N transistor (hereinafter simply referred to as MNPN transistor) Q
Is constituted by AND _{circuits 1} and a resistor R _1, the output portion of one
Composed of NOT circuits consisting of NPN transistor Q ₂ and a resistor R _2. Then, the base and collector of NPN transistor Q ₂ of MNPN transistor Q _1, the power supply voltage V _CC is applied via the respective resistors R ₁ and R _2. Where MNPN transistor Q
_The potentials input to, for example, three input terminals φ _A , φ _B and φ _C connected to _one multi-emitter are V _A , V _B and V _{C, respectively.}
And then, when the voltage output from the output terminal phi _out and V _out, as shown in the following table i, V _A, one of V _B and V _C is a low potential, i.e. the level of logical "0" when, based MNPN transistor Q _1, emitter is forward biased, this has accompanied no NPN transistor Q ₂ is the characteristic on cutoff region, the output voltage V _out is the level of the high potential, i.e. a logical "1" Become. Further, as shown in Table 2 below, when all of V _A , V _B and V _C are at a high potential, that is, at a logical level of “1”, the base and emitter of the MNPN transistor Q ₁ are reverse-biased. Ban no NPN transistor Q ₂ is the output voltage V _out goes to the characteristics on the saturation region is the level of the low potential, i.e. logically "0".

As shown in FIGS. 2 and 3, this NAND circuit has two element forming regions (2) and (3) separated from each other by a SiO ₂ film (1) from the lower part to the peripheral part. respectively MNPN transistor Q ₁ and NPN transistor Q ₂ is formed on,
A wiring layer (4) electrically connects the lowermost diffusion regions, and the wiring layer (4) is connected to the Al wiring layer (5) from portions other than the element forming regions (2) and (3). Get out through. That is, as shown in FIG. 3, in one element formation region (2) surrounded by the SiO ₂ film (1) from the lower part to the peripheral part, a P-type base extraction part (6) and N A high-concentration region (7) is formed, and a P-type base region (8) and an N-type emitter region (9) surrounded by the base region (8) are formed thereon. The N-type high-concentration region (7) is formed by being drawn out to the upper portion, and together with the N-type medium-concentration region (10) of the intermediate layer, the collector region (11).
Is configured. Also, from the bottom to the periphery, SiO ₂
In the other element formation region (3) surrounded by the film (1), an N-type high-concentration region (12) is formed below the element formation region (3), and a P-type base region (13) and the base region ( An N-type emitter region (14) surrounded by 13) is formed. The N-type high-concentration region (12) is formed so as to be drawn out to the upper portion, and together with the N-type medium-concentration region (15) of the intermediate layer, the collector region (1) is formed.
Make up 6). Then, a region between the P-type base extraction portion (6) formed under the one element formation region (2) and the collector region (16) formed under the other element formation region (3) is, for example, polycrystalline. Electrical connection is made with a wiring layer (4) made of a silicon layer or the like, and extraction to the upper part of the wiring layer (4) is performed in two element formation regions (2) and (3).
From other locations via the Al wiring layer (5). Of the wiring layer (4), on the left side of the wiring layer (4l) resistive elements R ₁ P-type impurity is doped are formed, the right side of the wiring layer (4
The r) resistance element R ₂ are formed N-type impurity is doped. The Al wiring layer (5) for upper extraction is formed at the boundary between the left wiring layer (4l) and the right wiring layer (4r) so as to simultaneously straddle them. As shown in FIG. 2, the emitter region (9) formed on one of the element forming regions (2) is interposed via three Al wiring layers (17A), (17B) and (17C), respectively. Three input terminals φ _A , φ _B and φ _C
Is connected. An output terminal φ _out is connected to a collector region (16) formed on the other element formation region (3) via an Al wiring layer (18). The ground potential _VSS is applied via the Al wiring layer (19). Further, the collector region (11) of the one element formation region (2) and the base region (13) of the other element formation region (3) are connected via an Al wiring layer (20) at the upper portion thereof. The power supply voltage V _CC is applied to the upper extraction Al wiring layer (5).

Next, an example of a method of forming the above-described NAND circuit, that is, an example of a method of forming the above-described NAND circuit by using bonding of an SOI substrate will be described with reference to the process chart of FIG.

First, as shown in FIG. 4A, a silicon wafer (31)
After patterning the upper convex portions (32) and (33), an SiO ₂ film (34) is formed on the entire surface by, for example, a CVD method or the like. Then, the protrusions (which will later become the element formation regions (2) and (3)) (32) and (33) are formed in the base extraction portion (6) and the portion that becomes the collector region (16) (see FIG. 3). The windows (35) and (36) are opened.

Next, as shown in FIG. 4B, after a polycrystalline silicon layer (37) is formed on the entire surface by, for example, a CVD method or the like, a resist mask (38) is formed on one of the protrusions (32). afterwards,
N-type impurities are ion-implanted into the entire surface and the other protrusion (33)
The upper polycrystalline silicon layer (37) is doped with an N-type impurity.

Next, as shown in FIG. 4C, a resist mask (38)
Then, a resist mask (39) is formed on the other convex portion (33). Thereafter, a P-type impurity is ion-implanted into the entire surface, and the polycrystalline silicon layer (3
7) is doped with a P-type impurity.

Next, as shown in FIG. 4D, the polycrystalline silicon layer (3
7) is patterned to form a wiring layer (4), and a relatively thick SiO ₂ film (4) is formed on the entire surface including the wiring layer (4).
0) is formed. After that, the SiO ₂ film (40) is partially polished to flatten its surface, and then another silicon wafer (4) is polished.
1) is bonded on the flattened SiO ₂ film (40).

Next, as shown in FIG. 4E, a silicon wafer (31)
The element formation regions (2) and (3) surrounded by the SiO ₂ films (34) and (40) are selectively polished from the back surface of the substrate. The SiO ₂ films (34) and (40) are used in FIGS. 2 and 3.
An SiO ₂ film (1) is formed.

Next, as shown in FIG. 4F, a P-type base extraction portion (6) shown in FIG. 3 is provided in one element formation region (2).
A P-type base region (8), an N-type emitter region (9), and an N-type collector region (N-type high-concentration region (7) and N-type medium-concentration region (10)) (11) are formed. Also, in the other element forming region (3), the N-type collector region (N-type high-concentration region (12) and N-type medium-concentration region (15)) (16) and P-type The base region (13) and the N-type emitter region (14) are formed. Then, after opening a window (42) on the SiO ₂ film (34) between the element forming regions (2) and (3), an Al wiring layer (5) is formed in the window (42) and each diffusion layer is formed. Al wiring layer [(17A), (17B),
(17C)], (18), (19) and (20) (not shown) are formed to obtain the NAND circuit according to the present example.

As described above, according to this example, the two element formation regions (2) and (3) are separated from each other from the lower portion to the peripheral portion by the SiO ₂ film (1). ) And MNPN transistor Q ₁ formed in (3)
And each collector region (11) of the NPN transistor Q ₂ and (1
It is possible to eliminate substantially the parasitic capacitance C _CS between 6) and silicon wafers _{(41) (C CS 0)} . Thus, for example, N
Etc. can be improved operating speed in the process of transition to the saturation region from the characteristic on the cutoff region of the PN transistors Q _2, it is possible to improve the overall characteristics.

Further, since the wiring layer (4) of the polycrystalline silicon layer is formed below the element forming regions (2) and (3), only the Al wiring is formed above the element forming regions (2) and (3). Can be formed, the degree of freedom of the Al wiring pattern can be improved, and the step (that is, step coverage) becomes gentle, so that the Al wiring can be prevented from being disconnected.

Next, the configuration of an analog circuit having a plurality of bipolar transistors according to the second embodiment, in particular, the configuration of a current mirror circuit will be described with reference to FIGS.

FIG. 5 is a circuit diagram showing a current mirror circuit according to the present example. FIGS. 6 and 7 are plan views of the current mirror circuit shown in FIG. It is sectional drawing on the -B line.

This current mirror circuit, as shown in FIG.
One lateral type PNP transistor (hereinafter simply referred to as an LPNP transistor) LQ ₁ and LQ ₂ are connected between the bases, and the LPNP transistor LQ ₁ is directly connected between the collector and the base to form a current mirror section formed as a diode. a switching unit composed of two NPN transistors Q ₃ and Q _4, comprised of NPN transistors Q ₅ Metropolitan constituting the constant current source. Further, the DC power source (5 between ground and the base of NPN transistor Q ₄ of the switching unit via the terminal φ
0) is connected, the switching unit is adapted to constitute a kind of differential amplifier, each emitter of the LPNP transistor LQ ₁ and LQ ₂ supply voltage V _CC is applied. The collector of _one LPNP transistor LQ ₁ is connected to the collector of NPN transistor Q ₃ and the other LPNP transistor
The collector of the transistor LQ ₂ is connected to the collector of the NPN transistor Q _4. And, NP via input terminal φ _in
When N transistor Q ₃ input potential V _in the same potential as the DC power source (50) to the base of the supplied input current from the LPNP transistor _{Q 1 I in (= I o} ) flows simultaneously LPNP transistor Q
The output current I _out of the same value as the input current I _in from ₂ (= I _o) flows. At this time, the collector of the NPN transistor Q _5, current I _in the value obtained by adding the input current I _in and the output current I _out
+ I _out (= 2I _o ) is provided.

As shown in FIG. 7, this current mirror circuit includes a P-type emitter region (53) and an N-type base in an element formation region (52) surrounded by a SiO ₂ film (51) from the bottom to the periphery. the region (54) and P-type collector region (55) and LPNP transistor LQ ₁ obtained by forming laterally surrounded by the element formation region (57) in a SiO ₂ film (56) toward the peripheral portion from the bottom P-type emitter region (58), N-type base region (59)
And a P-type collector region (60) is formed in the lateral direction.
The LPNP transistor LQ ₂ is laminated via the SiO ₂ film (61), and the emitter regions (53) and (58) of the LPNP transistors LQ ₁ and LQ ₂ are connected to each other and the base regions (54) and (59) are connected to each other. They are electrically connected via embedded electrodes (62) and (63), respectively. Then, the power supply voltage V _CC is applied to the emitter region (53) of _one LPNP transistor LQ1 via the Al wiring layer (64), and the base region (5
4) and the collector region (55)
Is connected to the collector region of the NPN transistor Q ₃ (not shown) via the wiring layer (65). Also, in the emitter region of the other LPNP transistor LQ ₂ (58), the buried electrode (6
2), emitter region of _one LPNP transistor LQ ₁ (53)
And the power supply voltage V _CC is applied via the Al wiring layer (64),
Base region (59) is buried electrode (63), is connected to the collector region of the NPN transistor Q ₃ (not shown) via one of the base region of the LPNP transistor LQ ₁ (54) and the Al wiring layer (65). The collector region (60) of the other LPNP transistor LQ _2, as shown by the three-dimensional view of a plan view and FIG. 8 of Figure 6, the collector region of the NPN transistor Q ₄ via Al wiring layer (66) (Not shown).

Next, an example of a method of forming the current mirror circuit, that is, an example of a method of forming the current mirror circuit using bonding of an SOI substrate will be described with reference to FIGS.

FIG. 9 is a process chart showing a method for producing _one LPNP transistor LQ1. The steps will be described below in order. The sixth
Components corresponding to those in FIG. 7 and FIG. 7 are denoted by the same reference numerals.

First, as shown in FIG. 9A, a silicon wafer (71)
After patterning the upper convex portion (72), an SiO ₂ film (51) is formed on the entire surface by, for example, a CVD method or the like. Thereafter, the SiO ₂ film (5
After partially polishing 1) to flatten the surface, another silicon wafer (73) is bonded onto the flattened SiO ₂ film (51).

Next, as shown in FIG. 9B, the element formation region (52) surrounded by the SiO ₂ film (51) is formed by selective polishing from the back surface of the wafer (71).

Next, as shown in FIG. 9C, a P-type emitter region (53) and an N-type base region (54) are formed in the element formation region (52).
After forming the P-type collector region (55) in the lateral direction, an SiO ₂ film (61a) is formed on the upper surface thereof. Thereafter, windows (74) and (75) are opened at positions corresponding to the emitter region (53) and the base region (54), and then, for example, selective CVD is performed.
Embedded electrodes (62) in the windows (74) and (75)
a) and (63a) to form one LPNP transistor LQ ₁
Get.

Next, the other method of LPNP transistor LQ ₂ based on the process diagram FIG. 10.

First, as shown in FIG. 10A, a silicon wafer (81)
After patterning the upper convex portion (82), an SiO ₂ film (56) is formed on the entire surface by, for example, a CVD method or the like. After that, the SiO ₂ film (5
After partially polishing 6) to flatten the surface, another silicon wafer (83) is bonded on the flattened SiO ₂ film (56).

Next, as shown in FIG. 10B, an element formation region (57) surrounded by the SiO ₂ film (56) is formed by selective polishing from the back surface of the wafer (81).

Next, as shown in FIG. 10C, a P-type emitter region (58) and an N-type base region (59) are formed in the element formation region (57).
After forming the P-type collector region (60) in the lateral direction, an SiO ₂ film (61b) is formed on the upper surface thereof. Thereafter, windows (84) and (85) are opened at positions corresponding to the emitter region (58) and the base region (59), and then, for example, selective CVD is performed.
Embedded electrodes (62) in the windows (84) and (85)
b) and (63b) to form the other LPNP transistor LQ ₂
Get.

Then, as shown in FIG. 11 A, bonding the ninth surface side of one of the LPNP transistor LQ ₁ shown in Figure C and the other surface side of the LPNP transistor LQ ₂ shown in Figure 10 C. At this time, the embedded electrodes (62a) and (62b) and (63a) and (6
3b) Lamination is performed while aligning them so that they match each other.

Next, as shown in FIG. 11B, the wafer (73) on the front side of _one of the LPNP transistors LQ1 is selectively polished to form an SiO ₂ film (5
1) Expose.

Next, as shown in FIG. 11C, a window (8) is formed at a position corresponding to the emitter region (53) and the boundary between the base region (54) and the collector region (55) of _one LPNP transistor LQ1.
After opening 6) and (87), add A to windows (86) and (87).
(1) The wiring layers (64) and (65) are formed to obtain the Caleto-mirror circuit according to this example. At this time, the other LPNP transistor
Al wiring layer in the window and the window is formed in places corresponding to the LQ ₂ in the collector region (60) (66) is formed (see FIG. 8).

As described above, according to this example, two LPNP transistors
Since LQ ₁ and LQ ₂ are laminated via the SiO ₂ film (61), two LPNP transistors LQ ₁ and LQ ₂ are substantially formed.
Despite the existence of one LP
NP transistor LQ ₁ or be a cell size of LQ _2, the 2
One of it is possible to realize the high integration of the current mirror circuit composed of the LPNP transistors LQ ₁ and LQ _2. In addition, two LPNP transistors LQ ₁ and LQ ₂ are formed in the element formation regions (52) and (57) surrounded by the SiO ₂ films (51) and (56) from the bottom to the periphery. occur have parasitic PNP transistor is substantially longer exists, input potential V high potential LPNP transistors LQ ₁ and LQ ₂ is accompanied the reduction emitter of _in, between base potential V _BE1 and V
_{Even if BE2} becomes large, malfunction due to the parasitic PNP transistor does not occur, and the operating characteristics of the current mirror circuit can be improved.

Although the NAND circuit according to the first embodiment and the current mirror circuit according to the second embodiment are formed by bonding an SOI substrate, the NAND circuit according to the first embodiment and the current mirror circuit according to the second embodiment may be sequentially stacked using, for example, epitaxial growth and selective CVD. It may be formed using so-called SIMOX (separation by implanted oxygen).

Next, with respect to the SOI substrate serving as a base in forming the NAND circuit according to the first embodiment and the current mirror circuit according to the second embodiment, it is possible to control the film thickness of the element formation region with high precision. A possible method of manufacturing an SOI substrate will be described with reference to FIG.

First, as shown in FIG. 12A, a silicon wafer (91)
After forming the SiO ₂ film (92) by, for example, thermal oxidation or CVD method or the like above, the SiO ₂ film (92) an SiN film (93) on for example C
It is formed by a VD method or the like.

Next, as shown in FIG. 12B, after forming a resist mask (94) on the entire surface, the resist mask (94) is patterned, and the underlying SiN film (93) is patterned by the resist mask (94). Along the etching.

Next, as shown in FIG. 12C, a field insulating layer (95) is formed on the portion where the SiN film (93) has been removed by performing selective oxidation on the entire surface. Here, when the field insulating layer across the thickness d of the (95) and 100, the thickness d ₁ bulging upward relative to the silicon surface (l) is the total thickness d
The thickness d ₂ swelling downward with respect to the silicon surface (l) is 55% of the entire film thickness d. Thus, 1000 Å thickness d _A of the silicon surface portion serving as an element formation region (100) after set the thickness d ₂ bulging downward about 1000 Å (96)
If it is desired to control the thermal oxidation time, the total thickness d of the field insulating layer (95) should be about 2200 °.

Next, as shown in FIG. 12D, after removing the SiN film (93) and the SiO ₂ film (92) on the surface, the whole surface is subjected to thermal oxidation (so-called sacrificial oxidation) to form an SiO ₂ film (97). Form. At this time,
The silicon surface (l) is also oxidized and the silicon surface (l) recedes downward. The oxidation of the field insulating layer (95) also proceeds, but since the field insulating layer (95) is thick, the oxidation at the field insulating layer (95) can be ignored in the thermal oxidation in this case. By controlling the time of thermal oxidation of the SiO ₂ film (27), the element formation region (10
0) the thickness d _A is set for.

Next, as shown in FIG. 12E, a flattening layer, for example, a polycrystalline silicon layer (98) is formed on the entire surface to fill the steps of the SiO ₂ film (97). The surface of the layer (98) is polished flat.

Next, as shown in FIG. 12F, another silicon wafer (99) is bonded to the flattened polycrystalline silicon layer (98).

Next, as shown in FIG. 12G, the field insulating layer (9
5) Selective polishing from the back surface of the wafer (91) as a polishing slipper to form a plurality of island-shaped silicon regions (element formation regions) (100) partitioned by a field insulating layer (95)
Is formed to obtain the SOI substrate (101) according to the present example.

As described above, according to this example, in FIG. 12C, a field insulating layer (95) is selectively formed on the wafer (91) by selective oxidation, and a thermal oxide film (97) is further formed on the entire surface. Since the silicon surface portion (96) surrounded by the field insulating layer (95) is made to be an element formation region (100) later, the thickness d inflated below the silicon surface (l) of the field insulating layer (95). ₂ control the thermal oxidation time, etc.
Further, by controlling the thermal oxidation time and the like of the thermal oxide film (97), fine adjustment of oxidation becomes possible, and the film thickness of the element formation region (100) can be easily and accurately controlled, and RIE. Unlike patterning by such as, there is no worry about damage. Therefore, after bonding the silicon wafer (91) and another silicon wafer (99),
The silicon wafer (91) is divided into a plurality of island-shaped silicon regions (element forming regions) (10) by a field insulating layer (95).
0) can control the film thickness d _A within one wafer, with high precision between a plurality of wafers or between lots of the element forming region (100) after providing selective grinding to expose, good reproducibility And a high quality, highly reliable SOI substrate (101) can be obtained.

〔The invention's effect〕

According to the semiconductor device of the present invention, the lowermost diffusion region among the plurality of diffusion regions formed in the plurality of element formation regions separated from the lower portion to the peripheral portion by the insulating film is connected to the resistance element. Electrically connected by a polycrystalline silicon wiring layer that also serves as a semiconductor device, and this wiring layer is taken out from a portion other than the element forming region, so that parasitic capacitance can be reduced and characteristics can be improved. Can be realized. In addition, the number of separate formation of the resistance element is reduced, and higher function and higher integration can be achieved.

Further, in the semiconductor device according to the present invention, a plurality of lateral transistors in which a plurality of diffusion regions are formed in an element formation region continuously surrounded by an insulating film from a lower portion to a peripheral portion are stacked via the insulating film. At the same time, the opposing base regions and emitter regions of each lateral transistor are electrically connected via a wiring layer penetrating the insulating film, so that the cell size of the integrated circuit can be reduced. The above-described integrated circuit can have high functionality and high integration. Further, the number of parasitic transistors can be reduced, and the operation characteristics of the integrated circuit can be improved.

In the method for manufacturing a semiconductor substrate according to the present invention, after selectively forming a field insulating layer on a semiconductor substrate by selective oxidation by thermal oxidation, forming an insulating film by thermal oxidation on the entire surface including the field insulating layer, After bonding the semiconductor substrate and another substrate, the semiconductor substrate is polished until a plurality of island-shaped semiconductor regions (element formation regions) partitioned by the field insulating layer are exposed. Control of the film thickness in the region can be performed with high accuracy and ease, damage can be reduced, and high quality and high reliability of the SOI substrate can be realized. In addition, since the lower surface of the island-shaped semiconductor region is in contact with a dense thermal oxide film having good insulating properties, for example, when a semiconductor element such as a lateral transistor is formed in this island-shaped semiconductor region, an interface with the thermal oxide film is formed. Leakage current hardly occurs.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a NAND circuit according to a first embodiment, and FIG.
3 is a plan view showing the configuration of the NAND circuit, FIG. 3 is a cross-sectional view taken along line AA in FIG. 2, FIG. 4 is a process diagram showing an example of a method of forming the NAND circuit, and FIG. FIG. 6 is a circuit diagram showing a current mirror circuit according to an example, FIG. 6 is a plan view showing the configuration of the current mirror circuit, and FIG. 7 is a line BB in FIG.
Line cross-sectional view, three-dimensional view 8 figures showing a configuration of a current mirror circuit, Figure 9 is a process diagram showing an example of one of the LPNP forming method of a transistor LQ _1, Fig. 10 the other of the LPNP transistor LQ ₂ FIG. 11 is a process diagram showing an example of a method of forming a current mirror circuit, FIG. 12 is a process diagram showing a method of manufacturing an SOI substrate according to the present embodiment, and FIG. 13 is a conventional example. FIG. 14 is a circuit diagram showing a current mirror circuit according to a conventional example, and FIG. 15 is a circuit diagram showing a NAND circuit according to the related art.
Sectional view showing a structure of an NPN transistor T _r1 in the circuit, the 16
The figure is a cross-sectional view showing the configuration of the LPNP transistor LT _r1 in the current mirror circuit, and FIG. 17 is a process diagram showing a conventional SOI substrate manufacturing method. Q ₁ is a multi-emitter type NPN transistor, Q ₂ is an NPN transistor, (1) is an SiO ₂ film, (2) and (3) are element formation regions, (4) is a wiring layer, (5), (17A), (17B),
(17C), (18), (19), (20) are Al wiring layers, (6)
Is a base take-out part, (8) and (13) are base areas,
(9) and (14) are emitter regions, (11) and (16) are collector regions, LQ ₁ and LQ ₂ are lateral PNP transistors, and Q ₃ , Q ₄ and Q ₅ are NPN
Transistor, (50) is DC power supply, (51), (56),
(61) is an SiO ₂ film, (52) and (57) are element formation regions, (5)
3) and (58) are emitter regions, (54) and (59) are base regions, (55) and (60) are collector regions, (62) and (63)
Is an embedded electrode, (64), (65), and (66) are Al wiring layers, (9
1), (99) are silicon wafers, (92) is SiO ₂ film, (9)
3) is a SiN film, (95) is a field insulating layer, (96) is a silicon surface portion, (97) is a SiO ₂ film, (98) is a polycrystalline silicon layer, and (100) is an island-shaped silicon region (element formation). Area), (1
01) is an SOI substrate.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 21/8222 H01L 21/88 Z 27/00 301 29/72 27/04 27/06 29/73 (58) Investigated field (Int.Cl. . ^7, DB name) H01L 27/12 H01L 21/3205 H01L 21/331 H01L 21/762 H01L 21/822 H01L 27/00 301 H01L 27/04 H01L 27/06 H01L 29/73

Claims (3)

(57) [Claims] 1. A plurality of diffusion regions formed in a plurality of element formation regions separated from a lower portion to a peripheral portion by an insulating film, among the plurality of diffusion regions formed between the lowermost diffusion regions also serve as resistance elements. A semiconductor device, wherein the semiconductor device is connected by a polycrystalline silicon wiring layer, and the wiring layer is formed below and around the element formation region and is taken out from a portion other than the element formation region. 2. A semiconductor device comprising: a plurality of lateral transistors formed continuously in an element forming region surrounded by an insulating film from a lower portion to a peripheral portion; A semiconductor device, wherein regions and emitter regions are electrically connected via a wiring layer penetrating the insulating film. 3. A method of manufacturing a semiconductor substrate having a plurality of island-shaped semiconductor regions continuously surrounded by an insulating film from a lower portion to a peripheral portion, wherein a field insulating layer is selectively formed on the semiconductor substrate by selective oxidation by thermal oxidation. Forming, and forming an insulating film by thermal oxidation on the entire surface including the field insulating layer by setting thermal oxidation conditions such that the film thickness of the island-shaped semiconductor region becomes a final desired film thickness. Bonding a semiconductor substrate and another substrate, and polishing the semiconductor substrate until a plurality of island-shaped semiconductor regions separated by the field insulating layer are exposed. Recipe.