JP3119589B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a highly integrated gate array type semiconductor integrated circuit device comprising CMOS basic cells.

[0002]

2. Description of the Related Art In recent years, this type of gate array type semiconductor integrated circuit device has been developed by computer-aided design and manufacturing (CA).
(D, CAM) technology can be designed and manufactured at a short delivery time and at low cost, so that it is widely used as a semiconductor integrated circuit device of various kinds and small-quantity production used for personal computers, communication devices, home electric appliances and the like. ing.

In addition, the miniaturization and high integration of the manufacturing process are progressing. Particularly, in a gate array type semiconductor integrated circuit device having a gate length of 0.5 μm (0.5 μm rule) or less, the mounted circuit scale exceeds 500K gates. Operating frequency is 15
It is becoming higher than 0 MHz. These large-scale circuits have a circuit configuration that performs synchronous operation with an accuracy of several tens of picoseconds by using PLL or clock tree synthesis technology for high-speed operation. Therefore, the number of transistors operating simultaneously increases due to the increase in circuit scale and speed,
There is a problem that the circuit malfunctions due to the resulting noise.

FIG. 4 is a layout plan view showing one of a plurality of CMOS basic cells formed side by side in an internal region on a semiconductor chip of a general first semiconductor integrated circuit device of this kind. Referring to FIG. 1A, the CMOS basic cell of the first conventional semiconductor integrated circuit device includes a P-type diffusion region (P-type region) 1 and an N-type diffusion region (N-type region) 2; P-channel MOS transistors P1 and P2 formed in the n-type region 1 and having the same gate width Wp and gate length Wl, respectively, and two P-channel MOS transistors similarly formed in the n-type region 2 and having the same channel width Wn and channel length. N-channel type M
It is composed of OS transistors N1 and N2.

Source / drain (transistor) of P-channel MOS transistors P1 and P2 in P-type region 1
The N-type region 2 includes transistor regions of N-channel MOS transistors N1 and N2.

P, N channel type MOS transistor P
The set of N1, N1 and the set of P2, N2 are each a common gate electrode (polysilicide) GC formed of polysilicon.
1 and GC2.

Further, in this layout plan view, a wiring grid (×
) Indicate horizontal grids K1 to K12 and vertical grids KA to KC. As is well known, in this type of semiconductor integrated circuit device, all wirings are arranged along these lattices.

Referring to FIG. 4B which shows a circuit diagram of the basic cell, the transistors P1 and P2 have their sources connected in common, and the source terminal SP is connected to the common connection point.
Are connected, and the respective drains are connected to terminals DP1 and D2, respectively.
Connected to P2. Sources of the transistors N1 and N2 are commonly connected to each other, a source terminal SN is connected to the common connection point, and respective drains are connected to terminals DN1 and DN, respectively.
2 is connected. The gate terminals of the transistors P1 and N1 and the gate terminals of the transistors P2 and N2 are commonly connected to each other, and the respective gate electrodes G are connected.
It is connected to gate terminals G1 and G2 on C1 and GC2.

By laying out the basic cells vertically and horizontally, a base of a gate array type semiconductor integrated circuit device is formed.

Next, referring to FIGS. 5A, 5B and 5C which respectively show a layout diagram of an inverter circuit constituted by the basic cells of FIG. 4 and its circuit configuration and equivalent circuit, respectively.
This figure shows a configuration of one inverter circuit I1 including only transistors P1 and N1 for convenience of explanation. In this circuit, aluminum wirings W1 and W3 for power supply VDD and ground GND are respectively disposed on lattice KB-K3 (indicating the crossing point of KB and K3) and lattice KB-K10 and electrodes SP, Contact C1, C corresponding to SN
2 and output wiring W3 is connected to lattices KA-K5 and KA
-K8 connected to the contacts C3 and C4 respectively corresponding to the electrodes DP1 and DN1 to make this contact C3 an output terminal TO, and the input terminal TI arranged on the grid KA-K6 by the input wiring W4. And the gate electrode GC1 corresponding to the electrode G1 is connected to the contact C5 corresponding to the gate electrode GC1 by the lattice KA-K7.

Next, the operation of the conventional semiconductor integrated circuit device will be described with reference to FIG.
When the level of I changes from L level to H level,
The transistor P1 changes to the cut-off state and the transistor N1 changes to the conductive state, and the level of the output terminal TO changes from the H level to the L level. Conversely, when the level of the input terminal TI changes from the H level to the L level, the transistor P1 changes from the cut-off state to the conductive state.
Changes from the conducting state to the blocking state, and the output terminal T
The level of O changes from L level to H level.

At the moment of these operations, the inverter circuit I
Since the input terminal TI of 1 has an intermediate level other than H or L, a slight instantaneous current flows from the power supply VDD to the ground GND, which causes noise. This is not limited to the inverter circuit.
The same applies to all logic circuits such as the D circuit and the NOR circuit.

As described above, a gate array type semiconductor integrated circuit device is formed on a base circuit in which basic circuits such as an inverter circuit, a NAND circuit and an OR circuit are laid, and these are combined to form one circuit. Construct an LSI. Therefore, when the above-mentioned 0.5 μm rule or less, the mounted circuit scale exceeds 500K gates and the operating frequency is 150M.
In a large-scale circuit of Hz or higher, the number of simultaneously operating transistors increases due to the increase in the degree of integration and the speed of operation, and the circuit malfunctions due to the resulting noise.

On the other hand, even in a conventional gate array type semiconductor integrated circuit device having a medium density of 0.8 μm or more, noise is generated due to simultaneous operation of a large external output buffer for outputting a signal to the outside of the LSI. There is a problem. As a countermeasure, a second conventional semiconductor integrated circuit device described in Japanese Patent Application Laid-Open Nos. 3-290721 (Document 1) and 4-249421 (Document 2) uses a plurality of external output buffers using a delay circuit or the like. Are shifted to avoid simultaneous operation.

Further, a third conventional semiconductor integrated circuit device according JP flat 1 -119051 discloses (Document 3), simultaneous operation by shifting the timing of operation by changing the circuit constant of the transistor operated simultaneously In a gate array type semiconductor integrated circuit device in which the base is fixed, this is realized by changing the arrangement and the number of the source / drain contacts of the transistor.

[0016]

In the above-mentioned first conventional semiconductor integrated circuit device, noise caused by a large current flowing at the moment when a large number of transistors simultaneously operate is generated by simultaneous operation of large-scale circuits. However, there is a disadvantage that the circuit malfunctions.

The conventional second semiconductor integrated circuit device in which the above-mentioned disadvantages are alleviated by shifting the operation timing of the output buffer by adding a delay circuit has a large original circuit and further adds the additional circuit. This has the drawback that it is difficult to apply since it is impractical to further increase the circuit scale.

[0018] Further, by changing the arrangement and number of the source / drain contacts of the transistor, the operation timing is shifted so as to alleviate the above-mentioned disadvantage.
Of the present invention is 0.5 μm
(Below) In the process of large-scale gate array of rules,
The source / drain of the transistor is silicided for speeding up, and there is a disadvantage that the transistor constant is hardly changed depending on the number and arrangement of the contacts, so that application is impossible.

An object of the present invention is to provide a highly integrated gate array type semiconductor integrated circuit device which suppresses a malfunction due to operation noise even when a large-scale circuit is mounted and operated simultaneously.

[0020]

The semiconductor integrated circuit device of the present invention According to an aspect of the semiconductor integrated circuit device of the gate array type constructed by arranging several CMOS type basic cells double in the vertical and the direction of the lateral, the The CMOS type basic cell is the first conductive type.
The first transistor region formed in the electrical diffusion region is
Sharing the first, each drain and connected in parallel to the predetermined gate <br/> over-wide source of N divided transistors of split gate width divided by N of the first conductivity type Ru formed, the second transistor
And disposed adjacent to the first transistor region.
A second transistor formed in the diffusion region of the second conductivity type
Each share a drain region and a drain and source connected in parallel.
And N divided transistors having the divided gate width.
Third and fourth transistors of the second conductivity type, respectively
The first and third transistors formed of polysilicon;
A common first gate electrode and the second and fourth gates.
A common second gate electrode of the transistor and the polysilicon
Each of the first to fourth transistors formed by
The gate of each of the N divided transistors constituting
It is constituted by a N -1 single resistor elements to connect in series.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1A, which shows a layout plan view of one of the basic cells of a semiconductor integrated circuit device according to an embodiment of the present invention. The basic cell of the semiconductor integrated circuit device according to the embodiment includes a P-type diffusion region (P-type region) 1 and an N-type diffusion region (N-type region) 2, and is formed in the P-type region 1 and has the same gate length as the conventional one. Wl, four P-channel MOS transistors P1A, P1B, P2A, P2B having a gate width Wp / 2 of 1/2 of the prior art.
And 4 of the gate width Wn / 4 similarly formed in the N-type region 2.
N-channel MOS transistors N1A, N1B,
N2A and N2B.

The P-type region 1 includes source / drain (transistor) regions of P-channel MOS transistors P1A, P1B, P2A, P2B, and the N-type region 2 includes N-channel MOS transistors N1A, N1B, N2A. ,
Includes N2B transistor region.

P and N channel type MOS transistors P
A set of 1A, P1B, N1A, N1B and P2A, P2
A set of B, N2A, N2B is a common gate electrode (polysilicide) GC1A, G formed of polysilicon, respectively.
It is configured to have C2A. As described above, the gate width is divided into two, that is, the transistor is folded so that the gate electrode GC1 is formed at the folded portion.
A, GC2A are respectively connected to resistors RP1, RP2,
RN1 and RN2.

In the layout plan view, as in the conventional case, the horizontal grids K1 to K6 and the vertical grids K1 to K6 indicating the wiring grids (marked by X) which are the position coordinates of each part of the basic cell are provided for design support. 4 shows lattices KA to KE.

Referring to FIG. 1B, which shows a circuit configuration of the basic cell in a circuit diagram, the drains of transistors P1A and P1B are commonly connected, a drain terminal DP1 is connected to this common connection point, and the source of transistor P1A is connected. Is connected to the source terminal SP1. Transistor P2A,
The drains of P2B are commonly connected, the drain terminal DP2 is connected to this common connection point, and the source of the transistor P2A is connected to the source terminal SP2. The sources of the transistors P1B and P2B are commonly connected, and the source terminal SP is connected to this common connection point. Transistor N1
The drains A and N1B are commonly connected to each other, and a drain terminal DN1 is connected to this common connection point to form a transistor N1B.
The source of A is connected to the source terminal SN1. The drains of the transistors N2A and N2B are commonly connected, the drain terminal DN2 is connected to this common connection point, and the source of the transistor N2A is connected to the source terminal SN2.
The sources of the transistors N1B and N2B are commonly connected, and the source terminal SN is connected to this common connection point.

The gate terminals of the transistors P1A and N1A and the gate terminals of the transistors P2A and N2A are commonly connected to the gate terminals G1 and G2 on the gate electrodes GC1A and GC2A, respectively.

Next, referring to FIGS. 2A, 2B and 2C which respectively show a layout diagram of an inverter circuit constituted by the basic cells of FIG.
In this figure, the transistors P1A, P1B,
One inverter circuit I2 consisting of only N1A and N1B
Is shown. This circuit connects the aluminum wiring W1 of the power supply VDD to the contacts C1A and C1B disposed on each of the grids KA-K1 and KC-K1 and corresponding to the electrodes SP1 and SP, respectively, and the wiring W3 for the ground GND.
Are disposed on each of the lattices KA-K6 and KC-K6, and the contacts C2A and C2B corresponding to the electrodes SN1 and SN.
And the output wiring W3 is connected to the lattice KB-K2, KB-
K5 is connected to the contacts C3 and C4 corresponding to the electrodes DP1 and DN1, respectively, and the contact C3 is used as the output terminal TO. The input terminal W is connected to the input terminal TI provided on the lattice KA-K3 by the input wiring W4. Gate electrode G corresponding to electrode G1 with corresponding contact C5 and lattice KA-K4
Connect to C1A.

That is, in each set of the transistors P1A and P1B and the transistors N1A and N1B, the drain and source are connected in parallel, and the gate is connected to the resistor R.
They are connected in parallel via P1 and RN1, respectively. Therefore, the equivalent transistor capability in the static state is the same as the conventional transistors P1 and N1, even though the gate widths are Wp / 2 and 1/2.

Next, the operation of this embodiment will be described with reference to FIG. 2. When the level of the input terminal TI changes from L level to H level, first, the transistor P
1A is turned off and the transistor N1A is turned on, and at the same time, the level change of the terminal TI is caused by the resistance RP.
1 and RN1 to the transistors P1B and N1B, and the transistor P1B is turned off and the transistor N1B is turned on with a slight delay due to the resistance and the parasitic capacitance including the input capacitance of the transistor. The level of TO changes from H level to L level. Conversely, when the level of the input terminal TI is H
When the level changes from L level to L level, the transistor P
1A changes from the cut-off state to the conductive state, and the transistor N1A changes from the conductive state to the cut-off state.
The transistor P1B is slightly delayed by P1 and RN1.
Is turned on and the transistor N1B is turned off, and the level of the output terminal TO changes from L level to H level.

As described above, the gate width of each transistor is １ ／ of the gate width of the transistor of the conventional basic cell.
Therefore, the instantaneous current flowing due to the state transition during the operation of each transistor becomes small. That is, the conventional transistor is divided into two parts, each of which operates with a time lag, thereby dispersing the timing at which the instantaneous current flows, so that the temporal current peak is reduced and the noise generated by this is reduced. Is also reduced. On the other hand, since the static current capability is equivalent to the conventional one, the driving capability of the circuit can be maintained at the same level, and therefore, it is possible to replace the conventional circuit as it is.

As described above, the layout of the basic cell is such that the transistor is folded back.
Since the redundant portion of the gate electrode generated at the folded portion is used as a gate input delay resistor of the folded transistor, the area is not larger than that of a conventional basic cell, and does not become a hindrance to high integration.

Next, referring to FIG. 3, which is a plan view showing a basic cell according to a second embodiment of the present invention, the difference between this embodiment and the first embodiment is the gate width. To 1 /
4Wp, 1 / 4Wn, and the number of basic cell divisions is increased to 4
Divided, the conventional transistors P1, P2, N1, N2
Of transistors P1A, P1B, P1 corresponding to
C, P1D, P2A, P2B, P2C, P2D and transistors N1A, N1B, N1C, N1D, N2A, N
2B, N2C, and N2D.

In response, the transistors P1A, P1
B, the resistors RP1A, RP1B, RP1C, the gates of the transistors P2A, P2B, the gates of the transistors P2A, P2C, and the gates of the transistors P2A, P2B.
2B, between the gates of P2C and the transistor P2
A resistor RP2A between each gate of C and P2D,
RP2B and RP2C are provided. Similarly, transistor N
1A, between the gates of N1B, transistors N1B,
N1C between each gate and transistors N1C, N1
A resistor RN1A, RN1 between each gate of D
B and RN1C are provided with resistors RN2A, RN2B and RN2C between the gates of the transistors N2A and N2B, between the gates of the transistors N2B and N2C, and between the gates of the transistors N2C and N2D, respectively.

In this embodiment, the area of the circuit having the same capacity is slightly larger than that of the first embodiment, but the instantaneous current is further dispersed, so that it will tend to increase in the future. This type of noise reduction by simultaneous operation is even better.

[0035]

As described above, in the semiconductor integrated circuit device according to the present invention, the gate width of each transistor in the basic cell is divided by N , and each gate of the divided transistor is directly connected.
A delay circuit by adding N-1 resistance elements connected to the column
Transistor N of and so was to operate, 1 / N size corresponding to each of one of the transistor in each circuit
Since the components operate with a time lag from each other, the instantaneous current value at the time of the level transition operation is reduced, and there is an effect that a malfunction factor due to simultaneous operation of the large-scale circuit can be suppressed.

[Brief description of the drawings]

FIG. 1 is a plan view and a circuit diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a plan view showing an example of an inverter circuit formed by the semiconductor integrated circuit device of the present embodiment, a circuit diagram thereof, and a circuit diagram showing an equivalent circuit.

FIG. 3 is a plan view showing a second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 4 is a plan view and a circuit diagram showing an example of a conventional semiconductor integrated circuit device.

FIG. 5 is a plan view showing an example of an inverter circuit constituted by a conventional semiconductor integrated circuit device, a circuit diagram thereof, and a circuit diagram showing an equivalent circuit.

[Explanation of symbols]

1 P-type region 2 N-type region N1, N2, N1A, N1B, N1C, N1D, N2
A, N2B, N2C, N2D, P1, P2, P1A, P
1B, P1C, P1D, P2A, P2B, P2C, P2
D transistors C1 to C5 contacts GC1, GC2, GC1A, GC2A, GC1B, GC
2B Gate electrodes RN1, RN2, RP1, RP2, RN1A, RN1
B, RN2A, RN2B, RP1A, RP1B, RP2
A, RP2B resistance W1-W4 wiring

Claims (4)

(57) [Claims] 1. A semiconductor integrated circuit device of the gate array type constructed by arranging multiple several CMOS type basic cells in the vertical and the direction of the transverse, the CMOS-type basic cell, the diffusion of the first conductivity type In the area
The each share a first transistor region is formed Ru formed parallel connection of drain <br/> in and source a predetermined gate width from the N divide transistor of split gate width divided by N 1
A first transistor and a second transistor of the first conductivity type, and a second transistor disposed adjacent to the first transistor region.
Transistor region formed in the conductive diffusion region of
Before sharing drains and sources in parallel
The second is composed of N divided transistors having the divided gate width.
And the third and fourth transistors of the conductivity type, respectively, and the first and third transistors formed of polysilicon , respectively.
A common first gate electrode of the transistor and the second and
Fourth and common second gate electrode of the transistor, to connect the gate of each of the N divided transistors are formed in the polysilicon constituting each of the first to fourth transistors in series N the semiconductor integrated circuit device characterized by comprising a -1 resistive element. 2. A pre-Symbol N -1 single resistor elements, the first,
The semiconductor integrated circuit device according to claim 1, wherein formed in the diffusion region outside the region after the N-divided characterized Rukoto the second gate electrode. 3. The transistor according to claim 1, wherein N is 2, and each of the first, second, third and fourth transistors has its drain and source connected in parallel to divide the predetermined gate width into two.
The first transistor includes a first and a second divided transistor having a divided gate width, and includes one resistive element that connects between the gates of the first and the second divided transistors. The gate of the split transistor and the gate of the first split transistor of the third transistor are commonly connected to form a first input terminal, and the gate of the first split transistor of the two transistors and the gate of the first transistor are connected to each other. 2. The semiconductor integrated circuit device according to claim 1, wherein the second input terminal is formed by commonly connecting the gates of said four transistors to said first divided transistor. Wherein said Ri N is 4 der, the first, second,
Each of the third and fourth transistors is connected to the predetermined gate.
The first to fourth divided transformers each having a divided gate width obtained by dividing the width into four.
The semiconductor integrated circuit device according to claim 1, wherein the formed Rukoto from register.