JP3119700B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a common polycide electrode.
The present invention relates to a method for manufacturing a semiconductor integrated circuit in which an NMOS transistor and a PMOS transistor are formed.

[0002]

2. Description of the Related Art A CMOS integrated circuit, in particular, a Bi-CM having both a bipolar transistor and a CMOS transistor.
A gate electrode of a CMOS transistor in an OS integrated circuit generally uses polysilicon or a polycide structure in which silicide is used in a lower layer of polysilicon. The gate electrode is generally doped with an n-type impurity (hereinafter referred to as an n ⁺ gate).

Further, as shown in FIG. 4 and FIG.
Considering the short channel characteristics of the transistor,
The gate of the PMOS transistor portion is a P ⁺ gate doped with a P-type impurity, and the NMOS transistor portion is n ^+
Some CMOS integrated circuits have a ⁺ gate. This CMOS
The integrated circuit will be described with reference to FIGS. An N well 203 and a P well 205 are formed in a semiconductor substrate 201, and an isolation oxide film 207 for separating these wells is formed. A gate electrode 209 is formed on the semiconductor substrate 201 so as to cross the N well 203 and the P well 205. The gate electrode 209 includes a lower polysilicon layer 211 and an upper tungsten silicide layer 213.
And a polycide structure composed of The gate electrode 230 on the N well 203 is connected to the n ⁺ gate electrode,
The gate electrode 250 on the well 205 is a P ⁺ gate electrode.

[0004]

However, in the refractory metal silicide film such as tungsten silicide constituting the polycide electrode of the CMOS integrated circuit described above,
The diffusion coefficient of impurities is 10 ³ times or more as compared with that of the polysilicon film, and N-type impurities in the refractory metal silicide film during high-temperature heat treatment exceeding 700 ° C. such as BPSG flattening heat treatment as an upper insulating layer. P-type impurities diffuse into each other. For this reason, the impurity concentrations in the N ⁺ gate and the P ⁺ gate fluctuate, and the controllability of the threshold voltage deteriorates. As a result, the threshold fluctuates.

An object of the present invention is to provide a method of manufacturing an integrated circuit in which the impurity concentrations in the N ⁺ gate and the P ⁺ gate do not change.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method of manufacturing a semiconductor integrated circuit, comprising: a P-channel transistor having a first polycide electrode into which a P-type impurity is introduced; Impurity introduced second
An N-channel transistor having a polycide electrode, wherein the first and second polycide electrodes are substantially composed of one polycide electrode via a connection portion. After the impurity is introduced into the first and second polycide electrodes, a part of the silicide layer constituting the upper layer of the polycide electrode in the connection portion is removed, and thereafter, heat treatment is performed.

[0007]

1 to 3 show a first embodiment B of the present invention.
FIG. 7 is a schematic sectional view illustrating a method for manufacturing an i-CMOS integrated circuit.

The PM on the (100) surface of the P-type substrate 100
An N-type buried layer 105 is formed in the OS formation region 101 and the NPN bipolar formation region 103, and a P-type buried layer 111 is formed in the NMOS formation region 107 and the separation region 109 for electrically separating the NPN bipolar transistor. Form. Next, after an N-type epitaxial layer 200 is formed on the P-type substrate 100, N-type epitaxial layers 200 and NPN bipolar formation
The well layer 113 is formed with a P-well layer 115 in the region 107 where the NMOS is to be formed and the region 109 where the NMOS is to be separated, and the buried layers 105 and 111 are connected to the N-well 113 and the P-well 115. Further, the pad oxide film 117
And a silicon nitride film 119 are selectively formed.
An isolation oxide film 121 having a thickness of 3000 to 6000 ° is formed by COS oxidation. This is FIG. 1A in which each element formation planned region is formed. Here, silicon nitride film 1
19 has a thickness of 1000 to 2000 °.

Next, as shown in FIG. 1B, the silicon nitride film 119 is removed by known etching, the pad oxide film 117 is removed thereafter, and the silicon oxide film 119 is removed by known thermal oxidation.
A gate oxide film 123 of 0 to 200 ° is formed.

After a resist 125 is formed on the entire surface, an opening 129 is formed only in base region 127 of NPN bipolar region 103.
Is formed, and boron (B) ions are implanted to form a base implant layer 131 (FIG. 1C).

Annealing such as heat treatment is carried out for the purpose of removing the resist 125, activating impurities and removing crystal defects, thereby forming a base layer 133 having a Xj base of 0.2 to 0.3 μm (FIG. 1 ( d)) was obtained.

Further, after a polysilicon 135 is formed on the entire surface by using a well-known LPCVD technique (FIG. 1E), a resist 137 having an opening only in the PMOS formation region 101 is formed by using a well-known photolithography technique. By implanting boron ions by ion implantation, the PMOS formation region 101 is implanted.
Only the upper polysilicon 135 is a P ⁺ gate 139 (FIG. 1F).

In the same manner as in the above process, the NMOS formation region 10
A resist 141 having only an opening 7 is formed, and arsenic ions (As) are implanted by an ion implantation method.
An N ⁺ gate 143 is formed only on the polysilicon 135 on the formation region 107 (FIG. 1G).

Next, as shown in FIG.
1 is removed, and a heat treatment is performed to activate the gate impurities and recover the implant damage. Thereafter, tungsten silicide is formed on the polysilicon 135 by a known sputtering technique at 2000 to 3000 °, and the NMOS formation area 107 and the PMOS formation area 10 are formed by photolithography etching technique.
1, a gate electrode 145 having a polycide structure is formed. Here, the NMOS formation region 107 and the PMOS formation region 10
The one gate electrode 145 is connected by a single line as shown in FIG. 2, but is not shown in this cross-sectional view. Therefore, only a portion between the NMOS formation region 107 and the PMOS formation region 101 is shown as the connection gate electrode 147. Thereafter, a resist pattern (not shown) is formed by a well-known photolithography technique,
In the S formation region 101, BF ₂ ions are implanted by using a resist (not shown) and a gate electrode 145 having a polycide structure as a mask.
× 10 ¹³ ions / cm ² about implanted, LDDP ^- layer 14
Similarly, phosphorus ions of about 1 × 10 ¹³ ions / cm ² are implanted into the NMOS formation region 107 using a resist (not shown) and a polycide structure gate electrode 145 as a mask.
The DDN ^- layer 151 is formed.

Thereafter, a side wall PSG film is formed on the entire surface of the substrate by a CVD method, and then a side wall 153 is formed on the side surface of the gate electrode 145 having a polycide structure by using a well-known RIE etching technique. Note that a sidewall is also formed on the side surface of the connection portion gate electrode 147, but is omitted because it is different from the illustrated direction. Gate electrode 1
The gate oxide film 123 on the surface of the element formation region excluding the region below 45
Is removed by additional etching (FIG. 2 (i)).

Further, CVD on the entire surface of the substrate using organosilane.
TEOS CVD oxide film 155 formed by
Form. In FIG. 2J, the TEOS oxide film 155 on the LOCOS oxide film is omitted for convenience. Using a photolithography technique, a resist 157 having an opening in the collector removal region of the NMOS formation region 107 and the NPN bipolar formation planned region 109 is formed.
^An ion implantation of about ¹⁵ ions / cm ² is performed to form an N ⁺ source / drain (S / D) implantation layer 159 and a collector extraction implantation layer 161 (FIG. 2 (k)).

As in the above-described process, the PMOS formation region 10
1 and a resist 163 having an opening in the base extraction region of the NPN bipolar formation planned region 109 is formed.
₂ ions are implanted at about 2.5 × 10 ¹⁵ ions / cm ² to form a P ⁺ SD implant layer 165 and a base extraction implant layer 167 (FIG. 2).
(L)).

Thereafter, as shown in FIG. 2 (m), the resist 163 is removed, and a new NPN bipolar formation region 1 is formed.
A resist 168 having an opening only in the emitter formation region 165 is formed using a known etching technique.
A window is formed in the OS oxide film 155 for forming an emitter.

The resist 168 is removed, and a well-known LPCV
After the entire surface of the polysilicon for the emitter is generated by the D technique, arsenic ions are used as an impurity for forming the emitter in an amount of 2 × 10 2.
¹⁶ ions / cm ^{2 is} implanted, and then emitter polysilicon 169 is formed on the emitter formation region 165 by a known photolithography etching technique (FIG. 3 (n)).

NSG / BPSG 171 is applied to the entire surface of the substrate.
Then, the SBD (Schottky barrier diode) formation region 173 and the connection gate electrode 14 are formed by a known photolithography etching technique.
7 is provided with a silicide etch slit pattern 17 in the center.
5 is formed. At this time, the corresponding portion of the TEOS oxide film 155 is also removed (FIG. 3 (o)).

Thereafter, platinum (P) is formed on the entire surface by sputtering.
t) 177 is formed. Thereby, the SBD formation region 1
Platinum 177 is formed on the Si surface 73 and on the tungsten silicide surface of the slit pattern 175 (FIG. 3 (p)).

Next, as shown in FIG. 3 (q), a heat treatment (400 to 600 ° C.) for a silicide reaction is performed to selectively form a platinum silicide layer 179, and aqua regia is used to remove unreacted platinum. Perform an etch. With this aqua regia etching, the tungsten silicide of the slit pattern 175 is partially etched to form a silicide deleted portion 181. The reason that only tungsten silicide can be etched after the silicide reaction is that the platinum silicide layer is not formed in the silicide layer forming step in a self-aligned manner with the slit pattern 175. The surface of tungsten silicide has a rate of formation of a natural oxide film more than twice that of a normal silicon substrate surface, and an oxide film that affects the silicide reaction quickly after the completion of pre-platinum sputtering cleaning may be formed. Further, since the temperature of the silicide reaction is limited to 600 ° C. and the processing time is about 20 minutes, platinum cannot move in tungsten silicide, and the amount of Si supplied from tungsten silicide is considered to be extremely small. Even if platinum silicide is formed at the tungsten silicide interface, it is a thin film containing a lot of platinum, and a tungsten film exists under the platinum silicide film, and a tungsten film which is not dissolved by aqua regia etching should remain. From the above two points, it is considered that platinum silicide is not formed. Tungsten silicide is only subjected to heat treatment at a temperature of about 600 ° C .. Originally, crystallized tungsten silicide does not dissolve in aqua regia but dissolves in aqua regia because it is close to non-crystal just after sputtering.

Thereafter, as shown in FIG.
A heat treatment called a BPSG flow is performed for flattening the / BPSG film 171 and activating each of the implantation layers, and the P ⁺ S /
D implantation layer 165 in P ⁺ S / D layer 183, N ⁺ S /
The D implantation layer 106 is provided on the N ⁺ S / D layer 185, and the collector extraction implantation layer 161 is provided on the collector extraction layer 187.
In the base extraction implant layer 167, arsenic, which is an impurity, is diffused into the base extraction layer 189 from the emitter polysilicon 169 and diffused into the base layer 103, whereby the emitter layer 191 is formed. Also NSG / BPSG17
The BPSG 193 is flattened to 1.

Finally, a contact hole is opened by a well-known photolithographic etching technique, and a wiring 195 is formed to complete the semiconductor integrated circuit (FIG. 3 (s)).

FIGS. 6 and 7 are schematic sectional views showing a method of manufacturing a CMOS integrated circuit according to a second embodiment of the present invention. Hereinafter, the second embodiment will be described with reference to these drawings.

First, an N well layer 403 is formed in a region 401 where a PMOS is to be formed on the (100) surface of an N type substrate 400.
A P-well layer 407 is formed in a region 405 where an NMOS is to be formed, and then a pad oxide film 409 and a silicon nitride film 41 are formed.
1 to form a 3000-6000 LOCOS oxide film 4
13 is formed. Here, the thickness of the silicon nitride film 411 is 1000 to 2000 ° (FIG. 6A).

Next, as shown in FIG. 6B, the silicon nitride film 411 is removed by etching, the pad oxide film 411 is also removed, and the thermal oxidation method is used to remove 100 to 200 ° C.
Of the gate oxide film 415 is formed.

Thereafter, a polysilicon 417 is formed on the entire surface of the substrate 400 by using the LPCVD technique, a resist 419 having an opening only in the PMOS formation region 401 is formed by using the photolithography technique, and boron is ion-implanted. By implanting ions, only the polysilicon 417 on the PMOS formation region 401 has a P-type polysilicon gate (hereinafter referred to as P-type polysilicon gate).
⁺ (Abbreviated as gate) (FIG. 6C).

As in the above-described process, the NMOS formation region 40
By forming a resist 421 having only an opening 5 and implanting arsenic ions by an ion implantation method, only the polysilicon 417 on the NMOS formation region 405 becomes an N-type polysilicon gate (hereinafter abbreviated as an N-type gate) ( FIG. 6D).

Thereafter, the resist 421 is removed, and a heat treatment is performed to activate the gate impurities and recover the implant damage. Thereafter, tungsten silicide 423 is formed in a thickness of 2000 to 3000 ° by a sputtering technique. Next, the NMOS formation region 401 and the PM
A gate electrode 42 having a polycide structure is formed in the OS formation region 405.
5 is formed.

Here, the NMOS formation region 401 and the PMO
The gate electrode of the S formation region 405 is connected by one as in the first embodiment. FIG. 4 also shows the gate electrode connection portion 427 as in the first embodiment (FIG. 6E).

Next, as shown in FIG. 6F, a resist 431 having a silicide etch slit pattern 429 is formed at the center of the gate electrode connecting portion 427 by photolithography. Using the resist 431 as a mask, the tungsten silicide 423 is etched by a Freon-based dry etching method using the emission spectrum of tungsten (w) ions as an end point detection to form a silicide-removed portion 433.

Further, a resist 435 having an opening in the NMOS formation region 401 is formed by photolithography,
Arsenic ions are implanted at about 5 × 10 ¹⁵ ions / cm ² to form an N ⁺ S / D (source / drain) implant layer 437 (FIG. 7G).

As described above, a resist 439 having an opening in the PMOS formation region 405 is formed, and BF ₂ ions are added to the resist 439.
Perform ion implantation of about 5 × 10 ¹⁵ ions / cm ² and P ⁺
An SD implantation layer 411 is formed (FIG. 4G).

As shown in FIG. 7 (i), NS
G / BPSG film 413 has a CV of about 1000/7000
A heat treatment called a BPSG flow is performed for flattening the NSG / BPSG film 413 and activating each of the implantation layers formed by the D technique. By this heat treatment, the P ⁺ S / D implantation layer 411 becomes the P ⁺ S / D layer 415, the N ⁺ S / D implantation layer 437 becomes the N ⁺ S / D layer 417, and the silicide deleted portion 433 is formed when the CVD film is formed. Buried.

Next, a contact hole is opened by a photolithography etching technique, and a wiring 419 is formed to form a contact hole.
The MOS integrated circuit is completed (FIG. 7 (j)).

FIGS. 8 and 9 are schematic sectional views showing a method of manufacturing a CMOS integrated circuit according to a third embodiment of the present invention. The third embodiment will be described below with reference to FIGS.

First, an N well layer 503 is formed in a region 501 where a PMOS is to be formed on the (100) surface of the N-type substrate 500.
A P-well layer 507 is formed in a region 505 where an NMOS is to be formed, and then a pad oxide film 509 and a silicon nitride film 51 are formed.
Form one. Then, using this silicon nitride film 511 as a mask, LOCOS oxide film 51 of 3000 to 6000 ° is formed.
3 is formed (FIG. 8A). Here, the thickness of the silicon nitride film 513 is 1000 to 2000 °.

Next, the silicon nitride film 513 is removed by etching, then the pad oxide film 511 is also removed, and a gate oxide film 515 of 100 to 200 ° is formed by thermal oxidation (FIG. 8B).

As shown in FIG. 8C, L
Polysilicon 517 is formed on the entire surface by using the PCVD technique. Further, a resist 519 having an opening only in the PMOS formation region 501 is formed on the polysilicon 517 by using photolithography technology, and boron ions are implanted by ion implantation using the resist 519 as a mask, so that P
Only the polysilicon 517 on the MOS formation region 501 is a P-type polysilicon gate (hereinafter abbreviated as P ⁺ gate).

Similarly to the above, a resist 521 having an opening only in the NMOS formation region 505 is formed, and arsenic ions are implanted by ion implantation using the resist 521 as a mask.
Only the polysilicon 519 on the OS formation region 505 is an N-type polysilicon gate (hereinafter abbreviated as an N ⁺ gate) (FIG. 8D).

Next, as shown in FIG.
21 is removed, and a heat treatment is performed to activate the gate impurities and recover the implant damage. Thereafter, tungsten silicide 523 is formed on polysilicon 519 by a sputtering technique at 2000 to 3000 °. Next, a gate electrode 525 having a polycide structure is formed in the NMOS formation region 501 and the PMOS formation region 505 by a photolithographic etching technique. Further, as in the first and second embodiments, a gate electrode connecting portion 527 having a polycide structure is also shown.

Thereafter, a resist 529 having an opening in the NMOS formation region 505 is formed by photolithography,
Arsenic ions 5 × 10 ¹⁵ ions / cm ² are implanted into the N ⁺ S / D (source / drain) implant layer 5.
31 are formed (FIG. 8F).

In the same manner as described above, a resist 531 having an opening in the PMOS formation region 501 was formed, and BF ₂ ions were implanted at about 2.5 × 10 ¹⁵ ions / cm ² to form a P ⁺ SD implant layer 533. (Fig. 9
(G)).

As shown in FIG. 9H, N
SG / BPSG film 535 is 1000/7000 CVD
Formed by technology.

The BPSG on the central portion of the gate electrode connecting portion 527 is formed on the substrate 500 by photolithographic etching.
The film 535 is etched to form a silicide etch slit pattern 537 (FIG. 9 (i)).

Further, the tungsten silicide 523 of the gate electrode connecting portion 527 is etched by aqua regia using the BPSG film 535 as a mask, and the silicide removed portion 5 is etched.
Form 39. Thereafter, a heat treatment called a BPSG flow is performed for flattening the BPSG film 535 and activating each of the implantation layers, and the P ⁺ S / D implantation layer 533 is formed.
Represents a P ⁺ S / D layer 541 and an N ⁺ S / D implantation layer 531
Becomes the N ⁺ S / D layer 543 (FIG. 9 (j)). In FIG. 9J, the slit pattern 537 is open but is filled during the BPSG flow.

Finally, a contact hole is opened by a photolithographic etching technique, and a wiring 545 is formed.
The MOS integrated circuit is completed (FIG. 9 (k)).

[0049]

As described above in detail, according to the present invention, after forming the P-type gate and the N-type gate in the polycide gate, the silicide-removed portion is provided at the gate electrode connecting portion of the gate electrode. Thereafter, even if a heat treatment such as activation (annealing) of the source / drain implant layer is performed, the P-type impurity of the P-type gate and the N-type impurity of the N-type gate do not mutually diffuse through the silicide film. As a result, the increase in the equivalent resistance of the gate electrode can be minimized, and the variation in the threshold value and the reproducibility of the MOS transistor are greatly improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a process sectional view of the first embodiment of the present invention.

FIG. 3 is a process sectional view of the first embodiment of the present invention.

FIG. 4 is a cross-sectional perspective view of a conventional CMOS circuit.

FIG. 5 is a cross-sectional view of a conventional CMOS circuit.

FIG. 6 is a process sectional view of a second embodiment of the present invention.

FIG. 7 is a process sectional view of a second embodiment of the present invention.

FIG. 8 is a process sectional view of a third embodiment of the present invention.

FIG. 9 is a process sectional view of a third embodiment of the present invention.

[Explanation of symbols]

 135, 417, 517 Polysilicon 423, 523 Silicide 145, 425, 525 Gate electrode 147, 427, 527 Gate electrode connecting part 181, 433, 537 Silicide removing part

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/092 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 27/06 H01L 21/8222 H01L 21/8249 H01L 21/28

Claims (2)

(57) [Claims] 1. A semiconductor device comprising: a P-channel transistor having a first polycide electrode into which a P-type impurity is introduced; and an N-channel transistor having a second polycide electrode into which an N-type impurity is introduced. In a method of manufacturing a semiconductor integrated circuit, wherein a second polycide electrode is substantially connected via a connection portion having a polycide structure, after introducing impurities into the first and second polycide electrodes, the polycide electrode of the connection portion A method of manufacturing a semiconductor integrated circuit, comprising removing a part of a silicide layer constituting an upper layer of the semiconductor integrated circuit, and thereafter performing a heat treatment. A step of preparing a semiconductor substrate having a CMOS transistor forming region and a bipolar transistor forming region; and a step of: forming a P-channel transistor having a first polycide electrode on the semiconductor substrate in the CMOS transistor forming region; Forming an N-channel transistor having a polycide electrode, wherein the first polycide electrode and the second polycide electrode are substantially connected to each other via a connection portion having a polycide structure; Forming a bipolar transistor having a collector electrode, a base electrode, and an emitter electrode on the semiconductor substrate in the bipolar transistor formation region; and forming a platinum layer extending from the polycide electrode to the base electrode. Heat treating the platinum layer, Forming a platinum silicide layer in contact with the base electrode of the polar transistor; and, simultaneously with removing the platinum layer, removing a part of a silicide layer constituting an upper layer of the polycide structure of the connection portion. A method for manufacturing a semiconductor integrated circuit.