JP3123505B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device relating to a "bipolar transistor having a heterojunction of" Si "and" Si containing Ge "".

[0002]

2. Description of the Related Art With the speeding up of a silicon bipolar transistor, a mixed crystal containing Ge is used in a base region, an "energy band gap" is changed to generate an electric field inside the base, and a "carrier" injected into the base is generated. A technique for increasing the operation speed of a transistor by accelerating the transistor has been used.

[0003] The above prior art will be described with reference to FIGS. 2 and 3. FIG. 2 is a view for explaining a conventional manufacturing method, and is a cross-sectional view in the order of manufacturing steps including steps A to C. FIG. 3 is a view illustrating steps D to F following step C in FIG. It is a manufacturing process order sectional drawing.

In a conventional manufacturing method, an N-type buried layer 2 serving as a collector electrode is selectively formed on a P-type semiconductor substrate 1 as shown in a step A of FIG. Layer 3 is grown to a thickness of 0.5 μm. Next, after the oxide film 4a is formed with a thickness of 50 nm, the oxide film 4a in the element isolation groove 5 region is selectively etched.

Next, as shown in step A, using the oxide film 4a as a mask, an element isolation groove 5 penetrating the N-type buried layer 2 is formed to define an element formation region. Subsequently, after the oxide film 4b is grown and filled in the element isolation trench 5,
The oxide film 4b on the surface is removed. Then, phosphorus is ion-implanted into a part of the element formation region to form a collector extraction region 6 reaching the N-type buried layer 2.

Next, as shown in step B of FIG. 2, after a polycrystalline silicon film 7a containing boron and having a thickness of 0.3 μm is formed, it is patterned as a base lead electrode. Subsequently, a nitride film 8a having a thickness of 0.2 μm is formed.

Next, as shown in step C of FIG. 2, the nitride film 8a and the polycrystalline silicon film 7a are selectively etched to expose the oxide film 4a, and an opening 9 for forming a base is formed. Subsequently, the oxide film 4a exposed in the opening 9 is selectively etched by isotropic etching.
The type epitaxial layer 3 is exposed. Further overetching is performed to form an eaves portion 10 of about 0.1 μm.

Next, as shown in a step D of FIG. 3, a base layer 11 is formed on the exposed N-type epitaxial layer 3.
70 nm P-type epitaxial layer containing Ge and boron
Grows selectively at a thickness of At this time, the polycrystalline silicon film 7b also grows on the surface of the polycrystalline silicon film 7a exposed in the opening 9. At this time, the thickness of the base layer 11 is
It is set so as to be in contact with at least the polycrystalline silicon film 7b grown on the surface of the polycrystalline silicon film 7a exposed at the eaves portion 10.

Next, as shown in a step E of FIG. 3 (step E in which the portion of the base layer 11 is shown in an enlarged manner), an oxide film 4c having a thickness of 0.1 μm is formed by the CVD method, 5
A 0 nm nitride film 8b is formed and etched back by anisotropic etching to expose the oxide film 4c, and a sidewall is formed in the opening 9. Subsequently, the oxide film 4c exposed by the isotropic etching is selectively etched to expose the base layer 11.

Next, as shown in a step F of FIG. 3 (step F in which the portion of the base layer 11 is enlarged and shown), a polycrystalline silicon film 7c containing phosphorus is grown to a thickness of 0.2 μm.
By applying heat treatment, phosphorus is diffused into the base layer 11 to form the emitter region 12. After that, the polycrystalline silicon film 7c is patterned as an emitter electrode to manufacture a semiconductor device shown in a step F of FIG.

[0011]

By the way, in the above-mentioned conventional method for manufacturing a semiconductor device, a CVD oxide film for forming a sidewall on the surface of the emitter-base junction (the oxidation process in the steps E and F in FIG. Since the film 4c) is in contact, there are many surface states, and there is a problem that "leakage current increases" between the emitter and the base.

Also, a Si epitaxial layer containing Ge
The (base layer 11) is subjected to a heat treatment at a high temperature for a long time due to a strain due to lattice constant mismatch with Si, and crystal defects are generated.
There is a problem that the leakage current increases at the emitter junction. In addition, when the ratio of Ge is increased and the film thickness is increased as the base layer 11, the temperature at which crystal defects occur is reduced.
Time decreases. For example, it contains Ge at a rate of 10%,
In the case of a Si-Ge mixed crystal region having a thickness of 50 nm,
There is a problem that a crystal defect is generated by the heat treatment for one minute, and a leak current between the base and the collector is increased.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can solve all of the above problems. More specifically, in a high speed bipolar transistor, a high reliability with a small leak current is provided. It is an object of the present invention to provide a method of manufacturing a semiconductor device having the following.

[0014]

In a method of manufacturing a semiconductor device according to the present invention, in particular, a surface of an epitaxial layer containing Ge constituting a base layer is oxidized to form a silicon oxide film (thermal oxide film). RTP (rapid thermal pro using lamp heating) is used as the oxidation means.
cess), thereby oxidizing at a low temperature (930 ° C. or lower), thereby achieving the above object.

That is, the method for manufacturing a semiconductor device according to the present invention comprises the steps of: (1) forming a reverse conductivity type first epitaxial layer after forming a reverse conductivity type buried collector electrode on a one conductivity type silicon substrate; (2) a step of providing a second insulating film on the first epitaxial layer; and (3) providing a first conductive film on the second insulating film and patterning it as a base lead electrode; (4) a step of selectively etching so as to remain on the base formation region; (4) a step of providing a third insulating film at least on the first conductive film; and (5) a step of forming at least the second insulating film. (6) etching the second insulating film exposed in the opening, exposing the first epitaxial layer, and further etching to form an eaves portion; and it was exposed (7) Come to the first epitaxial layer, at least
In some areas, it is one conductivity type impurity and more than 10%
Second epitaxy including Si-Ge mixed crystal region including Ge
At the same time as forming the axial layer,
At least on the surface of the first conductive film exposed at
In some regions, one conductivity type impurity and Ge at a rate of 10% or more are used.
Providing a polycrystalline layer including a Si-Ge mixed crystal region containing
The first conductive film and the second epitaxial layer
A step which is connected via the polycrystalline layer, (8) oxidizing the second epitaxial layer surface, forming a silicon oxide film, after forming on the entire surface (9) fourth insulating film, (10) exposing the second epitaxial layer at the bottom of the opening; (11) applying a reverse conductivity to the exposed second epitaxial layer at the bottom of the opening. And a step of forming an emitter region by introducing a type impurity (a matter specifying the invention).

Further, in the method of manufacturing a semiconductor device according to the present invention, in the step (8), the surface of the second epitaxial layer is formed by using a RTP (rapid thermal pro
oxidizing at a temperature of 930 ° C. or lower (→ claim 2).

According to the method of manufacturing a semiconductor device according to the present invention, the surface of the second epitaxial layer forming the base region is oxidized (at 930 ° C.), particularly in the step (8).
The following low-temperature oxidation causes a thermal oxide film (silicon oxide film) to be formed at a low temperature on the surface of the base-emitter junction, resulting from lattice mismatch between the Si-Ge mixed crystal region and Si. Without the occurrence of “crystal defects due to distortion”, the silicon interface with the oxide film can be stabilized and the interface state can be reduced. Thus, according to the present invention,
There is an effect that the leakage current between the emitter and the base can be reduced.

Further, in the step (8) [the step of forming a thermal oxide film (silicon oxide film)], the use of RTP can reduce the total heat treatment time in the oxidation step including the entry and exit furnace time. As a result, there is an operational effect that the heat treatment margin can be increased with respect to the occurrence of crystal defects due to strain due to lattice mismatch.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to FIG. FIG. 1 is a diagram illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention, and is a cross-sectional view of a manufacturing process including steps A to C.

(First Embodiment) In the manufacturing method according to the first embodiment, first, after forming the base layer 11 through the same steps as those of the above-mentioned conventional manufacturing method, the process shown in FIG. A to Step C and Step D of FIG. 3 following Step C), and as shown in Step A of FIG. 1, an oxide film 4d is formed. As a method for forming the oxide film 4d, heat treatment is performed in an oxygen atmosphere by a lamp annealing apparatus.

The thickness of the oxide film 4d may be "about several nm" in order to stabilize the interface with the base layer 11. Specifically, the temperature is set to "850 ° C.""Hydrogen 1: oxygen 1: nitrogen 20" and an oxidation time of "15 minutes" are used to form a 5-nm oxide film 4d. At this time, it is also necessary to pay attention to the thermal stress applied when the furnace enters and leaves the oxidation furnace. Since the time required for the entrance and exit furnace is usually about 40 to 60 minutes, the temperature at that time is set to “about 750 ° C.” to reduce the thermal stress during the entrance and exit. In addition, when the surface of the base layer 11 is oxidized, the impurity profile in the base layer 11 changes. In particular, when boron is used as the impurity, boron is taken into the oxide film 4d and the concentration decreases. There is a problem. Therefore, the thickness of oxide film 4d needs to be 10 nm or less.

Next, as shown in step B of FIG. 1, an oxide film 4c having a thickness of about 0.1 μm is formed by a CVD method, and a nitride film 8b having a thickness of about 50 nm is formed. Then, the oxide film 4c is exposed to form a sidewall on the side wall of the opening 9. Next, the exposed oxide films 4c and 4d are selectively etched by isotropic etching to expose the base layer 11. The thickness of the oxide film 4c needs to be selected so that the base layer 11 is not exposed by overetching at the time of etching back the nitride film 8b.

Next, as shown in step C of FIG. 1, a polycrystalline silicon film 7c containing an n-type impurity is grown to a thickness of about 0.2 μm, and a heat treatment is applied to the base layer 11 to deposit the n-type impurity. It diffuses to form the emitter region 12. (Note that n
Phosphorus, arsenic, and antimony can be used as the type impurities. Subsequently, the polycrystalline silicon film 7c is patterned as an emitter electrode to manufacture the semiconductor device shown in the step C of FIG.

According to the manufacturing method of the first embodiment, the leakage current between the emitter and the base can be reduced, and a highly reliable bipolar transistor can be realized. The reason is that a thermal oxide film (see oxide film 4d in step C in FIG. 1) is formed on the surface of the base-emitter junction, so that the CV
This is because the silicon interface with the oxide film is stabilized and the interface state is reduced as compared with the oxide film formed by the method D.

(Second Embodiment) A second embodiment of the present invention is a method using an RTP (rapid thermal process) in the step of forming the oxide film 4d of the first embodiment. In the RTP by lamp heating, the temperature of the inlet / outlet furnace is set to about 200 ° C., and the temperature after the inlet is raised to 100 ° C./sec.
By setting the temperature to about 150 ° C., the inlet and outlet furnace time can be reduced to about 2 to 5 minutes, and the total thermal stress in the oxidation step can be greatly reduced. Specifically, a 3-nm oxide film can be formed by dry oxidation at 930 ° C. for 5 minutes.

In the second embodiment, the total thermal stress including the time of the furnace entering and exiting the oxidizing apparatus can be reduced. Therefore, the selection range of the Ge concentration and the film thickness of the base layer is expanded, and the process design is improved. Degree of freedom can be expanded.

[0027]

As described in detail above, the present invention is characterized in that the surface of the Ge-containing epitaxial layer constituting the base layer is oxidized to form a silicon oxide film (thermal oxide film). This has the effect of reducing the leakage current between the emitter and the base and realizing a highly reliable semiconductor device (bipolar transistor). The reason is that a thermal oxide film is formed on the surface of the base-emitter junction, so that the silicon interface with the oxide film is more stable and the interface state is reduced as compared with the oxide film formed by the CVD method. It is.

Also, the present invention provides a method for oxidizing the surface of the above-mentioned epitaxial layer by using RTP using lamp heating.
(rapid thermal process), low temperature (below 930 ℃)
Oxidation at the base layer, whereby G of the base layer is
There is an effect that the selection range of the e-concentration and the film thickness is expanded, and the degree of freedom of the process design can be increased. The reason is that the silicon oxide film on the base-emitter junction surface
This is because the use of RTP for forming the (thermal oxide film) makes it possible to reduce the total heat treatment time in the oxidation step, including the time for entering and exiting the furnace.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention, and is a cross-sectional view illustrating a manufacturing process including processes A to C;

FIG. 2 is a view for explaining a conventional manufacturing method, and shows a process A;
FIG. 10 is a sectional view in order of a manufacturing process including Steps C to C.

3 is a cross-sectional view in the order of the manufacturing process, which includes a process D to a process F following the process C in FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 N-type buried layer 3 N-type epitaxial layer 4a, 4b, 4c, 4d Oxide film 5 Element isolation groove 6 Collector extraction region 7a, 7b, 7c Polycrystalline silicon film 8a, 8b Nitride film 9 Opening Part 10 Eave part 11 Base layer 12 Emitter region

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/33-29/331 H01L 29/73-29/737

Claims (2)

(57) [Claims] 1. A step of: (1) forming a reverse-conductivity-type collector buried electrode on a one-conductivity-type silicon substrate, and then growing a reverse-conductivity-type first epitaxial layer; and (2) the first epitaxial layer. (3) providing a first conductive film on the second insulating film and patterning it as a base lead electrode, and selectively forming a second conductive film on the base forming region. (4) providing a third insulating film on at least the first conductive film; and (5) providing a base forming opening reaching at least the second insulating film. (6) a step of etching the second insulating film exposed in the opening, exposing the first epitaxial layer, and further etching to form an eaves portion; (7) a step of forming the exposed first Less on the epitaxial layer
In some areas, it is one conductivity type impurity and more than 10%
Second epitaxy including Si-Ge mixed crystal region including Ge
At the same time as forming the axial layer,
At least on the surface of the first conductive film exposed at
In some regions, one conductivity type impurity and Ge at a rate of 10% or more are used.
Providing a polycrystalline layer including a Si-Ge mixed crystal region containing
The first conductive film and the second epitaxial layer
A step which is connected via the polycrystalline layer, (8) oxidizing the second epitaxial layer surface, forming a silicon oxide film, after forming on the entire surface (9) fourth insulating film, (10) exposing the second epitaxial layer at the bottom of the opening; and (11) applying a reverse conductivity to the exposed second epitaxial layer. A method of introducing a type impurity to form an emitter region. 2. In the step (8), the surface of the second epitaxial layer is subjected to RTP (rapid tapping) using lamp heating.
The method according to claim 1, wherein oxidation is performed at a temperature of 930 ° C. or less by a hermal process.