JP3124283B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an improvement in a method of manufacturing a semiconductor device.
The present invention relates to an improved method of manufacturing a vertical self-aligned bipolar transistor effective for speeding up, and a method of manufacturing a high-speed MOS field-effect transistor using the manufacturing method. The first object of the present invention is to improve the reliability by making it possible to manufacture the semiconductor device stably without causing any problem.
A second object of the present invention is to provide a method of manufacturing an S field effect transistor. For the first object, a first insulating film, a first conductor film and a second Forming a laminated film with the insulating film of, and forming an opening in the laminated film to expose the one conductivity type semiconductor layer, and on the one conductivity type semiconductor layer exposed in the opening, Forming a second conductive film having an upper surface lower than the upper surface of the second insulating film; and forming an opening in a region where the second conductive film is not formed, that is, a second conductive film. Forming a third sidewall made of a third insulating film in a space above a region where the conductor film is formed, that is, in a side wall of the opening in a region where the second conductor film is not formed; The second conductive film is etched using the third sidewall as a mask. Forming a first side wall made of the second conductive film on the side wall of the opening, and forming the first side wall and the third side wall on which the first side wall and the third side wall are formed. Introducing an impurity of the opposite conductivity type through the opening to form an internal base region in the semiconductor layer of one conductivity type, and forming the internal base region in the semiconductor layer of the one conductivity type; On the side wall of the opening,
Forming a second sidewall made of a fifth insulating film that completely covers the first sidewall; and implanting one conductivity type impurity into the opening where the second sidewall is formed. Forming an emitter region of one conductivity type in an upper layer of the internal base region by diffusing, and an impurity of an opposite conductivity type in the one conductivity type semiconductor layer below the first sidewall. Forming an external base region in contact with the internal base region by thermally diffusing the semiconductor device. Second
Forming a source / drain in the one conductivity type semiconductor layer by diffusing impurities from the first sidewall, and exposing the one conductivity type semiconductor layer to the opening. Forming a gate insulating film thereon;
Forming a gate electrode on the gate insulating film.

[Industrial applications]

The present invention relates to an improvement in a method for manufacturing a semiconductor device. In particular, the present invention relates to an improvement in a method of manufacturing a self-aligned bipolar transistor having a vertical structure that is effective for miniaturization and speeding up, and a method of manufacturing a high-speed MOS field-effect transistor using the manufacturing method.

[Conventional technology]

A method for manufacturing a self-aligned bipolar transistor according to the related art will be described.

See FIG. 3-1 (a). For example, a first silicon dioxide film 7 is formed on the n-type silicon layer 3 separated by the field oxide film 4 by the CVD method, and then, by using the CVD method. forming a first polycrystalline silicon film 8 into which a p-type impurity has been introduced;
A second silicon dioxide film 9 is formed thereon by using a CVD method.

See FIG. 3-1 (b). The first silicon dioxide film 7, the first
An opening 10 for base formation exposing the n-type silicon layer 3 is formed in the laminate composed of the polycrystalline silicon film 8 and the second silicon dioxide film 9.

See FIG. 3-1 (c). A second polycrystalline silicon film is formed on the second silicon dioxide film 9 including the inner surface of the base forming opening 10, and anisotropically etched by RIE. Then, the second polycrystalline silicon film is selectively removed, and a first sidewall 13 made of the second polycrystalline silicon film remains on the side wall of the opening 10.

In the anisotropic etching using the RIE method, over-etching is performed so that the upper end of the first sidewall 13 is lower than the upper surface of the second silicon dioxide film 9 by about 2,000 to 4,000 degrees. Therefore, the same concave portion is formed in the n-type silicon layer 3 exposed in the opening 10.

Referring to FIG. 3-1 (d), a fifth silicon dioxide film is formed on the second silicon dioxide film 9 including the inner surface of the opening 10 by using the CVD method, and anisotropically formed by using the RIE method. The fifth silicon dioxide film is selectively removed by performing a reactive etching, and
First sidewall made of second polycrystalline silicon film
A second side wall 16 made of a fifth silicon dioxide film is formed to cover 13.

Referring to FIG. 3-2 (e), after boron ions are implanted through the opening 10, heat treatment is performed to activate the introduced boron to form the p-type internal base region 15, and at the same time, to form the p-type Solid-phase diffusion of a p-type impurity from the first polycrystalline silicon film 8 to the n-type silicon layer 3 via the first side wall 13 formed of the second polycrystalline silicon film formed on the side surface of the opening 10 The p-type external base region in contact with the p-type internal base region 15
Form 19.

Referring to FIG. 3-2 (f), n is formed on the second silicon dioxide film 9 including the inner surface of the opening 10.
Forming a third type polycrystalline silicon film, patterning the same, and forming an n-type third polycrystalline silicon electrode 17 in the opening 10;
Is formed, and a heat treatment is performed to diffuse solid-phase impurities of the n-type impurity from the n-type third polycrystalline silicon electrode 17 to form an n-type emitter region 18 on the p-type internal base region 15. ,
Although not shown hereafter, a bipolar transistor is completed by forming a base electrode, a collector electrode and the like.

Next, a method for manufacturing a MOS field-effect transistor according to the related art will be described.

Referring to FIG. 4 (a), for example, the n-type silicon layer 3 separated by the field oxide film 4 is thermally oxidized to form a gate insulating film 24 made of a silicon dioxide film. An impurity-doped polysilicon layer is formed and patterned to form a gate electrode 25.

Referring to FIG. 4 (b), p-type impurities are ion-implanted using the gate electrode 25 as a mask to form the source / drain regions 23.

See FIG. 4 (c), for example, a PSG film 27 is formed as an insulating film, and this is patterned to form a contact hole for leading an electrode.
An aluminum film is formed on the main surface by filling the inside of the contact hole, and the aluminum film is patterned to form the source / drain electrodes.

[Problems to be solved by the invention]

In the manufacturing method of the bi-bora transistor, the second
The first sidewall 13 made of the polycrystalline silicon film is formed so as to be lower than the upper surface of the second silicon dioxide film 9 by about 2,000 to 4,000 degrees.
Need to be completely covered with a second side wall 16 made of a fifth silicon dioxide film and electrically insulated, but the height of the upper end of the first side wall 13 can be precisely controlled by etching. Therefore, the shoulder portion of the sidewall 13 is exposed from the insulating film 16, and the electrical insulation between the sidewall 13 and an emitter electrode to be formed later may be incomplete. Further, since the surface of the n-type silicon layer 3 exposed in the opening 10 is also etched to form a concave portion, a defect occurs in the n-type silicon layer 3 or a gap between the inner base region 15 and the A step is formed,
In this portion, the connection between the internal base and the external base diffusion layer becomes uncertain, and as a result, there arises a problem that the electrical connection becomes incomplete.

In a conventional MOS field-effect transistor,
The large parasitic capacitance of the source / drain hinders high speed operation.

An object of the present invention is to eliminate these disadvantages and has two objects. A first object is to improve reliability by enabling a vertical self-aligned bipolar transistor to be manufactured stably without causing defects. A second object is to provide a method for manufacturing a high-speed MOS field-effect transistor using the above-described method for manufacturing a bipolar transistor.

[Means for solving the problem]

Among the above two objects, the first object is to form a first insulating film (7), a first conductor film (8), and a second insulating film (9) on the one conductivity type semiconductor layer (3). Forming an opening (10) exposing the one-conductivity-type semiconductor layer (3) in the laminated film; and forming the one-conductivity-type exposed in the opening (10). Forming a second conductor film (11) having an upper surface lower than the upper surface of the second insulating film (9) on the semiconductor layer (3); and forming the second conductor film (11). The opening formed in the space region above the region where 11) is formed, that is, the second conductor film (11)
Forming a third side wall (12) made of a third insulating film on the side wall of the opening (10) where no opening is formed, and using the third side wall (12) as a mask, Forming a first sidewall (13) made of the second conductor film on the side wall of the opening (10) by etching the second conductor film (11); An impurity of the opposite conductivity type is introduced through the opening (10) in which the wall (13) and the third side wall (12) are formed, and an internal base region is formed in the one conductivity type semiconductor layer (3). (15) forming a first side wall on the side wall of the opening (10) where the first side wall (13) and the third side wall (12) are formed; A second sidewall (5) made of a fifth insulating film completely covering the wall (13) Forming the second side wall (16) and diffusing one conductivity type impurity into the opening (10) in which the second side wall (16) is formed to form an upper layer of the internal base region (15). Forming an emitter region (18) of one conductivity type, and diffusing impurities of the opposite conductivity type into the inside of the one conductivity type semiconductor layer (3) below the first sidewall (13). Forming an external base region (19) in contact with the internal base region (15).

Among the above two objects, a second object is to form a first insulating film (7), a first conductor film (8), and a second insulating film (9) on the one conductivity type semiconductor layer (3). A first conductive film having the opposite conductivity type by forming a rectangular opening (10) exposing the one conductivity type semiconductor layer (3) in the stacked film. A step of dividing (8) into two regions, and a step of forming an upper surface on the one conductivity type semiconductor layer (3) exposed in the opening (10) from the upper surface of the second insulating film (9). Forming a second conductive film (11) containing an impurity of the opposite conductivity type at a lower position, and forming a third conductive film on the side wall of the opening (10) where the second conductive film (11) is formed; Forming a third sidewall (12) made of an insulating film, and using the third sidewall (12) as a mask to remove the second conductive film (11). Etching to form a first side wall (13) made of the second conductive film on the long side wall of the rectangular opening (10); and forming the first side wall (13) ) And said third
The opening (10) in which the side wall (12) is formed
A second sidewall (16) made of a fifth insulating film which completely covers the first sidewall (13)
Forming the first side wall (13)
Diffusing impurities from the first conductive semiconductor layer (3)
Forming a source / drain (23) on the substrate, forming a gate insulating film (24) on the one conductivity type semiconductor layer (3) exposed in the opening (10), (24) a step of forming a gate electrode (25) on the semiconductor device.

[Action]

Generally, controlling the film thickness when depositing using a CVD method or the like more accurately controls the film thickness than forming a film having a desired thickness by reducing the film thickness by performing etching. be able to.

In the method of manufacturing a semiconductor device according to the first invention of the present application, the second conductor film 11 deposited to a desired thickness by using a CVD cheek in the opening 10 is anisotropically etched to form the opening. Since the first sidewall 13 is formed on the side wall, the upper end of the first sidewall 13 is surely formed lower than the upper surface of the second insulating film 9, and the first sidewall 13 is formed of the third insulating film. Is completely covered by the third sidewall 12 made of the fifth insulating film and electrically insulated. Further, the surface of the one-conductivity-type semiconductor layer 3 exposed in the opening 10 is not etched to form a concave portion, no defect occurs, and the connection between the inner base 15 and the outer base 19 is incomplete. This eliminates the problem of becoming

In the method for manufacturing a semiconductor device according to the second invention of the present application, by using the method for manufacturing a semiconductor device according to the first invention of the present application, the area of the source / drain is reduced, and the parasitic capacitance is reduced. As a result, the speed of the MOS field effect transistor can be increased.

〔Example〕

Hereinafter, two embodiments of the method of manufacturing a semiconductor device according to the present invention will be described.

First Example A method for manufacturing a bipolar transistor will be described.

Referring to FIG. 1-1 (a), an n ⁺ -type buried layer 2 is formed on a p-type silicon substrate 1 using a well-known method, and then an n-type silicon layer 3 is epitaxially grown. To form a field oxide film 4 having a thickness of about 6,000 mm. A collector contact region 5 is formed by diffusing an n-type impurity into the collector contact region formation region, and a vertical groove having a depth of about 5 μm is formed by anisotropic etching in the isolation formation region. Is embedded to form an isolation region 6.

Refer to FIG. 1-1 (b). The first silicon dioxide film 7 is
形成 Form thick. Instead of the first silicon dioxide film 7, a silicon nitride film used as a mask when forming the field oxide film 4 by using the LOCOS method may be used as it is. Next, p with impurity boron introduced
A first polycrystalline silicon film 8 having a mold is formed to a thickness of about 3,000 mm. Note that, instead of the first polycrystalline silicon film, a silicide film such as a tungsten silicide film or a titanium silicide film, or a polycide film including a stacked film of a polycrystalline silicon film and a silicide film may be formed. The first polycrystalline silicon film 8 is selectively removed by etching, and is left in the base formation region and the base lead region formation region, and the second silicon dioxide film 9 is coated on the entire surface by about 3,000.
形成 Form thick.

As shown in FIG. 1-1 (c), an n-type silicon layer 3 is pierced through a laminated film including a first silicon dioxide film 7, a first polycrystalline silicon film 8 and a second silicon dioxide film 9. The opening 10 for base formation which exposes is formed.

Referring to FIG. 1-2 (d), a second polycrystalline silicon film 11 is formed inside the opening 10 by using a selective CVD method. At this time, the second polycrystalline silicon film
The upper surface of 11 is 3,000 from the upper surface of the second silicon dioxide film 9
Formed to be ~ 4,000Å lower. This 3,000-4,000
The dimension of Å is set so that the third sidewall 12 formed in the next step is favorably formed, and the third sidewall 12 is formed even after the etching step for forming the first sidewall 13. Is determined to remain sufficiently. Note that, instead of the second polycrystalline silicon film 11, an amorphous silicon film or a silicide film may be formed.

Referring to FIG. 1-2 (e), the third surface is formed on the main surface including the inner surface of the opening 10 by using the CVD method.
Is formed to a thickness of 500 to 2,000 mm, anisotropic etching is performed to selectively remove the third silicon dioxide film, and an opening is formed in a region where the second polycrystalline silicon film 11 is not buried. A third side wall 12 made of a third silicon dioxide film is formed on the side wall of 10.

With reference to FIG. 1-2 (f), using the third side wall 12 as a mask, the second polycrystalline silicon film 11 is selectively etched away to form a first side wall 13 made of the second polycrystalline silicon film. To form

Next, an internal base region is formed using a conventional method. For example, a fourth silicon dioxide film 1 having a thickness of about 200 ° is formed on the surface of the n-type silicon layer 3 exposed to the opening 10 by thermal oxidation.
Form 4 and implant boron ions at an energy of 10 KeV,
Ion implantation is performed at a dose of 3 × 10 ¹³ cm ⁻² to form the internal base region 15.

See FIG. 1-3 (g). On the main surface including the inner surface of the opening 10, a fifth
Is formed to a thickness of about 3,000.ANG., And the fifth silicon dioxide film is selectively removed by anisotropic etching to form a second side wall 16 made of the fifth silicon dioxide film. . As a result, the first side wall 13 made of the second polycrystalline silicon film is completely covered by the third side wall 12 and the second side wall 16 and is electrically insulated.

Referring to FIG. 1-3 (h), a third surface is formed on the main surface including the inner surface of the opening 10 by using the CVD method.
A polycrystalline silicon film of 1,000 to 2,000 mm thick, with arsenic ion implantation energy of 60 KeV and dose of 1.5 × 10 ¹⁶
After ion implantation at cm ⁻² , etching is performed to form an n-type third polycrystalline silicon electrode 17 inside the opening 10. By performing a heat treatment, impurity arsenic is diffused from the third polycrystalline silicon electrode 17 to the upper layer of the internal base region 15 by solid-phase diffusion to form an emitter region 18. At the same time, impurity boron is solid-phase-solid diffused from the first polycrystalline silicon film 8 to the n-type silicon layer 3 via the first sidewall 13 to form an external base region 19 in contact with the internal base region 15. .

As a method for forming the external base region 19, in addition to the above-described method of introducing impurities contained in the first conductor film 8 into the semiconductor layer 3 through the first sidewall 13, the following method is used. Can be formed by using the method shown in FIG.

(A) The first conductor film 8 contains no impurities,
The impurity contained in the first sidewall 13 is thermally diffused into the semiconductor layer 3 to form the external base region 19.

(B) The impurities introduced in the ion implantation step for forming the internal base shown in FIG. 1-2 (f) are diffused not only in the depth direction by the subsequent heat treatment but also in the lateral direction, and An external base region 19 in contact with the internal base region 15 is formed below the sidewall 13 of FIG.

(C) In the step of forming the opening 10 shown in FIG. 1-1 (c), impurities are introduced into the semiconductor layer 3 to form the internal base region 15.
And the external base region 19 are formed simultaneously.

Referring to FIG. 1-3 (i), the insulating films 9 and 7 on the collector and the base are etched to form openings using a well-known method, and then the emitter electrode 20 made of aluminum and the base electrode are formed.
The bipolar transistor is completed by forming 21 and the collector electrode 22.

Second Example A method for manufacturing a MOS field-effect transistor will be described.

Referring to FIG. 2A, a field oxide film 4 for element isolation is formed on the n-type silicon layer 3 by using a well-known method, and then a first silicon dioxide film 7 is formed by using a CVD method. Approximately 2,000 mm thick. Next, a first polycrystalline silicon film 8 into which impurity boron is introduced is formed to a thickness of about 3,000 mm by using the CVD method, and is patterned and remains in the element formation region. The film 9 is formed to a thickness of about 3,000 mm.

Next, the n-type silicon layer 3 is exposed in the central region of the laminated film including the first silicon dioxide film 7, the first polycrystalline silicon film 8, and the second silicon dioxide film 9 through these. A rectangular opening 10 is formed. At this time, both ends in the longitudinal direction of the rectangular opening 10 are formed so as to reach over the field oxide film 4, and the first polycrystalline silicon film 8 is divided into two regions.

See FIG. 2 (b). Using the same method as in the first example, a second
First sidewall 13 made of a polycrystalline silicon film and third sidewall made of a third silicon dioxide film
12 and a second sidewall 16 made of a fifth silicon dioxide film are formed. Since both ends of the opening 10 in the longitudinal direction are on the field oxide film, the second polycrystalline silicon film does not grow in this region, so that the first side wall 13 made of the second polycrystalline silicon film is not formed. Is a rectangular opening
It is formed only on the side of the long side of 10.

By performing a heat treatment, impurity boron is diffused from the first polycrystalline silicon film 8 to the n-type silicon layer 3 through the first sidewall 13 by solid-phase diffusion to form a p-type source / drain 23.

See FIG. 2 (c). N-type silicon layer 3 exposed in opening 10 by thermal oxidation
A gate insulating film 24 made of a silicon dioxide film is formed thereon. Thereafter, the gate electrode 25 and the insulating film 9 are etched by using a well-known method to form a source / drain contact opening and a source / drain electrode 26, thereby forming a MOS The field effect transistor is completed.

〔The invention's effect〕

As described above, in the method of manufacturing a semiconductor device according to the present invention, the first sidewall made of the second conductive film formed for the purpose of forming the external base region and the formation of the base extension region includes: Since the upper end is formed to be surely lower than the upper surface of the second insulating film, the third side wall made of the third insulating film and the fifth
Is completely electrically insulated by the second side wall made of the insulating film. In addition, since the surface of the one conductivity type semiconductor layer is not etched to form a concave portion,
Generation of defects due to etching and poor connection between the internal base region and the external base region are also eliminated, and a high-quality bipolar transistor is stably manufactured and reliability is improved.
Further, by utilizing the method for manufacturing a bipolar transistor, the parasitic capacitance of the source / drain can be reduced, so that a high-speed MOS field-effect transistor can be manufactured.

[Brief description of the drawings]

FIG. 1-1, FIG. 1-2, and FIG. 1-3 are manufacturing process diagrams of a bipolar transistor according to one embodiment of the present invention. FIG. 2 is a manufacturing process diagram of a MOS field-effect transistor according to one embodiment of the present invention. FIG. 3-1 and FIG. 3-2 are manufacturing process diagrams of a bipolar transistor according to the prior art. FIG. 4 is a manufacturing process diagram of a MOS field-effect transistor according to the prior art. 1 ... p-type silicon substrate, 2 ... n ⁺ type buried layer, 3 ... one conductivity type semiconductor layer (n-type silicon layer), 4 ... field oxide film, 5 ... collector contact region, 8 ... opposite A conductive type first conductive film (p-type first polycrystalline silicon film), 10 an opening, 11 an opposite conductive type second conductive film (p-type second polycrystalline silicon film), 12 ... Third sidewall 13... First sidewall 15... Internal base region 16... Second sidewall 17. 18 ... emitter region, 19 ... external base region, 23 ... source / drain, 24 ... gate insulating film, 25 ... gate electrode.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 21/336 H01L 29/73 H01L 29/78

Claims (2)

(57) [Claims] 1. A step of forming a laminated film of a first insulating film (7), a first conductor film (8), and a second insulating film (9) on a semiconductor layer of one conductivity type (3). Forming an opening (10) in the laminated film for exposing the one conductivity type semiconductor layer (3); and exposing the one conductivity type semiconductor layer (3) in the opening (10).
Forming a second conductive film (11) having an upper surface lower than the upper surface of the second insulating film (9); and forming the second conductive film (11) thereon. Forming a third sidewall (12) made of a third insulating film on a side wall of the opening (10) in a region where there is no second insulating film, and using the third sidewall (12) as a mask to form the second sidewall (12).
Forming a first sidewall (13) made of the second conductor film on the side wall of the opening (10) by etching the conductive film (11); ) And an impurity of the opposite conductivity type is introduced through the opening (10) in which the third side wall (12) is formed to form an internal base region (15) in the one conductivity type semiconductor layer (3). Steps: on the side wall of the opening (10) where the first side wall (13) and the third side wall (12) are formed,
Forming a second sidewall (16) made of a fifth insulating film completely covering the first sidewall (13); and forming the second sidewall (16) in the opening ( Forming a one conductivity type emitter region (18) in an upper layer of the internal base region (15) by diffusing one conductivity type impurity into the inside of the first sidewall (13); Forming an external base region (19) in contact with the internal base region (15) by thermally diffusing an impurity of the opposite conductivity type inside the one conductivity type semiconductor layer (3). A method for manufacturing a semiconductor device. 2. A step of forming a laminated film of a first insulating film (7), a first conductor film (8), and a second insulating film (9) on the one conductivity type semiconductor layer (3). Forming a rectangular opening (10) exposing the one-conductivity-type semiconductor layer (3) in the laminated film;
Dividing the conductive film (8) into two regions; and the one conductivity type semiconductor layer (3) exposed in the opening (10).
A second conductor film (11) including an opposite conductivity type impurity, the upper surface of which is lower than the upper surface of the second insulating film (9);
Forming a third sidewall (1) made of a third insulating film on the side wall of the opening (10) where the second conductive film (11) is formed.
Forming the second sidewall, and using the third sidewall (12) as a mask.
The first conductive film (11) is formed by etching the conductive film (11) on the long side wall of the rectangular opening (10).
Forming a side wall (13), and a side wall of the opening (10) in which the first side wall (13) and the third side wall (12) are formed.
Forming a second sidewall (16) made of a fifth insulating film that completely covers the first sidewall (13); and diffusing impurities from the first sidewall (13); Forming a source / drain (23) in the one conductivity type semiconductor layer (3); and exposing the one conductivity type semiconductor layer (3) to the opening (10).
A method for manufacturing a semiconductor device, comprising: a step of forming a gate insulating film (24) thereon; and a step of forming a gate electrode (25) on the gate insulating film (24).