JP3124339B2 - Reset circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit,
In particular, the present invention is suitable for use in a serial printer in which the time from when the CPU reset signal is released to when the drive circuit control signal is output can be arbitrarily set.

[0002]

2. Description of the Related Art As is well known, a recent serial printer is provided with a central processing unit (hereinafter referred to as a CPU), and the CPU controls the operation of the entire printer. FIG. 5 is a block diagram showing an example of a conventional serial printer. In FIG. 5, 1 is CP
U and 2 are bus lines for transmitting and receiving data between the CPU 1 and peripheral elements, and 3 is a read only memory (hereinafter referred to as ROM).
A program and data for controlling the operation of U1 are stored.

[0003] Next, reference numeral 4 denotes a random access memory, which is used for storing received data and for a work area of the CPU 1. Reference numeral 5 denotes a gate array for reducing the load on the CPU 1 and controlling the space motor 8, the paper feed motor 9, the print head 10, and the like. Reference numeral 6 denotes an interface driver for performing communication with a host computer (not shown), reference numeral 7 denotes a drive circuit unit for driving the space motor 8, paper feed motor 9, print head 10, and the like. Reference numeral 11 denotes a CPU reset. Signal S
_RES, and a generation circuit for generating a voltage of + 5V _D.

Next, the operation of the reset circuit in the serial printer configured as described above will be described with reference to the circuit diagram of FIG. In FIG. 6, when the power is turned on, the power supply voltage V _CC1 gradually rises. The power supply voltage V
_CC1 is divided by resistors R1 and R2, is applied to the inverting input terminal of the first comparator CMP1 as the reference voltage V _REF. On the other hand, the comparator CMP1
The non-inverting input terminal of the detection voltage V _in is applied. The detection voltage V _in are those obtained by dividing the power supply voltage V _CC1 and Zener diode ZD1 and the resistor R3, resistor R4, R5, capacitor C1, diode D
1 and the like. A part of the output of the comparator CMP1 is returned to the non-inverting input terminal through the resistor R6.

The output terminal of the first comparator CMP1 is connected to a + 5V power supply through a resistor R7. As shown in FIG. 7A, a predetermined time elapses after the power supply is turned on. the detection voltage V at time t ₁
If _in is greater than the reference voltage V _REF, the output above the comparator CMP1 is turned on is as shown in (b) of FIG. 7, the "H" level at time t _2. The output of the first comparator CMP1 is
It is provided to the inverting input terminal of MP2. A voltage obtained by dividing the voltage of +5 V by the resistors R8 and R9 is applied to the non-inverting input terminal of the second comparator CMP2, and when the output of the first comparator CMP1 becomes "H" level. , The second comparator CMP2 turns on,
The output goes to "L" level.

The output of the second comparator CMP2 is +5
This is supplied to the _VD generation circuit 16. The + 5V _D generation circuit 16 includes a PNP transistor TR1, resistors R10, R
11, R12, etc., and the output of the second comparator CMP2 is a PNP transistor TR1
Given to the base. Therefore, when the second comparator CMP2 is turned on and its output goes to "L" level, the base potential of the PNP transistor TR1 goes to "L" level. Accordingly, since the base current is drawn, as shown in FIG. 7 (c), the PNP transistor TR1 is turned on at time t _3, the voltage from the collector + 5V _D is output. In the reset circuit thus configured, the first comparator CM
P1 output is used as the CPU reset signal S _RES, an output of the second comparator CMP2 is used in the drive circuit section 7.

[0007]

In the case of the reset circuit having the structure described above, the signal S for resetting the CPU is used.
_The time for outputting _RES can be arbitrarily selected by setting a circuit constant of an element externally connected to the first comparator CMP1. However, the time until the drive circuit control signal S _C of + 5V _D from the CPU reset signal S _RES is released is output had been determined by the delay time of the circuit elements. Therefore, conventionally, there has been a problem that the timing until the operation of the drive circuit 7 is started cannot be controlled with high accuracy.

[0008] As shown in FIG. 6, conventionally, a first comparator CMP1 and a second comparator CMP1 are used.
As described in 2, the use of two comparators complicates the overall circuit configuration and increases costs. The present invention has been made in view of the above problems,
The time from when the CPU reset signal is released to when the CPU starts operating until the drive circuit control signal is output can be arbitrarily set, and the circuit configuration can be simplified. With the goal.

[0009]

SUMMARY OF THE INVENTION A reset circuit according to the present invention releases a reset of a CPU a predetermined time after power-on, and a short time after the reset of the CPU is released. A reset circuit for outputting a signal for controlling the operation of the CPU, a timer means configured by a program of the CPU 1 and setting a time required until the operation is stabilized after the reset is released and the CPU is started to operate. Operates in response to a timeout signal output from the timer means,
Driving means for turning on the drive circuit control signal generation circuit by inverting the potential of the port of the CPU to which the circuit for generating the drive circuit control signal is connected.

[0010]

A timer circuit is provided inside the CPU, and the timer circuit manages the time until the CPU can stably operate, so that the drive circuit is released after the reset of the CPU is released. The time until the control signal is output can be set arbitrarily and accurately.

[0011]

FIG. 1 is a configuration diagram of a reset circuit showing one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a CPU, 2 denotes a bus line for transmitting / receiving data between the CPU 1 and peripheral elements, and 3 denotes a read-only memory (hereinafter referred to as a ROM).
The ROM 3 stores programs and data for controlling the operation of the CPU 1.

Next, reference numeral 4 denotes a random access memory which stores data received from the interface and
Used for the work area of PU1. 5 is CPU
1 is a gate array for controlling the space motor 8, the paper feed motor 9, the print head 10, and the like, while reducing the load of No. Reference numeral 6 denotes an interface driver for communicating with a host computer (not shown). Reference numeral 7 denotes a drive circuit for driving the space motor 8, the paper feed motor 9, the print head 10, and the like.
_{Reference numeral} 2 denotes a CPU reset circuit that generates a CPU reset signal _SRES .

FIG. 2 is a circuit diagram showing a specific circuit configuration of the reset circuit of this embodiment. In FIG. 2, when the power is turned on, the power supply voltage V _CC1 gradually rises. The power supply voltage V _CC1 is connected to the resistors R1 and R
2 and is supplied to the inverting input terminal of the first comparator CMP1 as the reference voltage V _REF . on the other hand,
The non-inverting input terminal of the comparator CMP1, the voltage V _in for detecting the power supply voltage is applied. The power supply voltage detection voltage V _in the power supply voltage has been generated by dividing by V _CC1 to the Zener diode ZD1 and the resistor R3, resistor R4, R5, capacitor C1, comprising a diode D1 such as an input circuit 15 to the non-inverting input terminal. A part of the output CMPO of the comparator CMP1 is returned to the non-inverting input terminal through the resistor R6.

[0014] As shown in (a) of the timing chart of FIG. 3, at the time t ₁ has elapsed a predetermined time from turning on the power, the detection voltage V _in is greater than the reference voltage V _REF . Then, as described above, the comparator C
MP1 is turned on and its output CMPO is shown in FIG.
The "H" level at time t ₁ as shown in FIG. The comparator output CMPO is the CPU reset signal S _RES
To the reset signal input terminal R of the CPU 1.

When the CPU 1 receives the CPU reset signal S _RES , it activates the timer means 13, and at a time t ₂ when a predetermined time has elapsed, the time-out signal S _OUT is derived from the timer means 13 to the driving means 14. As a result, the driving means 14 operates, and "0" is set to the port A by the operation of the driving means 14. A circuit 16 for generating a control signal of + 5V _D is connected to the port A. The + 5V _D generation circuit 16 includes a PNP transistor TR1, resistors R10, R11, R12 and the like, and the potential of the port A is applied to the base of the PNP transistor TR1. Therefore, port A
Is set to "0", the PNP transistor TR1
The transistor TR1 is turned on when the base potential of the transistor TR1 becomes "L" level and the base current is drawn. Thus, as shown in (d) of FIG. 3, the PNP transistor TR1 is turned on at time t _3, the voltage from the collector + 5V _D is output.

Next, referring to the flowchart of FIG.
The operation of U1 will be described. When the CPU 1 starts operating, execution of the program is started from address 0 in step P1. Usually, a processing program called initial processing is written at address 0 of the program, and this program is executed first. Note that the initial process performed here is a process of setting an initial value to a register, a timer, a port, and the like inside the CPU 1.

Next, at step P2, the CPU 1
The stabilization time T _{D with} respect to the timer means 13 provided in
Is set. The stabilization time T _D is a delay time from when the reset of the CPU 1 is released to when the transistor TR1 of the + 5V _D generation circuit 16 is turned on.
Reference numeral 1 denotes a time required until a stable operation can be performed. This stabilization time T _D is stored in the program ROM 3 in advance. Upon completion of such a process, the process proceeds to step P3, where the timer unit 13 is started. Then, the process proceeds to step P4 to monitor whether or not the count value set in the timer overflows.

If the count value has not overflown, the process waits in step P4 until the count value overflows. If the count value overflows, the process proceeds to step P5. In Step P5, as described above, the CPU 1
The driving means 14 provided in the
“0” is an initial value of the port A to which R1 is connected.
Is set. Note that the timer means 13 and the driving means 1
4 and the like are configured by a program of the CPU 1. When "0" is set to the port A, the transistor TR1 is turned on, and +5 V is applied from the collector of the transistor TR1.
_D voltage is output.

[0019]

According to the present invention, as described above, the timer means is provided inside the CPU,
The time from the start of operation to the output of the drive circuit control signal is set in the timer means to manage the time, and the drive circuit provided inside the CPU generates the drive circuit control signal. Since the operation is controlled, the time from when the reset of the CPU is released to when the drive circuit control signal is output is arbitrarily set.
In addition to being able to set accurately, the circuit configuration can be simplified, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reset circuit showing one embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a specific configuration example of a reset circuit according to an embodiment.

FIG. 3 is a waveform chart showing the operation of each part of the reset circuit of the embodiment.

FIG. 4 is a flowchart illustrating an operation of a CPU.

FIG. 5 is a block diagram showing a conventional reset circuit.

FIG. 6 is a circuit diagram showing a conventional reset circuit.

FIG. 7 is a waveform chart showing the operation of the conventional circuit.

[EXPLANATION OF SYMBOLS] 1 CPU 2 bus line 3 ROM 4 RAM 5 gate array 6 interface driver 7 driving circuit 12 CPU reset circuit section 13 timer means 14 driving means T _D stabilization time S _C drive circuit control signal V _in detection voltage V _REF reference voltage S _RES CPU reset signal S _OUT timeout signal

Claims (1)

(57) [Claims] 1. After a predetermined time from power-on, the CP
A reset circuit which releases a reset of U and outputs a signal for controlling the drive circuit with a short time after the reset of the CPU is released. The reset circuit is configured by the program of the CPU 1 and the reset is released. Timer means for setting a time required until the operation is stabilized after the CPU starts operation, and a circuit which operates in response to a timeout signal output from the timer means and generates the drive circuit control signal A drive circuit for turning on the drive circuit control signal generation circuit by inverting the potential of the port of the CPU connected to the drive circuit.