JP3124445B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art A thin film transistor (generally called a TFT) using a thin film semiconductor formed on a substrate having an insulating surface such as a glass substrate is known. This thin film transistor is used for various integrated circuits. In particular, an example is known in which each pixel portion of an active matrix type liquid crystal display device is disposed and used for switching pixels.

As a type of the thin film semiconductor, an amorphous silicon film and a crystalline silicon film are known. The amorphous silicon film has a feature of being excellent in productivity due to ease of film formation, but has a problem that its electric characteristics are low and characteristics of a thin film transistor obtained are low. On the other hand, the crystalline silicon film has a feature that a thin film transistor having high characteristics can be obtained. However, at present, a single crystal silicon film cannot be obtained, so that the obtained film has a polycrystalline structure or a microcrystalline structure (these are collectively referred to as a crystalline silicon film).

FIG. 2A shows an example of a typical thin film transistor. FIG. 2 shows that an N-type source region 2 is formed on a surface of a glass substrate 201 on which a silicon oxide film 202 is formed.
03, substantially genuine (I-type) channel forming region 20
4, an active layer composed of an N-type drain region 205, a gate insulating film 206, a gate electrode 207, an interlayer insulating film 208, a source electrode 209, and a drain electrode 21.
It has 0.

In a thin film transistor using such a crystalline silicon film, the presence of an OFF current (also referred to as a leakage current) poses a serious problem. The OFF current refers to, for example, when a negative potential is applied to the gate electrode 207 when an N-channel thin film transistor as shown in FIG.
And a phenomenon in which current flows between them. When the N-channel type thin film transistor is off, the gate electrode 20
When a negative potential is applied to 7, the portion of the channel formation region 204 that is in contact with the gate insulating film 206 becomes P-type. Therefore, if the thin film semiconductor forming the active layer (where the source / drain region and the channel formation region are formed) is a single crystal, a PN junction is formed between the source / drain and the source / drain No large current flows between them. However, when the thin film semiconductor forming the active layer has a polycrystalline structure or a microcrystalline structure, a high electric field formed between the source or drain region and the channel formation region causes carriers to pass through the crystal grain boundaries. Movement occurs. As a result, the OFF current becomes relatively large.

As a method of reducing the OFF current, a technique employing an LDD structure or an offset gate structure is known. These structures prevent an electric field from being concentrated at the interface between the source or drain region and the channel formation region and in the vicinity thereof, thereby reducing the OFF current.

[Process leading to the invention] According to the study of the present inventors, the LDD structure and the offset gate structure are of the OFD type.
It has been found that while effective in reducing F-current, it does not provide significant improvement in nature. Therefore, various parameters were changed, and the dependence of the OFF current on the various parameters was examined. As a result, it was found that the OFF current hardly changed even when the width of the active layer was changed. FIG. 2B shows a schematic shape of the active layer. FIG.
In (B), 21 is a source region, 22 is a channel formation region, and 23 is a drain region. W is the width of the active layer, and L is the length of the active layer.

First, when the width W of the active layer is changed, OF
No significant change was observed in the value of the F current. If O
If carriers causing the FF current are moved over the entire cross section of the active layer, a change in the value of the OFF current should be seen by changing the width W of the active layer. This is because a change in the width W of the active layer changes the area of the passage of the carrier (cross-sectional area of the active layer) that causes the OFF current.

On the other hand, when the thickness of the active layer was changed, a remarkable change was observed in the value of the OFF current depending on the change. That is, by reducing the thickness of the active layer, O
It was confirmed that the FF current decreased.

The above experimental fact is based on the fact that the movement of carriers causing the OFF current is mainly performed on the side surface 24 of the active layer. As described above, when the movement of the carrier that causes the OFF current is mainly performed on the side surface 24 of the active layer, even if the width of the active layer is changed, the OFF current is hardly related to the movement of the carrier. Hardly changes. On the other hand, when the thickness of the active layer is reduced, the path of carriers is narrowed, and the OFF current is reduced.

The carriers move through the side surface of the active layer because a large number of traps are concentrated on the side surface of the junction between the channel formation region and the source region or the drain region. I do. The traps are concentrated on the side surface of the active layer for the following reasons. Generally, a method by dry etching such as RIE is used to form an active layer. In this case, the plasma damage becomes remarkable at the peripheral edge and the peripheral side surface of the active layer. Then, defects are intensively formed on the side surfaces of the etched active layer. That is, traps are concentrated on the side surface of the active layer.

In order to eliminate or reduce the trap existing on the side surface of the active layer, defects on the side surface of the active layer are reduced after a patterning step (patterning by dry etching) for forming the active layer, and the trap density is reduced. Need to be reduced. That is, it is necessary to perform some kind of annealing on the side surface of the active layer. The invention described in this specification has been achieved through the above-described processes.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor having a small OFF current.

[0014]

One of the inventions disclosed in this specification is characterized in that the crystallinity at the peripheral edge of the active layer is particularly enhanced. In the above structure, as an active layer in which a source region, a drain region, and a channel formation region are formed, a structure shown by 106, 108, and 107 in FIG. 1 can be given. In FIG. 1, 106 and 10
8 is a source region and a drain region, and 107 is a channel formation region. In the configuration shown in FIG.
Source / drain regions and channel formation regions are formed in the active layer (semiconductor layer indicated by 103).
Further, a lightly doped region or an offset gate region may be formed in the active layer.

According to another aspect of the present invention, there is provided an active layer having a source region, a drain region, and a channel forming region formed therein, and at least at the interface between the drain region and the channel forming region and / or in the vicinity thereof. Is characterized in that the crystallinity is particularly enhanced.

According to another aspect of the invention, a step of forming an amorphous silicon film on a substrate having an insulating surface; a step of crystallizing the amorphous silicon film to form a crystalline silicon film; Patterning a film to form an active layer; and irradiating the active layer with laser light or strong light.

In the above structure, examples of the substrate having an insulating surface include a glass substrate, a quartz substrate, a glass substrate having an insulating film formed thereon, a semiconductor substrate having an insulating film formed thereon, and a conductor substrate having an insulating film formed thereon. be able to.

As a method of crystallizing the silicon film, there are a method by heating, a method by irradiation with laser light or strong light, and a method by combining heating with irradiation with laser light or strong light. Further, it is useful to employ a crystallization method using a metal element which promotes crystallization of the amorphous silicon film. In this case, Fe, Co, Ni, Cu, Ru,
One or a plurality of elements selected from Rh, Pd, Ag, Os, Ir, Pt, and Au can be used. In particular, a remarkable effect can be obtained when Ni (nickel) is used. Specifically, a crystalline silicon film can be obtained by heat treatment at 550 ° C. (conventionally 600 ° C. or higher) for about 4 hours (conventionally 12 hours or longer). It is effective to combine laser light or strong light irradiation with crystallization by heating using the metal element.

In order to introduce this metal element into the amorphous silicon film, a thin film of the metal element or a thin film containing the metal element may be formed on the surface of the amorphous silicon film.

The concentration of the metal element in the active layer is 1 ×
It is preferably from 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . When the concentration is lower than this range, the effect of promoting crystallization is small, and when the concentration is higher than this range, the characteristics of the semiconductor show behavior as a metal, which is inconvenient for use in a semiconductor element. It will be something.

Irradiation of laser light or intense light after forming the active layer by patterning is performed by annealing the peripheral edge of the active layer to remove defects at the peripheral edge of the active layer, particularly at the side surface of the active layer. This is to reduce it.

It is effective to selectively irradiate the laser light or the intense light on the peripheral edge of the active layer. It is extremely effective to irradiate the side surface of the active layer with laser light.

Another invention disclosed in this specification includes a step of forming an amorphous silicon film on a substrate having an insulating surface, a step of crystallizing the amorphous silicon film to form a crystalline silicon film, Patterning the crystalline silicon film to form an active layer, irradiating the active layer with laser light or strong light, and forming a source / drain region opposite to a source / drain region on at least a part of a side surface of the active layer. Implanting an impurity for imparting a mold.

The order of the step of irradiating a laser beam or an intense light and the step of implanting an impurity imparting a conductivity type opposite to that of the source / drain region to at least a part of the side surface of the active layer may be reversed.

The source / drain region and the region into which the impurity imparting the opposite conductivity type is implanted must be at least the side surface of the active layer where the interface between the channel formation region and the source / drain region exists.

[0026]

The defects are formed intensively on the side surface of the active layer formed by patterning due to plasma damage and damage during etching. That is, defects are concentrated on the side surface of the active layer. Therefore, by irradiating laser light or intense light after forming the active layer, defects generated on the side surface of the active layer at the time of forming the active layer can be reduced. In particular, by irradiating the side surface of the active layer with laser light, defects existing on the side surface of the active layer can be effectively reduced.

As described above, the trap density on the side of the active layer can be reduced by reducing the defects existing on the side of the active layer by irradiating laser light or strong light. , The number of carriers that move via the network can be reduced. Thus, a thin film transistor having a small OFF current can be realized.

Further, by forming the peripheral end of the active layer to have a conductivity type opposite to that of the source / drain region, a PN junction is formed between the channel forming region and the source / drain region on the side surface of the active layer during the OFF operation. And the insulating property between the source and the drain can be improved.

[0029]

【Example】

Embodiment 1 FIG. 1 shows an example of a thin film transistor shown in this embodiment. First, a silicon oxide film 102 is formed as a base film on a glass substrate 101 to a thickness of 2000 ° by a sputtering method. Next, an amorphous silicon film is formed to a thickness of 1000 ° by a plasma CVD method or a low pressure thermal CVD method. Then, a crystalline silicon film is obtained by performing a heat treatment.
Irradiation with a laser beam after this heat treatment has a very large effect in improving the crystallinity of the obtained crystalline film. Next, patterning is performed by etching using the RIE method to form an active layer as indicated by 103 in FIG. In this state, the region indicated by 100 receives plasma damage. In particular, defects are intensively generated on the side surface of the active layer.

FIG. 3 is a sectional view taken along the line BB ′ of FIG.
Shown in (A) and (B) shown in FIG. 3 show a method of irradiating a laser beam described later. In addition, FIG.
A cross section taken along A ′ is shown in FIG. 1 and 3
As shown in (1), the region that is subjected to the plasma damage indicated by 100 extends over the entire peripheral side surface of the active layer.

Here, by irradiating a laser beam, it is possible to anneal the plasma damage on the side surface of the active layer indicated by 100. Of course, the crystallinity of the entire active layer is also improved. KrF as laser light
An excimer laser or a XeCl excimer laser can be used. At the same time as this laser beam irradiation,
It is effective to heat to a temperature of 00 to 500 ° C. This is because, by using heating in combination, the melting time of the silicon surface in accordance with the laser light irradiation is lengthened, and the annealing effect by the laser light irradiation is enhanced.

In place of laser light, strong light such as infrared light may be used. After irradiation with this laser light,
Further, heat treatment is effective in reducing defects in the active layer.

As a method of irradiating a laser beam, FIG.
(A) and (B). The method shown in (A) is performed over the entire surface from above, and is the most general method and is excellent in productivity and controllability. In this method, since energy is concentrated on the peripheral edge of the active layer, the crystallinity on the side surface of the active layer can be particularly increased. That is, the crystallinity on the side surface of the active layer can be made particularly high in the entire active layer.

The method shown in (B) is a method of irradiating a laser beam from a diagonal direction to positively irradiate the side surface of the active layer with the laser beam. When this method is adopted, the annealing effect on the side surface of the active layer can be extremely enhanced. In order to irradiate laser light from an oblique direction as shown in (B), the substrate may be irradiated with the laser light obliquely.

Thus, defects on the peripheral side surface of the active layer can be eliminated or greatly reduced. Next, a silicon oxide film 104 functioning as a gate insulating film is formed to a thickness of 1000 ° by a plasma CVD method. Then, a gate electrode 105 is formed by forming a coating mainly composed of known silicon doped with phosphorus at a high concentration and performing patterning. Then, phosphorus ions are implanted to form source / drain regions. Where N
Phosphorus ions are implanted to form a channel thin film transistor. If boron ions are implanted here, a P-channel thin film transistor can be obtained.

In this step, the source region 106 is self-aligned.
And a drain region 108 are formed. Further, a channel formation region 107 is formed at the same time. Then, laser light irradiation is performed to activate the source region 106 and the drain region 108. In this step, intense light may be irradiated instead of laser light. Alternatively, the source / drain regions may be activated by heating.

The silicon oxide film 10 is used as an interlayer insulating film.
9 is formed to a thickness of 7000 ° by a plasma CVD method, and a source electrode 110 and a drain electrode 111 are formed through a hole making step. Then, heat treatment is performed for 1 hour in a hydrogen atmosphere at 350 ° C., whereby FIG.
Is completed.

[Embodiment 2] This embodiment is an example in which the invention disclosed in this specification is applied to a thin film transistor having an offset gate structure and a lightly doped region. FIG. 4 illustrates a manufacturing process of the thin film transistor described in this embodiment.

First, a silicon oxide film is formed as a base film 402 on a glass substrate 401 to a thickness of 2000 .ANG. By a plasma CVD method or a sputtering method. Next, an amorphous silicon film 403 is formed to a thickness of 1000 ° by a plasma CVD method or a low pressure thermal CVD method. Then, nickel is introduced into amorphous silicon as a metal element for promoting crystallization of the amorphous silicon film. Here, nickel is introduced into the amorphous silicon film 403 using a nickel acetate salt solution.
That is, by applying a nickel acetate solution onto the amorphous silicon film 403 using a spinner, the amorphous silicon film 40
3 is in a state where the nickel element is in contact with and held on the surface. Here, the nickel concentration in the active layer is 1 × 10 ¹⁵
The amount of nickel introduced is controlled so as to be in the range of cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . Here, the amount of nickel to be introduced may be controlled by controlling the nickel concentration in the nickel acetate salt solution. In addition, as a method for introducing nickel, there are a plasma treatment, a sputtering method, and a plasma CVD method.
A method or an ion implantation method may be used.

The amorphous silicon film is transformed into a crystalline silicon film by heating or irradiating laser light, or by using both heating and laser light irradiation. Here, heat treatment is performed at 550 ° C. for 4 hours in a nitrogen atmosphere to obtain a crystalline silicon film. (FIG. 4 (A))

Next, patterning is performed to form an active layer 404 of the thin film transistor. Here, by performing isotropic etching, a peripheral end portion of the active layer 404 indicated by 420 is formed in a tapered shape. Details of this step will be described with reference to FIG. First, an extremely thin oxide film is formed on the upper surface of the silicon film 403. Here, 550 in an oxygen atmosphere
An oxide film 803 is formed by performing heat treatment at 1 ° C. for one hour. The oxide film 803 is necessary for preventing a resist formed later from directly contacting the silicon film 403 and preventing organic substances and the like from the resist from diffusing into the silicon film.

Next, a resist mask 800 is formed. Then, by performing isotropic plasma etching, FIG.
The etching proceeds as shown by dotted lines 802 and 801 in FIG. As a result, it is possible to obtain an active layer 404 that is formed in a tapered shape as indicated by 420. In this state, at a dose of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² , ions of an impurity imparting a conductivity type opposite to that of the source / drain regions are implanted. The implantation of the impurity ions is performed by using the remaining resist mask 800.
Is performed in the tapered region of the active layer shown by the oblique lines in FIG. 8C.
This is shown in FIG. FIG. 9 shows FIG. 8C as viewed from above. A cross section taken along line AA ′ in FIG. 9 corresponds to FIG. In this case, an impurity imparting a conductivity type opposite to that of the source / drain region is doped all around the active layer. Here, boron ions are implanted at a dose of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² . Since this step can be performed in a self-aligned manner using the remaining resist mask 800, it is significant that it is not necessary to newly add a mask. Then, the resist mask 800 and the oxide film 803 are removed to obtain a state shown in FIG. The state shown in FIG. 8D corresponds to FIG.

By making the portion indicated by 420 a tapered shape, it is possible to make a structure in which the wiring formed on the active layer 404 does not break down. But 42
Since plasma damage is concentrated on the peripheral edge and peripheral side surface of the active layer indicated by 0, many traps are concentrated. Therefore, laser light irradiation is performed to reduce traps on the peripheral side surface of the active layer. The irradiation with the laser beam performed here may be performed on the entire surface of the active layer as shown in FIG.
As shown in (B), the process may be performed obliquely to the edge of the active layer.

Thereafter, the silicon oxide film 400 is formed by plasma CVD.
The film is formed by a method or a low pressure thermal CVD method. Then 600
An aluminum film is formed to a thickness of 0 ° by electron beam evaporation or sputtering. This aluminum film contains 1 wt% of silicon or 0.1 wt% of scandium. And 50 to 10 on the surface of the aluminum film.
An anodic oxide film 405 of about 0 ° is formed. This anodic oxide film is formed by performing anodic oxidation using an aluminum film as an anode in an ethylene glycol solution containing 3 to 10% tartaric acid. Here, the applied voltage is 1
A dense barrier type anodic oxide film is formed at a voltage of 00 to 200 V, for example, 150 V.

Then, a mask using a photoresist is formed, and an aluminum film 406 patterned by a dry etching method is formed. On this aluminum film, there is a dense oxide layer 405 formed by the previous anodic oxidation. (FIG. 4 (C))

Next, by performing anodization in a 3-20% citric acid or nitric acid solution, a thickness of 3000Å-1
a porous oxide layer 4 having a thickness of, for example, 5000 .mu.m.
07 is formed. Here, this anodic oxidation is performed in a 10% nitric acid solution at 30 ° C. by applying a voltage of 10 V for 25 minutes. (FIG. 4 (D))

Next, the dense oxide layer 405 is removed, and anodic oxidation is again performed in an ethylene glycol solution containing tartaric acid to form a dense oxide layer 408. The thickness of this oxide layer 408 is 2000 °. In this anodic oxidation step, a gate electrode 409 containing aluminum as a main component is determined. (FIG. 4E)

Then, the silicon oxide film 400 is removed by dry etching using the oxide 407 as a mask. Thus, the state shown in FIG. 5A is obtained.

After the state shown in FIG. 5A is obtained, the porous oxide layer 407 is selectively etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Then, impurity ions are implanted to form source / drain regions. Where N
In order to manufacture a channel thin film transistor, phosphorus ions are implanted. Here, 5 × 10 ^{14 to} 5 × 10 ¹⁵
Phosphorus ions are implanted at a dose of cm ⁻² .

In this step, the source region 410 and the drain region 416 are formed in a self-aligned manner. In addition, lightly doped regions 411 and 415, and offset gate regions 412 and 414 are simultaneously formed. The lightly doped regions 411 and 415 are formed by performing ion implantation at a lower concentration than the source region 410 and the drain region 416 because part of the implanted ions is blocked by the remaining silicon oxide film 400. Further, impurity ions are not implanted into the offset gate regions 412 and 414 using the oxide layer 408 around the gate electrode 409 as a mask. (FIG. 5 (B))

Then, a silicon oxide film 417 is used as an interlayer insulating film.
Is formed to a thickness of 6000 ° by a plasma CVD method. Further, a source electrode 418 and a drain electrode 419 are formed through a hole forming step. Here, since the end side surface of the active layer is formed in a tapered shape, it is possible to adopt a configuration in which the electrode wiring formed on the active layer is not disconnected.
That is, since the side surface around the active layer denoted by reference numeral 420 is formed in a tapered shape, various electrode wirings formed above the active layer are formed at a smooth angle and have no step disconnection. be able to. Further, since the region formed in a tapered shape has a conductivity type opposite to that of the source / drain region, a P-type region between the channel formation region and the source / drain region on the side surface of the active layer during the OFF operation.
An N junction is formed, and the insulation between the source and the drain can be increased. Therefore, the OFF current can be reduced.

FIG. 6 shows a photograph of a cross section of the completed thin film transistor. FIG. 6 shows a thin-film active layer and a tapered end thereof. FIG. 7 shows a photograph of the thin film transistor taken from above. This FIG.
The photograph shown by indicates a fine pattern formed on the substrate. A cross section cut along AA ′ in FIG. 7 corresponds to FIG. 5C, and a cross section cut along BB ′ in FIG. 7 corresponds to FIG.

Finally, a heat treatment is performed in an atmosphere of normal pressure hydrogen at 350 ° C. to hydrogenate the active layer, thereby completing a thin film transistor.

[0054]

The thin film transistor having a small OFF current can be obtained by particularly increasing the crystallinity on the side surface of the active layer.

[Brief description of the drawings]

1A to 1C illustrate a manufacturing process of a thin film transistor described in an example.

FIG. 2 is a diagram showing a schematic configuration of a general thin film transistor.

FIG. 3 is a diagram showing a method for irradiating a laser beam to an active layer.

FIG. 4 illustrates a manufacturing process of a thin film transistor described in an example.

FIG. 5 illustrates a manufacturing process of a thin film transistor described in an example.

FIG. 6 is a photograph showing a thin film constituting a thin film transistor.

FIG. 7 is a photograph showing a fine pattern (thin film transistor) formed on a substrate.

FIG. 8 is a view showing a step of forming an active layer.

FIG. 9 is a top view of FIG.

[Explanation of symbols]

101 glass substrate 102 silicon oxide film (base film) 103 active layer 104 silicon oxide film (Gate insulating film) 105: Gate electrode 106: Source region 107: Channel forming region 108: Drain region 109 interlayer insulating film 110 source electrode 111 drain electrode 201 glass substrate 202 ... Silicon oxide film 203... Source region 204... Channel formation region 205... Drain electrode 206. Gate insulating film 207 ... Gate electrode 208 ... Interlayer insulating film 20 9 Source electrode 210 Drain electrode 21 Source region 22 Channel formation region 23 ... Drain region 400... Silicon oxide film (gate insulating film) 401 glass substrate 402... Silicon oxide film (base film) 403... Silicon film 404... Active layer (crystalline silicon film) 405... Oxide layer (dense oxide layer) 406. ... Aluminum film 407 ... Oxide layer (porous oxide layer) 408 ... Oxide layer (dense oxide layer) 409 ... Gate electrode 410... Source region 411, 415. ······ Offset gate region 413 ······ Channel formation region 416 ······· Drain region 417 ··········· Interlayer insulating film 418 ······ .Source electrode 419... .Drain electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-99347 (JP, A) JP-A-4-290443 (JP, A) JP-A-63-12160 (JP, A) JP-A-62 190878 (JP, A) JP-A-6-168876 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21/336

Claims (13)

(57) [Claims] A metal element which has a source region, a drain region, and a channel formation region and promotes crystallization is 1 × 10
¹⁵ cm ^-3 has an active layer including a concentration of ~1 × 10 ¹⁹ cm ^-3, an interface between the drain region and the channel forming region also
Side of the active layer in the vicinity of the interface, the active layer
A semiconductor device characterized by being a portion having high crystallinity in the semiconductor device. 2. The device according to claim 1, wherein the side surface of the active layer is
A semiconductor device characterized by being formed in a tapered shape.
Place. 3. A source region, a drain region and a channel type.
And a metal element that promotes crystallization is 1 × 10
Activity contained at a concentration of ¹⁵ cm ^-3 to 1 × 10 ¹⁹ cm ^-3
A layer, the junction between the drain region and the channel forming region or
Or the end of the active layer near the junction is
Characterized in that it is a portion having high crystallinity in the conductive layer.
Conductor device. 4. The device according to claim 3, wherein the end of the active layer is
A semiconductor device characterized by being formed in a tapered shape.
Place. 5. A any one of claims 1 to 4,
The semiconductor device, wherein the active layer has crystallinity. 6. The method according to claim 1, wherein
The active layer is formed on a substrate having an insulating surface.
Glass substrate as the substrate having the insulating surface, quartz
Substrate, glass substrate with insulating film formed, insulating film formed
Semiconductor substrate or conductor substrate with insulating film formed
A semiconductor device characterized by being inserted. 7. forming an amorphous silicon film on a substrate having an insulating surface, the amorphous silicon film is crystallized by the crystalline silicon film, an active layer by patterning the crystalline silicon film formed, a method for manufacturing a semiconductor device comprising a selectively anneal to Turkey the sides of the front <br/> Symbol active layer by irradiating laser light or strong light to the active layer. 8. forming an amorphous silicon film on a substrate having an insulating surface, the amorphous silicon film is crystallized by the crystalline silicon film, an active layer by patterning the crystalline silicon film formed, in the method for manufacturing a semi <br/> conductor arrangement you irradiated with laser light or strong light to the active layer, the side surface of the active layer is formed in a tapered shape, the laser light or the strong light when irradiated, a method for manufacturing a semiconductor device characterized by selectively irradiating the portion formed in the tapered shape. 9. An amorphous silicon film on a substrate having an insulating surface
Is formed, and the amorphous silicon film is crystallized to form a crystalline silicon film, the crystalline silicon film is patterned to form an active layer, and the active layer is irradiated with laser light or strong light. Previous
Characterized in that the edge of the active layer is selectively annealed.
Manufacturing method of a semiconductor device. 10. An amorphous silicon film on a substrate having an insulating surface.
Forming a film, crystallizing the amorphous silicon film into a crystalline silicon film, patterning the crystalline silicon film to form an active layer, and irradiating the active layer with laser light or strong light. Half
In the method for manufacturing a conductor device, an end of the active layer is formed in a tapered shape, and when the laser light or the strong light is applied, the
It is characterized by selectively irradiating the tapered portion.
A method for manufacturing a semiconductor device. 11. Amorphous silicon on substrate with insulating surface
Forming a film, Crystallizing the amorphous silicon film into a crystalline silicon film, Patterning the crystalline silicon film to form an active layer, At the end of the active layer, the source region or the drain
Implanting an impurity that imparts a conductivity type opposite to that of the Irradiating the active layer with laser light or strong light
Characterized in that the edge of the active layer is selectively annealed.
Manufacturing method of a semiconductor device. 12. Amorphous silicon on substrate with insulating surface
Forming a film, Crystallizing the amorphous silicon film into a crystalline silicon film, Patterning the crystalline silicon film to form an active layer, At the end of the active layer, the source region or the drain
Implanting an impurity that imparts a conductivity type opposite to that of the Irradiating the active layer with laser light or strong light;
In the method for manufacturing a conductor device, Forming an end of the active layer in a tapered shape, When irradiating the laser light or the strong light, the
It is characterized by selectively irradiating the tapered portion.
A method for manufacturing a semiconductor device. 13. The method according to claim 7 , wherein the amorphous silicon film is crystallized when crystallizing the amorphous silicon film.
By introducing a metal element for promoting crystallization of silicon films, a method for manufacturing a semiconductor device, which comprises carrying out the heat treatment.