JP3124611B2 - Semiconductor device having MOS anode short auxiliary gate structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic induction thyristor (SI thyristor) as a power semiconductor device having a bipolar junction and requiring high-speed switching and low loss,
Gate turn-off thyristor (GTO) and insulated gate bipolar transistor (Insulated Gate Bipolar T)
MOS anode short auxiliary gate structure in which the characteristics of a semiconductor element having a MOS anode short structure can be further improved by optimizing the anode electrode structure and improving the trade-off between the turn-off performance and the turn-on performance in IGBTs and the like. And a semiconductor device having:

[0002]

2. Description of the Related Art Heretofore, a structure in which an n-buffer layer is provided on the anode side has been manufactured as a structure that emphasizes on-performance with a view to increasing the breakdown voltage. In contrast to this structure, to improve the off performance, a structure having no n-buffer layer can keep the on-voltage low while improving the turn-off performance. A structure in which a layer is short-circuited to the anode side by an n ⁺ layer has been proposed in the example of GTO. The anode short structure using the electrostatic induction effect is described in, for example, a document “SI thyristor with a new anode short structure”, IEICE Electronics Device Research Group, ED
D-87-66, pp. 37-49 (October 7, 1987). Alternatively, Japanese Patent Laid-Open No. 1-9316
No. 9, “Power Semiconductor Element”. Examples of the GTO structure in which the n-buffer layer is short-circuited to the anode side by the n ⁺ layer include, for example, a document “6 kVGTO thyristor employing an N-buffer and a new anode short structure”, IEICE Electronics Device Research Group, EDD-87-65, pp.2
7-35 (October 7, 1987). FIG. 14 shows an example in which the latter structure is applied to an SI thyristor. On the other hand, a "semiconductor device having a MOS anode short structure" has been disclosed in Japanese Patent Application No. 3-280646 by the same applicant as the present applicant.

In FIG. 14, 1 is an anode electrode, 2 is a gate electrode, 3 is a cathode electrode, 4 is an anode p emitter layer (p _E ) layer, 5 is an n ⁺ short layer, 6 is an n buffer layer, and 7 is a high buffer layer. A resistance semiconductor layer, 8 is a p gate layer, 9 is a passivation film, and 8 'is a cathode n emitter layer (n _E ) layer. In FIG. 14, by setting the thickness and impurity concentration of n-buffer layer 6 to predetermined values, the electric field in the depletion layer spreading in high-resistance semiconductor layer 7 can be maintained at a high value. Easy structure. But n
Excessive hole injection from the anode p emitter layer 4 is caused by the accumulation effect of the electrons accumulated in the buffer layer 6. FIG. 14 shows a structure in which an n ⁺ short layer 5 is provided to help outflow of electrons accumulated in the n buffer layer 6.

However, the conventional purpose of the anode short structure having the n-buffer layer (6) is to secure a withstand voltage, and when the concentration of the n-buffer layer (6) is increased,
It is difficult to improve the off performance by increasing the anode short ratio. If the anode short rate rises too much,
The on-voltage rises rapidly, and the latch-up operation that turns on the thyristor becomes impossible. In this case, the off-loss (of
f-loss) falls, but on-loss rises sharply.
Improving the trade-off between on (on) performance and off (off) performance, improving both performances, and achieving both are the conventional n
It is extremely difficult for a semiconductor device having a buffer structure.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a MOS anode short auxiliary gate structure in which a thyristor structure having an n-buffer layer has an excellent trade-off between on performance and off performance. It is in.

[0006]

An example of the configuration of the present invention is as follows. That is, the present invention relates to a cathode n emitter layer (8 ') and a p base layer or p
In a bipolar semiconductor device in which a layer including a gate layer (8), a high-resistance semiconductor layer (7), an n-buffer layer (6), and an anode p-emitter layer (4) is laminated, the anode p An etching process is performed on the emitter layer (4), and a MOS anode short layer (5 ″) serving as an n ⁺ short layer is provided at an end of the anode p emitter layer (4) facing the etching groove (12). 4), but not in contact with the n-buffer layer (6), and a portion of the MOS anode short layer (5 ″) serving as an n ⁺ short layer from the etching groove (12) is formed by SiO 2. _The anode electrode (1) was formed by covering the entire anode side with the metal after covering with the _two membranes (10).
For a semiconductor device having a MOS anode short structure, a short auxiliary gate formed by insulating an insulating film (14) with respect to the anode electrode (1) along the SiO ₂ film (10) in the etching groove (12). Electrode (hereinafter SA)
It has a configuration as a semiconductor element having a MOS anode short auxiliary gate structure to which a G (Short Assist Gate) electrode (13) is added.

Alternatively, the present invention has a configuration as a semiconductor device having a MOS anode short structure, characterized in that an n ⁺ short auxiliary layer (5 ') is provided at the bottom of the etching groove.

[0008]

FIGS. 9 to 12 are diagrams for explaining the operation principle of a semiconductor device having a MOS anode short auxiliary gate structure according to the present invention. Each figure includes a schematic diagram corresponding to an energy band diagram, carrier movement, and VI characteristics (voltage-current characteristics between the anode and the cathode). The operation of each structure in each operation of the SI thyristor as a semiconductor element will be described.

FIG. 9 shows the ignition characteristics. At this time, SAG
The electrode (13) and the anode electrode (1) are short-circuited. Shows a case applied forward voltage V _D low at about 25V about 9. At this time, the MOS channel (11) is hardly working. In other words, in this state, the operation is as if there was no MOS anode short-circuit, and the operation is a reverse blocking thyristor.

FIG. 10 shows the turn-on characteristics. At this time, the SAG electrode (13) and the anode electrode (1) are short-circuited. The V _D, for example, 1/2 of the forward withstand voltage shows a case about 1250V and higher. At this time, the MOS channel (11) is connected to the cathode n
The electron injection from the emitter layer (8 '), that is, the operation of flowing through the n-buffer layer (6) is performed. In addition, holes start to be injected from the anode p emitter layer (4) to the nMOS channel (11). That because SI thyristor is shifted to the ON operation, V _D drops rapidly MOS channel (11) disappears, the hole injection still occurs in a large amount. That is, the operation becomes close to the reverse blocking thyristor operation again.

FIG. 11 shows the conduction characteristics. At this time, SA
The G electrode (13) and the anode electrode (1) are short-circuited. V _D is about ON voltage because of conduction and 2.5
A case where the voltage is as low as V is shown. At this time, the MOS channel (11) is not operating. That is, the operation of the reverse blocking thyristor is performed, and the ON voltage is lower than that of the thyristor having the conventional anode short structure.

FIG. 12 shows the turn-off characteristics. When a hole current is drawn from the gate electrode (2), a reverse bias is applied between the gate electrode (2) and the cathode electrode (3),
Carriers decrease sharply, and the periphery of the p gate layer (8) is depleted. 'The depletion layer forming extending between the cathode n emitter layer (8 p gate layer (8) cathode n emitter layer (8)' electron injection from) is stopped, the anode-cathode voltage V _D increases Accompanying the SAG electrode (1
By positively biasing 3) with respect to the anode electrode (1), the MOS channel (11) is actively conducted, so that the MOS channel (11) is in the high-resistance semiconductor layer (7) and the n-buffer layer (6).
The electrons that remain floating therein conduct from the n ⁺ short auxiliary layer (5 ′) to the MOS anode short layer (5 ″) via the MOS channel (11) and are swept out to the anode electrode (1). In some cases, unlike the case of the turn-on operation, the electron injection is performed in the cathode n emitter layer (8 ').
The recombination process of hole injection is mainly due to recombination with residual electrons, and the location where the carrier recombination process is likely to occur between the n-buffer layer (6) and the anode p-emitter layer (4). Becomes The tail current in the latter half of the turn-off can be positively reduced. In other words, in the turn-off operation, the MOS channel (11) continues to operate positively, so that the effect of anode short-circuiting becomes strong, the turn-off time is shortened, and the tail current is reduced.

As described above, the principle of operation of the present invention is that, in the MOS anode short auxiliary gate structure, at the time of turn-off, the SAG electrode (13) is positively biased to activate the MOS channel and activate the discharge of electrons. It is a thing using. As a result, the on-operation is close to the operation of the reverse blocking thyristor, and the
In the off operation, device characteristics with excellent off performance such as a strong anode short type can be obtained.

[0014]

Embodiment 1 FIG. 1 shows an embodiment of a semiconductor device having a MOS anode short auxiliary gate structure according to the present invention, and is a schematic sectional structural view of an electrostatic induction thyristor having a MOS anode short auxiliary gate structure. In FIG. 1, 1 is an anode electrode, 2 is a gate electrode, and 3 is a cathode electrode. 4 is an anode p emitter layer and 5 'is n ⁺
The short auxiliary layer 5 ″ is a MOS anode short layer that functions similarly to the n ⁺ short layer (5) in the conventional example (FIG. 7). 6 is an n buffer layer, 7 is a high resistance semiconductor layer, and 8 is p. A gate layer or p base layer, 8 'is a cathode n emitter layer, 9 is a passivation film between the gate and cathode, 10 is a SiO ₂ film which functions as an insulating film of a MOS anode short structure.
Indicates a MOS channel in the MOS anode short structure. Reference numeral 13 denotes a short auxiliary gate electrode, which is electrically insulated from the anode electrode 1 by the insulating film 14,
Pulled out.

A brief description of the manufacturing method is as follows. In order to apply to the SI thyristor (FIG. 1), the anode p emitter layer (p _E layer) 4 is locally removed by etching until reaching the n buffer layer 6 to form an etching groove 12, and the formed island-shaped anode p the emitter layer (p _E layer) 4
Thinner than the anode p emitter layer 4 on the end, provided with MOS anode short layer 5 'to the same role as n ⁺ short layer. Further, n in a central location that etching of the ⁺
A short auxiliary layer 5 'may be provided. MOS anode short layer 5 "and n ⁺ anode p emitter layer up to the short auxiliary layer 5 '(p _E layer) 4 to form a MOS channel 11 in the region's surface causing MOS operation, SiO ₂
A membrane 10 is provided. This etching groove 12, SiO ₂ film 1
In accordance with 0, the SAG electrode 13 is selectively formed by vapor deposition to form an insulating polyimide film. An anode electrode 1 is deposited thereon. The method of manufacturing the structure on the cathode side is the same as that of the conventional example shown in FIG.

The features of the embodiment as a semiconductor device having a MOS anode short auxiliary gate structure will be described below. In FIG. 1, a MOS structure is formed by the anode electrode 1, the SiO ₂ film 10 and the anode p emitter layer 4, and carriers in the n short auxiliary layer 5 'or the n buffer layer are turned on by the MOS channel 11 so that a MOS anode short layer is formed. 5 "is performed.

In the n-channel MOSFET equivalently formed by this MOS anode short structure, the MOS anode short layer 5 "can be regarded as the source, and the anode p emitter layer 4 serving as the substrate is short-circuited to the equivalent source. N equivalently acting as a drain
The potential of the buffer layer 6 or the n ⁺ short auxiliary layer 5 ′ is zero or negative compared to the equivalent source potential, that is, the potential of the anode electrode 1. The larger the amount of electrons stored in the cell, the larger the value of the negative potential. However, this potential difference is at most about 1 V in the case of silicon, which is extremely low. The above-described equivalent n-channel MOSFET formed by the MOS anode short-circuit structure has a reverse potential of the equivalent n-channel MOSFET during execution of the MOS anode short-circuit operation because the drain potential is negative compared to the source. Operation. The reverse bias is about 1 V or less.
It is extremely important for the performance of the anode short. The channel length of this equivalent n-channel MOSFET, the thickness of the SiO ₂ film 10 as an insulating film, the impurity density or the channel doping level of the channel in the MOS channel 11, the channel width as a whole, and the total channel of the MOS anode short The number (or the pitch for forming the MOS anode short) and the plane orientation for forming the MOS channel 11 may be, for example, 100 planes.
This is a factor that determines the resistance of the OS anode short-circuit, and it can be said that the means for lowering the on-resistance of the normal MOSFET similarly works effectively.

In the present invention, a short auxiliary gate electrode 13 is added to make the MOS anode short structure work more effectively. Therefore, MOS anode short circuit
Channel formation becomes smoother, and carrier extraction at turn-off becomes faster.

In the embodiment shown in FIG. 1, an electrostatic induction thyristor having a MOS anode short auxiliary gate structure has been described as an example. However, as a semiconductor device having another structure,
For example, it is easily conceivable to apply the MOS anode short auxiliary gate structure according to the present invention to a gate turn-off thyristor, an insulated gate bipolar transistor (IGBT), a plane gate type SI thyristor, a buried gate type SI thyristor, and the like. It is an example.

[0020]

Embodiment 2 FIG. 2 shows a structural example of a semiconductor device having a MOS anode short auxiliary gate structure as another embodiment (embodiment 2) of the present invention. Short auxiliary gate electrode 1
Numeral 3 is an example formed substantially in a trapezoidal shape. An inclined tapered etching surface having a specific plane orientation is formed on the silicon surface using an anisotropic etching technique, and a MOS channel 11 is formed on the tapered silicon surface 15. Since the MOS channel 11 can be formed in a specific plane orientation and the thickness of the taper can be easily controlled, an equivalent channel of the MOSFET is formed as compared with the case where the trench for the MOS channel is formed by simple mesa etching. It is characterized in that the length can be easily controlled and the effect of MOS anode short can be stably maintained. In FIG. 2, components having the same functions as those in FIG. 1 are denoted by the same reference numerals.

[0021]

Third Embodiment FIG. 3 is a structural example of a semiconductor device having a MOS anode short auxiliary gate structure as another embodiment (third embodiment) of the present invention. Short auxiliary gate electrode 1
3 is formed in a trapezoidal shape opposite to the case of FIG. 2 (Example 2). In the example of FIG. 3, since the short auxiliary gate electrode 13 has an inverted trapezoidal shape as compared with FIG. 2, the MOS anode short layer 5 ″ can be formed in a relatively small area, and as a result, the anode The area of the p-emitter layer 4 can be widened, and the anode side shape in FIGS. 2 and 3 can be a known dielectric isolation process, a polycrystalline silicon single crystallization process, an anisotropic etching process, or a silicon substrate. The second and third embodiments are characterized in that the anode electrode 1 can be formed flat.
In FIG. 3, the same reference numerals are given to components having the same functions as those in FIGS.

[0022]

Fourth Embodiment FIG. 4 is a structural example of a semiconductor device having a MOS anode short auxiliary gate structure as another embodiment (Embodiment 4) of the present invention. The structural features of Example 4 are as follows:
n ⁺ short auxiliary layer 5 ', MOS channel 11 and MO
The S anode short layer 5 ″ is formed on a substantially flat silicon surface (anode surface), and therefore, the short auxiliary gate electrode 13 has a structure that can be formed very easily in a planar shape. An n ⁺ short auxiliary layer 5 ′ is formed to extend to the silicon surface on the anode side, and the structure shown in FIG.
The feature is that a process of forming an n-channel MOSFET by a planar process can be easily applied. In FIG. 4, the same reference numerals are given to components having the same functions as those in FIGS.

[0023]

Fifth Embodiment FIG. 5 is a structural example of a semiconductor device having a MOS anode short auxiliary gate structure as another embodiment (Embodiment 5) of the present invention. The structural features of Example 5 are as follows:
The point is that a MOSFET using the n ⁺ short auxiliary layer 5 ′ and the MOS anode short layer 5 ″ as equivalent source / drain is formed almost vertically. In order to realize this structure, in the fifth embodiment, The short auxiliary gate electrode 13 has a substantially rectangular cross section and is formed substantially embedded in the anode p-emitter layer 4. The manufacturing method is as follows.
After forming a substantially rectangular groove by IE or ECR plasma etching, etc., and removing the damaged layer at the silicon interface which is the MOS interface, the SiO ₂ film 10 is formed, and the short auxiliary gate electrode 13 is formed by polysilicon or the like. . As is clear from FIG. 5, in the fifth embodiment, the anode electrode 1
Is also characterized in that it can be formed almost flat.
In FIG. 5, the same reference numerals are given to components having the same functions as those in FIGS.

[0024]

Sixth Embodiment FIG. 6 is a structural example of a semiconductor device having a MOS anode short auxiliary gate structure as another embodiment (Embodiment 6) of the present invention. The structure of the MOS anode short auxiliary gate is substantially the same as that of the fifth embodiment shown in FIG.
The structural feature of the sixth embodiment is that it has a highly diffused region in the anode p emitter layer 4, that is, an anode p ⁺ emitter region 4 '. By the function of the anode p ⁺ emitter region 4 ′, the anode p emitter layer 4 and the MOS
The feature is that the lateral resistance between the anode short auxiliary layer 5 ″ can be reduced and the short function of MOS anode short can be increased.
In FIG. 6, the same reference numerals are given to components having the same functions as those in FIGS. 1 to 5.

[0025]

Seventh Embodiment FIG. 7 is a structural example of a semiconductor device having a MOS anode short auxiliary gate structure as another embodiment (Embodiment 7) of the present invention. The MOS anode short auxiliary gate structure is substantially the same as in the fifth and sixth embodiments. The point that an anode p ⁺ emitter region 4 ′ is provided is substantially equivalent to the sixth embodiment. Structural features of embodiment 7 of Fig. 7, n the buffer layer 6 is n ⁺ n ^- in that has a structure ^- n ⁺ n. The n ⁻ portion of the n buffer layer 6 is sufficiently depleted by a depletion layer extending from the n ⁺ portions on both sides, and the potential of the n ⁻ portion has a size and an impurity density which are determined by the potential of the n ⁺ portion by capacitive coupling. Designed to have. Moreover, the aforementioned anode p ⁺
The p _E layer 4 and the n ⁻ portion are arranged in front of the emitter region 4 ′, and holes injected from the anode p ⁺ emitter region 4 ′ pass through the n ⁻ portion and pass through the ni layer 7. It has a structure that is easy to be injected. On the other hand, the ni layer 7
Electrons and n of the inner ^- portion of the electron or electrons injected from the n _E layer 8 'has a predominantly accumulated in structure easy to n ⁺ portion of the n buffer layer 6. The seventh embodiment having such a structural feature has a feature that the effect of MOS anode short-circuit at the time of turn-off is increased, and conversely, the on-resistance at the time of turn-on is easily reduced. In FIG. 7, the same reference numerals are given to components having the same functions as those in FIGS.

[0026]

[Embodiment 8] FIG. 8 is a structural example of a semiconductor device having a MOS anode short auxiliary gate structure as another embodiment (Embodiment 8) of the present invention. The structural feature of FIG. 8 is that the structure of the seventh embodiment is reduced in the lateral direction. n buffer layer 6
Have an n ⁺ n ^- n ⁺ n ^- structure and are formed at a constant pitch. The n ⁺ portion of the n buffer layer 6 functions as the n ⁺ short auxiliary layer 5 ′. Increasing the number of MOS channels 11;
It has a structural feature that increases the effect of MOS anode short. Therefore, the short auxiliary gate electrode 13
Is at n ⁺ portion of the same pitch in the anode p emitter layer 4, moreover are arranged formed through the insulating film 10 and the n ⁺ portion. The n ⁺ short auxiliary layer 5 ′ and the MOS anode short layer 5 ″ are arranged almost vertically, and a number of equivalent vertical MOSFETs are vertically formed by the short auxiliary gate electrode 13 (for details, see an enlarged view). M
The OS anode short layer 5 ″ and the anode p ⁺ emitter region 4 ′ have a structure formed in contact with each other, but both have the same potential due to the anode electrode 1.
Of course, they may be formed apart from each other. The structure of the eighth embodiment shown in FIG. 8 is characterized in that the number of MOS channels is increased as compared with the first to seventh embodiments, so that the effect of MOS anode short-circuit is increased.
In FIG. 8, the same reference numerals are given to components having the same functions as those in FIGS. 1 to 7.

[0027]

FIG. 13 shows a 2500 V / 300 A class device in which the cathode side structure is fixed (SI thyristor structure) and the anode side structure is a conventional example (FIG. 14) and an example of the already disclosed MOS anode short structure. examples of MOS anode short auxiliary gate structure preparative invention and a graphical view turn-on loss (turn-on-loss) E on and the turn-off loss (turn-off-loss) E off relationship with the case (FIG. 1) It is. As the switching condition, V _D = 12
50 V, I _T = 300 A, T _j = 125 ° C. Compared with the conventional example, turn-on loss E _on and turn-off loss E _off of the trade-off in the present invention is improved, it is excellent.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a schematic cross-sectional structural view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 2) of the present invention;

FIG. 3 is a schematic sectional view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 3) of the present invention.

FIG. 4 is a schematic sectional structural view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 4) of the present invention.

FIG. 5 is a schematic sectional view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 5) of the present invention.

FIG. 6 is a schematic sectional view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 6) of the present invention.

FIG. 7 is a schematic sectional view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 7) of the present invention.

FIG. 8 is a schematic cross-sectional view of a semiconductor device (static induction thyristor) having a MOS anode short auxiliary gate structure as an embodiment (Embodiment 8) of the present invention, and an enlarged view in the vicinity of the MOS anode short auxiliary gate structure.

FIG. 9 is an explanatory view of the operation principle of a semiconductor device having a MOS anode short auxiliary gate structure according to the present invention, which is an explanatory view of an ignition characteristic (energy band diagram, carrier movement,
(Vi characteristics)

FIG. 10 is an explanatory view of the operation principle of the semiconductor device having the MOS anode short auxiliary gate structure of the present invention, and is an explanatory view of a turn-on characteristic (energy band diagram, carrier movement, VI characteristic).

FIG. 11 is a diagram illustrating the operation principle of the semiconductor device having the MOS anode short auxiliary gate structure according to the present invention, and is a diagram illustrating conduction characteristics (energy band diagram, carrier movement, VI characteristics).

FIG. 12 is a diagram for explaining the operation principle of the semiconductor device having the MOS anode short auxiliary gate structure of the present invention, and is a diagram for explaining turn-off characteristics (energy band diagram, carrier movement, VI characteristics);

FIG. 13 shows the turn-on loss E _on and the turn-off loss E _off of a semiconductor device having a MOS anode short auxiliary gate structure according to the present invention and a semiconductor device having a conventional anode short structure (including a MOS anode short structure). Comparison diagram of trade-off relationship

FIG. 14 is a schematic cross-sectional view of a static induction thyristor having a conventional anode short structure as a prior art of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 anode electrode 2 gate electrode 3 cathode electrode 4 anode p emitter layer (p _E layer) 4 ′ anode p ⁺ emitter region 5 n ⁺ short layer 5 ′ n ⁺ short auxiliary layer 5 ″ MOS anode short layer 6 n buffer layer (n Buffer) 7 high resistance semiconductor layer ( _ni layer) 8 p gate layer or p base layer 8 'cathode n emitter layer (n _E layer) 9 passivation film 10 SiO ₂ film 11 MOS channel 12 etching groove 13 short auxiliary gate electrode 14 Insulating film 15 Tapered silicon surface

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/74 H01L 29/744 H01L 29/78 655

Claims (2)

(57) [Claims] 1. A bipolar semiconductor device in which a layer including a cathode n-emitter layer, a p-base layer or a p-gate layer, a high-resistance semiconductor layer, an n-buffer layer, and an anode p-emitter layer is laminated. In the above, the anode p emitter layer is subjected to etching, and a MOS anode short layer serving as an n ⁺ short layer at the end of the anode p emitter layer facing the etching groove is brought into contact with the anode p emitter layer and with the n buffer layer. MO that functions as an n ⁺ short layer from the etching groove
In a semiconductor device in which a portion of the S anode short layer is covered with a SiO ₂ film and the entire anode side is covered with a metal, along a SiO ₂ film in the etching groove,
A semiconductor device having a MOS anode short auxiliary gate structure, wherein an insulated metal electrode is added to an anode electrode. 2. The semiconductor device having a MOS anode short auxiliary gate structure according to claim 1, wherein an n ⁺ short auxiliary layer is provided at the bottom of said etching groove.