JP3124642B2 - ATM switch system switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to system switching of an ATM switch.
In particular, the present invention relates to an ATM switch which has a duplex configuration in which two identical ATM communication paths are arranged in parallel, switches the current operating system to the standby system without instantaneous interruption, and switches the operating state by changing the current standby system to the operating system. The present invention relates to a system switching method .

[0002]

2. Description of the Related Art There is a growing need for multimedia communication including not only voice communication and data communication but also moving image communication. As a means for realizing such broadband communication, an asynchronous transfer mode (Asynchronous Transfer Mode) has been proposed.
de: ATM) based B-ISDN (Broadband-
ISDN) exchange technology has been agreed at CCITT and research is ongoing.

In the current time division multiplexing system of the digital switching system, the time axis is divided into time slots at predetermined time intervals, multiplexed transmission is performed by allocating N channel data to each time slot and synchronizing each channel. To achieve. On the other hand, in the ATM method, a line is allocated to a plurality of calls by multiplexing logical links on a physical line. Then, image data, audio data, and the like from the terminal corresponding to each call are decomposed into fixed-length information units (referred to as cells) and sequentially transmitted to the line to realize multiplexing. still,
In the ATM system, even cells having the same destination are sent out to the line asynchronously. Further, a break between cells is identified based on a header written in the cell.

As shown in FIG. 11, a cell is composed of a fixed-length block of 53 bytes, of which 5 bytes are a header part HD and 48 bytes are an information field (information part) DT. The header part HD has a virtual channel identifier (Virtual Channel Identifier: VC) for call identification so that the destination can be recognized even after the data is decomposed into blocks.
I), and an identifier (Virtual Path Identifier) of a virtual path generated by combining several virtual channel numbers.
ifier: VPI) and a generic flow control GFC (Generic Fl) used for flow control between links.
ow Control) and error correction code HEC (Head
er Error Control).

FIG. 12 shows an AT for explaining the ATM system.
1 is a schematic configuration diagram of an M network, where 11a and 11b are terminal devices,
Reference numeral 13 denotes an ATM network. The ATM network 13 includes an information network 13a for transmitting data cells and a signal network 13 for transmitting control signals.
b, each ATM exchange 13c- in the information network 13a.
The CPUs 13d-1 to 4d-n of 1 to 13c-n are connected to the signal network 13b. When the originating terminal 11a performs a calling operation for calling the terminating terminal 11b, the ATM exchange (originating exchange) 13c-1 detects the call and detects a calling number (telephone number),
The connection information including the called number and other data is transmitted to the signal network 13b.
To send to. As a result, the signaling network 13b performs call control, and sets the AT to which the called terminal is connected from the originating exchange 13c-1.
The down path to the M exchange (receiving exchange) 13c-n and the relay ATM exchanges 13c-2, 13c-3,... Are determined. When each ATM exchange becomes a call relay station, it determines its own VCI for the call and sends it to the signaling network 13b.
Notifies the subordinate ATM exchange of the VCI of the ATM exchange together with the calling number, called number, and the like.

[0006] The receiving side exchange 13c-n has a calling number, a called number,
Upon receiving the connection information including the VCI of the higher-level ATM exchange, a predetermined VCI is assigned to the receiving terminal and it is checked whether the receiving terminal 11b can talk. If a call is possible, the signaling network 13b notifies the originating exchange 13c-1 while deciding the up path, as in the case of the downlink, to the originating exchange 13c-1, and the originating exchange sends a predetermined VCI to the originating terminal 11a.
Assign. Each ATM switch 13c-1 to 13c on the path
-n is the V of the upper ATM switch for each of the down path and the up path.
(1) connection information for specifying an output path (outgoing highway) of a cell having the VCI,
New VCI added to output cell (own VCI)
Is registered in the built-in routing table.

As described above, the transmitting terminal 11a and the receiving terminal 1
When a path is formed between 1b, both terminals transmit and receive a calling cell and a response cell to each other and confirm the communication procedure. Thereafter, the originating terminal 11a decomposes the data to be transmitted into a predetermined byte length, generates a cell with a header including the allocated VCI, and sends the cell to the ATM network 13. Each of the ATM exchanges 13c-1 to 13c-n receives a cell from a higher-order exchange via a predetermined incoming highway,
VC of the input cell based on the routing table
At the same time, I is sent out to a predetermined outgoing highway.
As a result, the cell output from the calling terminal 11a reaches the terminating exchange 13c-n via the path determined by the call control. The terminating exchange 13c-n changes the VCI added to the input cell to the VCI assigned to the terminating terminal based on the routing table, and then changes the terminating terminal 11b.
To the line to which is connected.

Thereafter, the transmitting terminal 11a sequentially sends the cells to the receiving terminal 11b, and the receiving terminal assembles the information section DT included in the received cell and restores the original data. The above is 1
In the case of one call, by changing the VCI values held at both ends of each line between the terminal and the ATM exchange and between the adjacent ATM exchanges, it is possible to establish logical links corresponding to many calls on one line. And high-speed multiplex communication is thereby realized. According to the ATM system, information of information sources having different transmission speeds such as images, data, and voices can be multiplexed, so that one transmission line can be used effectively, and furthermore, packet switching is performed by software. Such retransmission control and complicated communication procedures are not required, and ultra-high-speed data transmission of 150 Mbps becomes possible.

Also, the ATM exchange has a buffering function. With this buffering function, even when a large number of calls are generated in the ATM exchange or the terminating terminal, the call is accepted and sent to the terminating terminal without waiting for the calling terminal. be able to. For example, if a call is generated from a large number of terminals to the receiving terminal 11b at the same time and the line between the receiving-side exchange 13c-n and the receiving terminal 11b becomes full, cells that cannot be transmitted to the receiving terminal are generated. In such a case, the receiving side exchange 12c-
n buffers the cells that cannot be sent and sends them when the line is free, so that the call can be accepted and sent to the called terminal without waiting for the calling terminal.

FIG. 13 is a block diagram of a self-routing ATM exchange for explaining the buffering function of such an ATM exchange. One basic switching unit SW is shown.
U, control information addition unit CIAU, and call processing CP
It has a U (call control unit) CLP. In this ATM switch, a plurality of paths exist between one input line (input port) and one output line (output port), and a three-stage self-routing switch module exists between each input line and output line. A multi-path multi-stage buffer type ATM communication path configuration. The basic switching unit SWU includes input stage self-routing switch modules SRM _{11 to} SRM ₁₃ ,
Intermediate-stage self-routing switch module SRM _{21 to} S
And RM _23, the output stage self-routing switch module S
RM _{31 to} SRM ₃₃ are provided and have a multi-stage link (three-stage link in FIG. 13). L ₁₁ ~L ₃₃ is the primary link,
M ₁₁ ~M ₃₃ is a secondary link. Input stage module SR
Input of M ₁₁ ~SRM ₁₃ is connected via a control information addition circuit CIAU incoming line (the incoming highways) # 1 to # 9, the output terminal is connected to an intermediate stage module SRM ₂₁ ~SRM _23, an intermediate stage module Each output terminal is an output stage module S
Is connected to the RM ₃₁ ~SRM _33, the output terminal of the output stage module is connected to the output lines (output highways) # 1 to # 9.

The control information adding unit CIAU includes additional circuits AC1 to AC9 for adding routing information and the like corresponding to the respective input lines # 1 to # 9.
Numeral 9 adds a routing header (described later) to a cell input from a corresponding incoming line, and a VCI included in the cell.
And sends it out to the basic switching unit SWU. When a call is originated, the call control unit CLP performs call control to control the V
In addition to determining the CI, a routing header is determined according to the location of the called terminal, and the control information (routing header or VCI) is stored in a routing table (not shown) of an additional circuit to which a cell corresponding to the call is input. Write. still,
The additional circuit to which the cell is input is known from information notified at the time of call control from the upper ATM switch. Further, the determined control information (routing header or VCI) is stored in the upper ATM.
The data is written in the routing table in correspondence with the VCI of the exchange. The routing header RH includes three pieces of routing information R.
H ₁ has a ～RH _3, routing information RH ₁ primary link number, i.e. indicates the output number of the input stage modules, routing information RH ₂ is the secondary link number, that is, the output end of the intermediate-stage module It indicates the number, routing information RH ₃ shows outgoing line number, i.e., an output terminal number of the output stage.

After the call control is completed, when a cell is input to a predetermined incoming line via the higher-level ATM exchange, the additional circuits AC1 to AC9 connected to the incoming line switch the VCI added to the input cell from the routing table. Control information (routing header RH and VCI) corresponding to. Then, the routing header is added to the cell, and the VCI of the cell is replaced with the read VCI and sent to the basic switching unit SWU. FIG. 14 is a format example of information output from each of the additional circuits AC1 to AC9. The module SRMij in each stage uses the routing header RHi to guide the cell to a corresponding link, that is, a predetermined output terminal, and finally sends the cell from a predetermined output line. Before sending to the outgoing line, the routing header is removed by a post-processing circuit (not shown).

FIG. 15 is a circuit diagram showing a specific example of a self-routing switch module (SRM). I _{1 to} I ₃ are control information detection circuits, D _{1 to} D ₃ are transmission information delay circuits, DM
_{1 to} DM ₃ are demultiplexers, and DEC _{1 to} DEC ₃ are control information decoding circuits.
An LD is configured. FM _{11 to} FM ₃₃ are buffer memories, for example, FIFO (First-In First-Out) memories, SEL ₁
To SEL ₃ selectors, AOM ₁ ~AOM ₃ is arrival order management FIFO. Each arrival order management FIFO (AOM ₁
To AOM ₃ ) are control information decode circuits DEC ₁ to DEC _1, respectively.
Is connected to the output end of the DEC _3, corresponding three buffer memories FM ₁₁ ~FM _{13 to, FM 21 ~FM 23, FM 31} ~FM
₃₃ stores the order in which cells arrive, and stores a corresponding selector S
By controlling EL _{1 to} SEL ₃ , the cells are read from the three buffer memories in the order of arrival of the cells and transmitted to outgoing lines # 1 to # 3. Figure 16 is a simplified representation view of a self-routing switch modules, the buffer memory FM ₁₁ ~FMmm on the intersection of the input link and m number of output links of the m have been placed, self-routing switch module of FIG. 15 is a dotted line Corresponds to the part enclosed by.

Transmission information entering the input terminals # 1 to # 3 is shown in FIG.
And the detection circuit Ii (i = 1 to 1)
3) extracts the control information contained in this signal and sends it to the decoding circuit DECi (i = 1 to 3). The control information includes the input stage routing header RH1 and the intermediate stage routing header RH.
2. Since it has the output stage routing header RH3, the detection circuit Ii detects the corresponding routing information RH1 to RH3 according to the order of the self-routing switch module SRM and decodes it by the decoding circuit DECi.
To enter.

[0015] The decoding circuit DECi receives the input route.
The output information indicates output terminal #j (j = 1 to 3)
For example, the demultiplexer DMi is operated by the switching signal Si.
Then, the transmission information is sent to the FIFO memory FMji. For example,
The routing information included in the information input from power terminal # 1 is
If it indicates the output terminal # 2, the decoding circuit DEC ₁
Is the demultiplexer DM₁To operate from input terminal # 1
Information FM_{twenty one}To enter. Arrival Order Management FIFO (AO
Mi) is a control information decode circuit DEC₁~ DEC_ThreeOutput
Three corresponding buffer memories FMi connected to the ends₁~
FMi_ThreeThe order in which cells arrive. For example, cell
Is the buffer memory FM₁₁→ FM₁₂→ FM₁₃→ FM₁₂→ ・
.. If the arrivals are in the order of, the arrival order management FIFO (AO
M₁) Is the order of cell arrival, such as 1 → 2 → 3 → 2 → ...
Stores the buffer memory identification code. After a while
The arrival order management FIFO (AOMi) has a corresponding selector S
By controlling ELi, three buffer memories F
Mi₁~ FMi_ThreeRead from cell and send to outgoing line #i
You.

By providing the FIFO memory FMij with a capacity of a plurality of cells, a buffer function can be obtained, and it is possible to sufficiently cope with a case where transmission data temporarily increases. Further, retained cell equivalents number to each buffer memory FMi ₁ ~FMi ₃ for reading a cell from the buffer memory FMi ₁ ~FMi ₃ in order cell arrives, the situation is eliminated cells are discarded overflow from the buffer memory. The above is the case of a multi-path multi-stage buffer type ATM communication path, but when the number of incoming lines and outgoing lines is small, FIG.
One, as shown in 7 self-routing switch module SRM ₁ may be constituted the basic switching unit SWU. Also, as shown in FIG. 18, a plurality of (two-stage in FIG. 18) switch modules SRM ₁ ,
Single path multi-stage buffer type ATM in which switch unit SWU is configured by connecting SRM ₂ in series
It can be a communication channel.

In the above-described ATM exchange, an active system (Act system) and a standby system (Sb) are used to improve reliability.
(y system), and when a failure occurs in the current operation system, the current standby system is immediately switched to the operation system to improve the service. By the way, even if a failure occurs while the currently operating system is operating for a long time and the system is switched to the standby system, it is not known whether the standby system normally operates. Therefore, periodically switch from the active system to the standby system and from the standby system to the active system,
After confirming that both systems are operating normally, the system switches to the standby system when a failure occurs. In this way, it is possible to prevent the communication system from going down due to the malfunction of the standby system when a failure occurs. It should be noted that periodic system switching is performed about once a day to check whether or not the standby system operates normally. If the standby system does not operate normally, the system is returned to the original state and the malfunction of the standby system is corrected.

Such system switching must be performed without interruption. That is, the ATM exchange stores the ATM cells by the buffering function as described above. If the operation state of the active system and the standby system is suddenly switched, the ATM cells staying in the ATM exchange are lost ( Cell discard). A
End-to-end 1 as service condition of TM network
The cell must be discarded in the order of / 10 ¹¹ to 1/10 ⁶ . For this reason, if cell loss occurs due to periodic system switching, the service conditions will not be satisfied. Therefore, it is necessary to perform system switching without instantaneous interruption, in other words, without discarding cells. From the above, a system switching method for performing system switching without an instantaneous interruption has been proposed.

FIG. 19 is a schematic configuration diagram of an ATM communication path of one of the systems in the proposed system switching system, and is constituted by a single-stage ATM switch. FIG. 20 is an explanatory diagram of the proposed system switching method. In FIG. 19, M
LP is a multiplexing unit, and DBF1 to DBFm are outgoing buffers. The multiplexing unit MLP multiplexes the cells of the speed v going to the output lines # 1 to #m, stores the multiplexed cells at the speed of mV in the output buffers DBF1 to DBFm provided for the respective output lines, and reads the cells at the speed V from the output buffers. To the corresponding outgoing lines # 1 to #m. In FIG. 20, ATPT0 and ATPT1 are the active and standby ATM communication paths shown in FIG. 19, and only the output buffer DBFi of the output line #i is shown. SSW is a system switching unit for switching between the standby system and the active system, SCC is a system switching instruction unit for instructing system switching, and EMN is an output buffer D.
An empty monitoring unit that monitors that BFi is empty.

When there is a switching instruction from the system switching instruction unit SCC, all the outgoing buffers DBF1 to DBFm of the current standby ATM communication path ATPT1 are emptied. For example, all outgoing buffers are cleared by buffer clear means (not shown). Next, the cell input to the currently operating ATM communication path ATPT0 is stopped, and the current standby ATM communication path ATPT0 is stopped.
Input cells only to PT1. The system switching unit SSW validates the output from the current operation system, selects the cell from the current operation system, and outputs the selected cell to each output line. The current standby ATM communication path ATPT1 stores the input cell in each output buffer DBF.
1 to DBFm. Outgoing buffer DBFi corresponding to outgoing line #i of the current operation system
When all the cells staying in the cell are output, the empty monitoring unit E
MN outputs a system switching signal. As a result, the system switching unit SSW selects a cell from the output buffer DBFi of the current standby ATM communication path ATPT1 and outputs it to the output line #i. Thereafter, similarly, every time all the cells staying in each output buffer are output, the system switching signal is output and the system is switched to the standby system, and the cells finally output to all the outgoing lines are output from the standby system. The system is switched to the cell, and the system is switched without any instantaneous interruption.

According to this switching method for each output buffer, it is not necessary to redundantly prepare the buffer length in order to absorb the variation in the number of cells staying between the output buffers.
Excellent with no hard increment. In the case where switching is performed not for each outgoing line but for all outgoing lines at once, a double buffer length is required, which is excellent in this respect. This method can also be applied to a common buffer type ATM communication path in which the output buffer of each output line is shared as shown in FIG. In FIG. 21, MLP is a multiplexing unit, CMM is a common buffer memory, and DMPX is a demultiplexing unit.
A system confounding point (switching point between the active system and the standby system) is provided at a point before multiplexing each input link and a point at which the output is multiplexed and demultiplexed. After confirming that all data has been read from the operating system, the output selection logic is changed on the receiving side. The fact that the number of storage cells for each output route has become 0 means that the contents of a FIFO (not shown) that manages the use address of the common buffer memory CMM for each output route have become 0. Easy to check.

[0022]

However, in the proposed system switching method, the input to the active system is stopped and cells are input only to the standby system. Switch. For this reason, if the standby system does not operate normally when switching to the standby system, switching to the original operating system causes cell discarding, and the service conditions (cell loss rate) of the ATM network cannot be satisfied, resulting in a decrease in service. There is a problem to come.

Although the proposed system switching method can be applied to switching of an ATM communication path using a single-stage ATM switch, there is a problem that it cannot be applied to a multi-path multi-stage buffer type ATM communication path. This is because when applying to a multi-path multi-stage buffer type ATM communication path, system crossover points are needed before and after each ATM switch, the number of system crossover points increases, hardware such as selectors increases, and both systems increase. This is because the input link and output link of each ATM switch intersect, and control / management becomes complicated, making implementation impossible. Also, the proposed system switching method is a multi-path multi-stage buffer type A, even in a single-path multi-stage buffer type ATM call, when the number of ATM switches increases.
The same problem as in the case of the TM communication path occurs. Furthermore, even if the proposed system switching method is one-stage, there is a problem that it cannot be applied to an ATM communication path having an ATM-specific shaping function. Hereinafter, this point will be described in detail.

FIG. 22 shows an ATM communication path in which the ATM switch (ATPT) shown in FIG. 19 is provided in the first stage and a VP shaper (VSH) having a shaping function is provided in the second stage. Although only the outgoing line # 1 is shown for the VP shaper, the same VP shaper is provided for other outgoing lines.
The VP shaper uses a bandwidth V (for example, 150M) of one transmission path.
b / s) is set in advance for each VPI, and cells are transmitted to the transmission path so as to be within the used band. By managing the bandwidth used for the transmission path for each VPI, a specific V
Most of the bandwidth of the transmission path is occupied by the PI and other VPI
Can be prevented from being unable to be transmitted.

In the VP shaper, VPDV is VPI
A VP distribution unit that distributes cells every time, and FB1 to FBn are V
A FIFO buffer provided for each PI, SEL is a selector, and SCD is a scheduler that reads cells from each buffer according to a preset schedule and sends out the cells to the outgoing line (transmission line) # 1. When the scheduler divides the transmission path into 128 cell slots in one cycle, it is preset in each of the cell slots S _{1 to} S ₁₂₈ which cell from which buffer is to be called, and for each of the 128 cell slots, The cell is read from a predetermined buffer and transmitted to the transmission path, and this operation is performed cyclically. Thereby, the use bands V1, V2,... Vn (V ≧ V1 +
V2 +... + Vn).

In the ATM communication path having such a VP shaper, there is not a confounding point at the exit of each buffer for each VPI, but a system switching point after multiplexing at a speed V, and all buffers FB1 of the VP shaper To FBn are performed simultaneously. Therefore, if there is a system switchover instruction,
Input cells must be stored in the buffer of the standby shaper until all buffers of the active shaper become empty. The number of storage cells depends on the most time-consuming one of the currently operating system.

It is not necessary to rescue the cells discarded when the system switching is not performed by the standby system at the time of system switching. It can happen. For example, V = 150 Mb / s, V1 = 10 Mb / s, Q1 = 100 (Q is the number of staying cells), V2 = 140 Mb / s, Q2 = 0, and then cells are continuously transferred to the buffer FB2 at 140 Mb / s. Shall arrive. If the operation system is passed without performing system switching, all cells to the buffer FB2 are naturally transmitted to the transmission line # 1 via the buffer. However, when the system switching is activated, V2 · Q1 / V1 = 1400 cells arrive in the standby system until the buffer FB1 becomes empty. In order to absorb this, it is necessary to prepare a very long buffer, and the amount of hardware becomes too large. In other words, the proposed system switching method is ATM
It cannot be applied to a VP shaper having a unique shaping function.

Accordingly, an object of the present invention is to provide a system switching method for an ATM switch which does not need to provide a redundant buffer amount. Another object of the present invention is to provide a system switching method for an ATM switch which can be applied to a multi-stage buffer type ATM communication path without increasing the number of system confounding points. Yet another object of the present invention is to provide an A
It is an object of the present invention to provide a method for switching a system of an ATM exchange applicable to a TM communication path. Another object of the present invention is that cell discard does not occur even when the system switching is stopped, and therefore cell discard occurs even when the standby system is found to be not operating normally and is returned to the original state. The purpose of the present invention is to provide an ATM switching system switching method . Still another object of the present invention is to provide a system switching method for an ATM exchange in which system switching may be performed for each outgoing line (output link) or system switching may be performed simultaneously for all outgoing lines. That is.

[0029]

FIG. 1 is a diagram for explaining the principle of the present invention, and has a duplex configuration in which two identical ATM communication paths are arranged in parallel. In FIG. 1A, reference numeral 51 denotes an active ATM communication path, FM denotes one buffer (corresponding to the outgoing line #i) in the active ATM communication path, 51 '
Is a standby ATM communication path, FM 'is one buffer in the standby ATM communication path, 52 is a vacancy monitoring unit that monitors that the working buffer is vacant, and 53 is a cell from a predetermined buffer. This is a system switching unit that outputs.

In FIG. 1B, reference numeral 61 denotes an active ATM.
The communication path and FMi (i = 1, 2,...) Are the active ATs
One buffer in the M channel, 61 'is the standby A
The TM communication path, FMi 'is one buffer in the standby ATM communication path, and 62 is a continuous free space monitoring for monitoring that the last stage buffer of the working system becomes free (N-1) times. And 63, a system switching unit. In FIG. 1C, reference numeral 71 denotes an active ATM communication path, and FMi (i = 1,
(2,...) Is one buffer in the active ATM communication path, 71 'is a standby ATM communication path, FMi' is one buffer in the standby ATM communication path, and 72 is a buffer at each stage of the active ATM communication path. Each stage vacancy monitoring unit that monitors that the vacancy has become vacant, and 73 is a system switching unit.

[0031]

According to the system switching request, all buffers of the current standby system 51 'are emptied once, and then the input cells are multicast to the current active system 51 and the current standby system 51' to add the same cell flow to both systems. The reading is performed in the same manner in both systems, and the selector 53 outputs each output line #i (i = 1, 2,.
Continue to select cells from the active system as output to m). The vacancy monitoring unit 52 monitors, for each outgoing line #i, the vacancy of the buffer of the active system connected to the outgoing line #i, and all buffers connected to the predetermined outgoing line #i When the line becomes empty even once, the contents of all buffers connected to the outgoing line #i of both systems match, so the selector 53 selects a cell from the current standby system for the outgoing line. This makes it possible to switch the system for transmitting cells to the outgoing line #i from the current operation system to the current standby system without any instantaneous interruption. After that, similarly for other outgoing lines, the vacancy of all buffers of the current working system is checked at least once, and then a cell is switched from the current working system to the current working system by selecting a cell from the current working system. I do. Rather than performing system switching for each output line as described above, after all buffers have been checked once for buffer availability, cells from the current standby system are output collectively to all output lines. Then, the system operated from the operation system to the standby system can be switched at once for all outgoing lines. In this way, even if there is a system switching instruction, the same cell flow is applied to both systems, and it is confirmed that the cells of both systems are completely identical due to the empty buffer of the active system. And the standby system are switched, so it is not only possible to switch the system without any instantaneous interruption without providing the buffer amount redundantly, but also to suspend the system switch after the system switch request occurs and maintain the current active system. Therefore, even when it is determined that the standby system does not operate normally after the occurrence of the system switching request, even if the system is operated in the original state, cell discard does not occur, and the reliability of operation can be improved.

A single-path multi-stage buffer type AT in which N stages of buffers are connected in tandem between an input line and an output line, and there is only one path connecting a certain input / output line.
In the case of the M communication path (FIG. 1 (b)), the continuous idle monitoring unit 62 determines that the buffer FM _N of the last-stage switch module has a period corresponding to the time during which cells are transferred from the first-stage switch module to the last-stage switch module. , And continuously monitors whether or not cells are vacant. If the vacancies are continuously vacant, cells from the current standby system are selected and output to the outgoing line #i. This is because if the buffer at the last stage becomes empty during the period, the contents of the buffers of the active system and the standby system related to the outgoing line #i thereafter match. As described above, even in the case of the single-path multi-stage buffer type ATM communication path, the system can be switched without any instantaneous interruption, and even if the system switching is stopped, no cell discard occurs. Even if it returns to the original state at the time when it is determined that it is not operating, cell discard does not occur, and service can be improved. Further, in this method, system switching can be realized with a simple hardware configuration without increasing the number of system confounding points.

Further, in the case of a single-path multi-stage buffer type ATM communication path in which a plurality of buffers are provided between an incoming line and an outgoing line (see FIG. 1 (c)), each stage empty monitoring unit 72 determines that the preceding buffer is empty. performs a free check operation of the next stage of the buffer after determining that it is now, when the free buffer FM _N of the last stage was confirmed in the same manner thereafter, select the cell from the current standby system outgoing line # Output to i. In this way, since the contents of the operation-stage and standby-system buffers related to the outgoing line #i thereafter match, the single-path multi-stage buffer type AT
Even in the case of M communication path, system switching can be performed without instantaneous interruption,
Moreover, even if the system switching is stopped, cell discard does not occur,
Therefore, even if it is determined that the standby system is not operating normally, the cell is not discarded even if the state is returned to the original state, and the service can be improved. Further, according to this method, the system switching points can be realized with a simple hardware configuration without increasing the number of system confounding points, and can also be applied to the system switching of an ATM communication path equipped with a VP shaper.

Further, when this system is developed, a plurality of paths exist between a certain incoming line and a certain outgoing line, and a multi-path multi-stage buffer type ATM communication path in which a plurality of buffered switch modules exist between each incoming and outgoing line. System switching. In other words, for each of the output links of all the previous switch modules connected to a certain output link,
Monitors the vacancy of the buffer sharing the output link of the previous stage, and when the simultaneous vacancy of the buffer in the output link of the previous stage is confirmed, the output link is shared for all output links of all switch modules of the next stage. The operation of monitoring the free space of the buffer in the last stage is started, and thereafter, for each of all output links (outgoing lines) of all the switch modules in the last stage, the free space of the buffer in the last stage sharing the outgoing line is monitored. When the buffers sharing a given outgoing line are simultaneously vacant, select and output the cell from the current standby system for the outgoing line, and confirm the simultaneous vacancy of the buffer for each outgoing line. Select and output the cell from the current standby system to switch the operating state between the active system and the standby system.

In this case, when it is confirmed that the buffers are simultaneously vacant for each of the outgoing lines, cells from the current standby system are selected and output to all the outgoing lines at once, and the operating states of the active system and the standby system are determined. Can be switched. Also, multi-path 3
In the case of the stage buffer type ATM path, instead of monitoring that the buffers sharing the output link of the first stage are simultaneously vacant, the output link of the first stage (the input link of the second stage) is used. It can be replaced by monitoring whether all the buffers in the second stage to be connected are simultaneously free.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (a) Outline of the present invention Before describing the present invention in detail, its outline will be described with reference to FIG. Overview of the first embodiment (refer to FIG. 1A) All buffers of the current standby system 51 'are emptied once in response to a system switching request, and then the current active system 51 and the current standby system 51'.
In addition to multicasting the input cell to add the same cell flow to both systems, reading is performed in the same manner in both systems,
The selector 53 continues to select a cell from the currently operating system as an output to each outgoing line #i (i = 1, 2,... M). Since the same number of cells are input to the current active system and the current standby system thereafter and are read out in the same pattern, the number of stagnated cells in the buffer of the active system always exceeds the number of stagnated cells in the current standby system. . In other words, the number of cells staying in the buffer of the active system should increase by the number of cells already stored in the active system when the system switching request occurs. Therefore, if the number of stagnant cells in the buffer of the active system becomes 0 at a certain point in time, the number of stagnant cells in the buffer of the current standby system also becomes zero. Is stored. At this time, even if the output is changed from the current operating system to the current standby system by the selector 53, the system can be switched without discarding the cells.

Therefore, the vacancy monitoring unit 52 sets, for each outgoing line #i,
It monitors the availability of buffers of the active system connected to the outgoing line #i, and when all buffers connected to the outgoing line #i become free at least once, the outgoing lines #i of both systems are monitored. Since the contents of all buffers to be connected match, the selector 53 selects a cell from the current standby system for the outgoing line. This makes it possible to switch the system for transmitting cells to the outgoing line #i from the current operation system to the current standby system without any instantaneous interruption. Since then
Similarly, for other outgoing lines, after confirming at least once that all the buffers of the current working system are empty, a cell from the current working system is selected to switch the working system from the current working system to the current standby system. .
In addition, instead of performing system switching for each outgoing line as described above,
After the buffer vacancy is confirmed once for all outgoing lines, cells from the current standby system are output to all outgoing lines at once, and the system that operates from the working system to the standby system is batched for all outgoing lines. You can also switch.

As described above, even if there is a system switching instruction, the same cell flow is applied to both systems, and it is confirmed that the cells of both systems are completely the same due to the empty buffer of the working system.
After that, the system is switched between the active system and the standby system. It may be maintained, therefore, even if it is found that the standby system is not operating normally after the occurrence of the system switching request, the cell is not discarded even when operated in the original state,
Operational reliability can be improved.

Outline of the second embodiment (see FIG. 1 (b)) N stages of buffers are connected in tandem between an input line and an output line, and there is only one path connecting a certain input / output line. In the case of a single-path multi-stage buffer type ATM communication path that only exists,
The continuous empty monitoring unit 62 monitors whether the buffer FM _N of the last-stage switch module has been continuously empty for a predetermined period, and if it has been continuously empty, selects a cell from the current standby system and sets the outgoing line #. Output to i. The predetermined period is a period corresponding to the time required for transferring cells from the first-stage switch module to the last-stage switch module. When there is only one buffer between the input and output lines: only one stage of the buffer passes between a certain input and output line, and
When there is only one path connecting the input and output lines, the buffer of the current standby system is vacated once, the same cell is input to the buffers of both systems, and the cells are read from the buffers of both systems at the same timing. Then, the number of cells stored in the buffer of the current working system is always the same as or larger than that of the current working system. For this reason, when the buffer of the currently operating system becomes empty, the statuses of the buffers of both systems thereafter completely match, and thereafter the system can be switched without discarding cells.

When the buffers are connected in N-stage cascade between the input and output lines: When the buffers are connected in N-stage cascade between certain input and output lines, even if one buffer of the currently operating system is used. However, just because the file becomes empty does not mean that the other buffers in the active system are also empty. In other words, even if one buffer of the current operation system becomes empty, the staying cells of all buffers between the input / output lines of the current operation system / current protection system are not exactly the same. , The system is not switched without cell discard. But,
Even if the buffers are connected in cascade N stages,
If there is only one route between the outgoing lines, the last stage (N-th stage) of the current operation system is used for a period corresponding to the time required for the cells staying in the first stage buffer to reach the last stage. If the buffers are continuously vacant, all the buffers of the active system in the path between the input and output lines are vacant. That is, during the above-mentioned period, if the vacancy of the buffer at the last stage is continuously confirmed, the number of storage cells of the current operation system / current protection system thereafter completely matches.

For example, assuming that the read speed of the link between the buffers connecting the multi-stage buffers is equal to the output speed and that cells are sent to the next buffer as long as the link is free, one read of the output line is performed. If the last stage buffer is empty for the time, the buffer immediately before the last stage becomes empty, and if the buffer is empty for two readout times of the outgoing line, the buffer immediately before and the last stage for the last stage is empty. Becomes empty, and so on. If the buffer at the last stage is empty for the N cell read time, all buffers between the input and output lines of the currently operating system become empty, and thereafter, the buffers of both systems become empty. Match. As described above, even in the case of the single-path multi-stage buffer type ATM communication path, the system can be switched without any instantaneous interruption, and even if the system switching is stopped, no cell discard occurs. Even if it returns to the original state when it is found that it is not operating, cell discard does not occur,
Service can be improved. Further, in this method, system switching can be realized with a simple hardware configuration without increasing the number of system confounding points.

Outline of Third Embodiment (See FIG. 1 (c)) Another non-stop switching method in the case of a single-path multi-stage buffer type ATM communication path in which a plurality of buffers are provided between an incoming line and an outgoing line. Will be described. In FIG. 1 (c), if the buffer of the first stage of the active system once becomes empty, the state of the buffers of the first stage of the active system and the standby system is completely restored thereafter as described above. Therefore, the output cell flows also match. That is, the cell flows applied to the second-stage buffer coincide. Therefore, the buffer of the second stage of the current operation system is monitored thereafter, and if the buffer becomes empty, the state of the buffer and the output cell flow of the second stage of the current operation system and the second stage of the current standby system thereafter match. Can be determined. This is continued to the last stage buffer, and if it can be confirmed that the last stage buffer of the current operation system is empty, thereafter, the buffer storage cells of the current operation system / current standby system and the output cell flow coincide. That is, cell discard does not occur even when the system is switched.

[0043] Accordingly, each stage free monitoring unit 72 performs the idle confirmation operation of the next stage of the buffer after determining that the preceding buffer is empty, the empty buffer FM _N of the last stage in the same manner thereafter When confirmed, the cell from the current standby system is selected and output to the outgoing line #i. In this way, since the contents of the operation-stage and standby-system buffers related to the outgoing line #i thereafter match, the single-path multi-stage buffer type AT
Even in the case of M communication path, system switching can be performed without instantaneous interruption,
Moreover, even if the system switching is stopped, cell discard does not occur,
Therefore, even if it is determined that the standby system is not operating normally, the cell is not discarded even if the state is returned to the original state, and the service can be improved. Further, according to this method, the system switching points can be realized with a simple hardware configuration without increasing the number of system confounding points, and can also be applied to the system switching of an ATM communication path equipped with a VP shaper.

Outline of the Fourth Embodiment When the third embodiment is developed, a plurality of paths exist between a certain input line and a certain output line, and a plurality of stages of buffered switch modules exist between each input and output line. The present invention is also applicable to system switching of a multi-path multi-stage buffer type ATM communication path. In a multi-path multi-stage buffer type ATM communication path, when one output link with a certain stage is connected to several switch modules in the preceding stage, the currently operating system connected to the output link of the certain stage It is meaningless to monitor the empty buffer unless it is executed under the condition that the cell flow to the input link of the certain stage matches the current operation system and the current standby system. This condition can be checked by monitoring the status of all buffers of the active system at the preceding stage connected to each input link. That is, if each input link is connected to a plurality of buffers in the preceding module, the simultaneous availability of all buffers in the active system is checked independently for each input link. If the simultaneous availability of all buffers of the active system can be confirmed for each input link, the cell flows of the input link from the preceding stage coincide between the active system and the current standby system. Under these conditions, if all the buffers connected to the output link become empty at the same time, the cell flows of the output link (input link at the next stage) will be completely the same in both systems.

As described above, for each input link (previous stage output link) of all the switch modules in a certain stage, the simultaneous vacancy of all previous stage buffers connected to the input link is monitored, and for all the input links, When it is confirmed that all the buffers connected to the input link of the same stage are simultaneously vacant, the operation of monitoring the vacancy of all the buffers connected to the respective input links is performed for all the input links of all the switch modules in the next stage, and so on. Then, for all output links (outgoing lines) of all switch modules in the last stage, the availability of all buffers connected to each outgoing line is monitored, and all buffers connected to a predetermined outgoing line are simultaneously vacant. , The cell from the current standby system is selected and output for the outgoing line, and similarly, for each outgoing line, the simultaneous availability of all buffers is confirmed. Switching the operational state of the operating system and the protection system by selecting the cell from the current reserve system by. In this case, when simultaneous availability of the buffer is confirmed for each of all outgoing lines at the last stage, cells from the current standby system are selected and output to all outgoing lines at once, and the operating status of the active and standby systems is checked. Can be switched.

(B) First Embodiment of the Present Invention FIG. 2 is a schematic explanatory view of a first embodiment of the present invention, in which only buffers corresponding to one outgoing line are shown. 51
Is an active ATM communication path, and 51 'is a standby ATM communication path, each having a self-routing switch module configuration shown in FIG. 15, for example. FMi, FM
i 'is a buffer expressing all the buffers FMi1 to FMim (see FIG. 15) sharing the outgoing line i (i = 1, 2,... m), and 52 is that the working buffer FMi becomes empty. An empty monitoring unit 53 for monitoring, a system switching unit 53 for outputting cells from a predetermined buffer, and a system switching control unit 54 for outputting a system switching signal SCH periodically or when a failure occurs in the active system.

The system switching control unit 54 issues a system switching instruction signal S
When a CH occurs, the current standby system 51 'empties all buffers by clear means (not shown). Thereafter, the input cells from the incoming lines # 1 to #m are multicast to the current operating system 51 and the current standby system 51 'to add the same cell flow to both systems, and the reading is performed in the same manner in both systems. Also, first, the system switching unit 53 outputs each outgoing line #i (i
= 1, 2,... M) from the active system. The vacancy monitoring unit 52 uses the system switching instruction signal SCH to output the buffer FM sharing the outgoing line for each outgoing line #i of the currently operating system.
i (buffers FMi1 to FMim in FIG. 15) is monitored for availability.

Then, when all the buffers sharing the predetermined outgoing line #i become empty at least once, the contents of the buffers FMi and FMi 'of the currently operating system and the standby system become identical thereafter. . Therefore, the empty monitoring unit 52 inputs the system switching enable signal CEN to the system switching unit 53. As a result, the system switching unit 53 selects and outputs a cell from the current standby system for the outgoing line # 1. Similarly, for the other outgoing lines, the cells from the current standby system are selected and output by confirming the availability of all the buffers sharing the outgoing line, and the operating state of the active system and the standby system is switched. Thus, the switching from the active system to the standby system and the standby system to the active system are completed. When it is confirmed that the buffers FM1 to FMm are simultaneously vacant for all the outgoing lines (# 1 to #m), the cells from the current standby system are collectively selected for all the outgoing lines # 1 to #m. It is also possible to output and switch the operation state between the active system and the standby system.

FIG. 3 is a block diagram of a first embodiment of the present invention, and the same parts as those of FIG. 2 are denoted by the same reference numerals. Reference numeral 51 denotes an active ATM communication path, and reference numeral 51 'denotes a standby ATM communication path, each having a self-routing switch module configuration. 52 is an empty monitoring unit, 53 is a system switching unit,
54 is a system switching control unit. In the ATM communication path 51, CELD is a cell distribution unit that distributes cells input from each of the incoming lines # 1 to #m to buffers of each of the outgoing lines # 1 to #m based on a routing header. Detection circuits I _{1 to} Im, transmission information delay circuits D _{1 to} Dm, demultiplexers DM _{1 to} DMm, control information decoding circuit D
It is composed of EC ₁ ~DECm. FMi1 to FMim are buffers connected to outgoing line #i, SELi is a selector, A
OMi is an arrival order management FIFO.

Normally, the cell distribution unit CEL of the operation system 51
D distributes cells input from incoming lines # 1 to #m to a predetermined buffer based on the routing header. For example, routing information contained in the information input from the input terminal # 1 as long as it exhibits an output terminal # 2, the cell distributing unit CELD inputs the cell to the buffer FM _21. The arrival order management FIFO (AOMi) is connected to the cell distributing unit, and the m buffer memories FMi1 to FMi1 to
The order in which cells arrived is stored in FMim. For example, if the cell is a buffer memory FMi1 → FMi2 → FMim → FMi1 →
.. If they arrive in the order of, the arrival order management FIFO (AO
In Mi), buffer memory identification codes are stored in the order of cell arrival, such as 1 → 2 → m → 1 →. Accordingly, since the arrival order management FIFO (AOMi) corresponding to the outgoing line #i becomes empty, it can be determined that all the buffers sharing the outgoing line #i become empty at the same time.

Thereafter, the arrival order management FIFO (AOM)
i) controls the corresponding selector SELi to read out the cells from the m buffer memories FMi1 to FMim in the order of arrival of the cells, and sends them out to the outgoing line #i via the system switching unit 53. In this state, when a system switching instruction is issued from the system switching control unit 54, the current standby system 51 'empties all buffers by clear means (not shown). Thereafter, the input cells from the incoming lines # 1 to #m are multicast to the current operating system 51 and the current standby system 51 'to add the same cell flow to both systems, and the reading is performed in the same manner in both systems. First, the system switching unit 5
3 selects a cell from the currently operating system as an output to each outgoing line #i (i = 1, 2,... M).

The vacancy monitoring unit 52 uses the system switching instruction signal SCH to output an arrival order management FIFO for each outgoing line #i of the currently operating system.
It monitors whether the content of (AOMi) is empty. Then, the arrival order management FIFO (A
When the contents of OMi) become empty, that is, outgoing line #i
When all the buffers FMi1 to FMim sharing the same buffer become free at the same time, the buffers FM1 of the current working system and the backup system
The contents of i and FMi 'match. Therefore, the empty monitoring unit 52 sends the system switching enable signal C to the system switching unit 53.
Enter EN. Thereby, the system switching unit 53 outputs the outgoing line # 1.
Thereafter, the cell from the current standby system is selected and output.
Similarly, by checking the availability of the arrival order management FIFO for the other outgoing lines (simultaneous emptyness of all buffers sharing the outgoing line), the cell from the current standby system is selected and output, and the active system and the standby system are output. Switch the operation status. Thus, the switching from the active system to the standby system and the standby system to the active system are completed.

(C) Configuration of the Second Embodiment of the Present Invention FIG. 4 is a configuration diagram of the second embodiment of the present invention. This is an example in which the present invention is applied to a multi-stage buffer type ATM communication path.

Reference numerals 61 and 61 'denote an active system and a standby system single path multistage buffer type ATM communication path, respectively, SRMi,
SRMi '(i = 1, 2,... N) is, for example, a self-routing switch module shown in FIG.
The buffers sharing a predetermined output link for each switch module SRMi, SRMi ', 62 monitoring that the buffer FM _N in the switch module SRM _N of the operational final stage becomes to (N-1) times the free Continuous A continuous idle monitoring unit 63, a system switching unit 63, and a system switching control unit 64. Although only one input link and one output link of each switch module SRMi, SRMi 'are shown, there are m input links and m output links, and the output link of the preceding stage is connected to the predetermined input link of the next stage. Have been. In the following description, it is assumed that the output link #j in the preceding stage is connected to the input link #j in the next stage.

The condition matching condition in the active system and the standby system
Consideration In a single-path multi-stage buffer type ATM communication path,
Even if all buffers connected to the last output line #j of the current operation system become empty, cells (cells destined for the output line #j) are stored in the buffer connected to the output link #j of the previous stage. There is no guarantee that the state (the number of staying cells) of the active system and the standby system is exactly the same at that time. Therefore, in such a single-path multi-stage buffer type ATM communication path, a condition in which the state of each stage buffer related to the outgoing line #j of the active system and the standby system matches will be considered.

As long as cells are stored in the preceding buffer, the staying cells are read-accessed to the preceding buffer so as to arrive at the succeeding buffer in the next cell time. The empty buffer means the empty buffer in the preceding stage at the present time. Similarly, when the buffer in the subsequent stage becomes empty during the two cell time, it means that the buffer in the previous stage and the buffer in the preceding stage at the present time are empty.
Similarly, during the (N-1) cell time, the fact that the buffer at the subsequent stage becomes empty means that all the buffers are empty at the present time. That is, when N stages of buffers that are read and written at the same speed are arranged in a line, the last stage buffer is (N-
1) If the vacancy continues continuously, it can be determined that cells for the outgoing line #j are not staying in all the buffers in the preceding stage, and thereafter, each stage of the active system and the standby system related to the outgoing line #j The contents of all buffers in

When the system switching instruction signal SCH is generated from the operation system switching control section 64, the current standby system 61 'empties all buffers in all stages by clear means (not shown). Thereafter, the input cells from the incoming lines # 1 to #m are multicast to the current operating system 61 and the current standby system 61 'so that the same cell flow is added to both systems, and reading is performed in the same manner in both systems. Also, first, the system switching unit 63 outputs each outgoing line #j (j
= 1, 2,... M) from the active system. The continuous empty monitoring unit 62 is a switch module S in the last stage.
All buffers FM _N coupled to outgoing line j of RM _N are (N−1)
During the cell transfer timings, it is continuously monitored whether or not the cell becomes empty.

When all the buffers sharing the predetermined outgoing line #j are simultaneously vacant, thereafter, for the outgoing line j, all the buffers FMi and F of all stages of the current operation system and the standby system are used.
The contents of Mi '(i = 1, 2,... N) match. Therefore, the continuous idle monitoring unit 62 inputs the system switching enable signal CEN to the system switching unit 63. Thereby, the system switching unit 6
Reference numeral 3 thereafter selects and outputs cells from the current standby system for the outgoing line #j. Similarly, by confirming (N-1) consecutive simultaneous vacancies of all buffers in the last stage sharing the outgoing line with other outgoing lines, cells from the current standby system are selected and output, and the cells are output to the active system. The operation status of the standby system is switched. Thus, the switching from the active system to the standby system and the standby system to the active system are completed.

(D) Configuration of the Third Embodiment of the Present Invention FIG. 5 is a configuration diagram of the third embodiment of the present invention, in which a single path in which N stages of switch modules with buffers are connected in series between input and output lines. This is an example applied to a multi-stage buffer type ATM communication path. Reference numerals 71 and 71 'denote operating system and standby system single-path multi-stage buffer type ATM communication paths, SRMi,
SRMi '(i = 1, 2,... N) is, for example, a self-routing switch module shown in FIG.
Is a buffer that shares a predetermined output link of each of the switch modules SRMi and SRMi '; 72 is a continuous empty monitoring unit that monitors that the buffers in the switch modules SRMi of each stage of the operating system are empty; 73 is a system switching unit;
74 is a system switching control unit. Each switch module SR
Although only one input link and one output link of Mi and SRMi 'are shown, there are m input links and m output links, and the output link of the preceding stage is connected to the predetermined input link of the next stage. . In the following description, it is assumed that the output link #j in the preceding stage is connected to the input link #j in the next stage.

The condition matching condition in the active system and the standby system
Consideration As described above, in the single-path multi-stage buffer type ATM communication path, even if the buffer connected to the output line #j at the last stage of the active system becomes empty, the output link #j at the preceding stage becomes available.
Cells (cells going to the outgoing line #j) may be accumulated in the buffer connected to, and it is guaranteed that the state (the number of staying cells) of the active system and the standby system is exactly the same at that time. Absent. Therefore, such a single-path multi-stage buffer type AT
Consider another condition in which the states of the outgoing line #j of the active system and the standby system match in the M communication path.

The fact that the buffer in the first stage becomes empty means that not only the input link but also the input state of the buffer in the second stage matches in the active system and the standby system thereafter. In this way, if the inputs to the second-stage buffers match, if the second-stage buffers become empty, the input states to the third-stage buffers will match thereafter. That is, after confirming the vacancy of the buffer up to the previous stage, the vacancy state of the buffer of the next stage is monitored, so that the vacancy of the buffer for accumulating cells heading for the outgoing line #j in order from the first stage is confirmed. If it is confirmed that the buffer at the last stage is empty, the ATM cell flows in the active system and the standby system for the outgoing line j completely match after that point.

When the system switching instruction signal SCH is generated from the operation system switching controller 74, the current standby system 71 'empties all buffers in all stages by clear means (not shown). Thereafter, the input cells from the incoming lines # 1 to #m are multicast to the current operating system 71 and the current standby system 71 'to apply the same cell flow to both systems, and the reading is performed in the same manner in both systems. Also, first, the system switching unit 73 outputs each outgoing line #j (j
= 1, 2,... M) from the active system.

[0063] monitors whether free monitoring unit 72 ₁ of the first stage in each stage free monitoring unit 72 is the total buffer FM ₁ connected to the output link #j vacated. Once the empty, indicating the output link #j in all buffers FM ₂ free monitoring of binding to the free monitoring section of the second stage (not shown). Thereafter, sequentially, the first stage → 2 stage → ··· (N-1) If the free buffer FM _N that binds to stage and the output link #j is confirmed, free monitoring unit of the last stage 72 _N is It is monitored whether the buffer to be connected to the outgoing line #j becomes free.

[0064] Then, when the buffer FM _N sharing the prescribed outgoing line #j has become free, thereafter, for the outgoing line j, the total buffer FMi of all stages of the current operating system and the backup system, FM
The contents of i 'match. Therefore, the last stage empty monitoring unit 72
_N inputs the system switching enable signal CEN to the system switching unit 73. Thereby, the system switching unit 73 selects and outputs the cell from the current standby system for the outgoing line #j. Similarly, for the other outgoing line, the cell in the current standby system is selected and output by confirming the availability of the buffer at the last stage sharing the outgoing line, and the operating state of the active system and the standby system is switched. . Thus, the switching from the active system to the standby system and the standby system to the active system are completed.

Application Example of Third Embodiment FIG. 6 shows an application example of the third embodiment. The self-routing switch module SRM shown in FIG.
This is an example in which the present invention is applied to an ATM communication path in which a VP shaper (VSH) is provided at the lower stage. Although only the VP shaper corresponding to outgoing line # 2 is shown, the same VP shape is applied to other outgoing lines.
A shaper is provided. The spare system is not shown, but is arranged in parallel with the active system so as to have the positional relationship shown in FIG.

In the VP shaper, VPDV is VPI
A VP distribution unit that distributes cells every time, and FB1 to FBn are V
A FIFO buffer provided for each PI, SEL is a selector, and SCD is a scheduler that reads cells from each FIFO buffer according to a preset schedule and sends out the cells to the outgoing line (transmission line) # 2. When the scheduler divides a transmission line into 128 cell slots per cycle, it is preset that which FIFO buffer should be called from each of the cell slots S _{1 to} S ₁₂₈ ,
The cell is read out from a predetermined FIFO buffer every 128 cell slots and transmitted to the transmission line # 2, and this operation is performed cyclically.

The system switching control unit issues a system switching instruction signal SCH
Occurs, the current standby system 71 '(FIG. 5) empties all buffers of the switch module SRM and the VP shaper VSH. Thereafter, the input cells from the input lines # 1 to # 4 are multicast to the current operating system 71 and the current standby system 71 ', and the same cell flow is added to both systems, and reading is performed in the same manner in both systems. Also, first, the system switching unit 73 outputs each outgoing line #j (j
= 1, 2,... M) from the active system. 1 stage free monitoring unit 72 ₁ monitors whether all the buffers connected to the output link # 2 has become empty. Once the empty, output links # 2 for the two-stage free monitoring unit 72 ₂
Instructing all FIFO buffers FB ₁ ~FBn free monitoring of binding to.

[0068] The second stage of free monitoring unit 72 ₂ outgoing lines #
When all the buffers FB ₁ ~FBn simultaneous free of binding to 2 is detected, thereafter, the output line # 2, the contents of all buffers in all stages of the current operational and standby systems coincide. Thus, the system switching enable signal CE to the free monitoring unit 72 ₂ system switching section 73
Enter N. Thereby, the system switching unit 73 selects and outputs the cell from the current standby system for the outgoing line # 2. Similarly, the cells from the current standby system are selected and output by confirming the simultaneous availability of all buffers in the last stage sharing the outgoing line with the other outgoing lines, thereby switching the operating state between the active system and the standby system. I do. Thus, the switching from the active system to the standby system and the standby system to the active system are completed.

(E) Fourth Embodiment of the Present Invention Limitations of the Second Embodiment The second embodiment is an ATM in which the connection relation of buffers is complicated.
Difficult to extend to the call path. For example, a case is considered in which there are a plurality of front-stage buffers connected to a rear-stage buffer, such as a multi-path multi-stage buffer type ATM communication path (see FIG. 13), and these are also connected to other subsequent-stage buffers. It is clear.

FIG. 7 is an explanatory diagram of the limit of the second embodiment. In the buffer 1 at the preceding stage, both cells going to the buffer 1 at the subsequent stage and cells going to the buffer 2 at the subsequent stage are accumulated.
When the next buffer 1 becomes empty, the first buffer 1
Cannot be guaranteed that they are empty. The reason is that if the first several storage cells of the first buffer 1 are for the second buffer 2 and the last cell to be stored in the first buffer 1 is stored, the second buffer 1 This is because, after being vacant, cells arrive at the subsequent buffer 1 after the first few cells of the preceding buffer 1 have been extracted. Of course, this method
It is sufficient to confirm that the vacancy of the subsequent stage continues for the read time of the buffer length of all the buffers of the preceding stage, but this probability is extremely small, which is not realistic considering the complicated connection relationship of the buffers. In addition, the above problem clearly indicates that the entire communication path is empty if this state is continued after the simultaneous empty state of all the buffers in the subsequent stage has been confirmed. Are perfectly matched, but the probability is also very small, making this method impractical for multi-path multi-stage buffered ATM channels.

Extension of the Third Embodiment The third embodiment is an ATM in which the connection relation of buffers is complicated.
It can be extended to a communication path, for example, a multi-path multi-stage buffer type ATM communication path. FIG. 8 is a schematic explanatory view of a fourth embodiment obtained by expanding the third embodiment. If the buffers of all stages in the standby system are emptied by the system switching instruction, the same cell flow is input to the active system and the standby system, and the cells are output from the active system and the standby system in the same manner. Can be said. That is, in a state where the states of the active system and the standby system up to the (i-1) -th stage are identical, if the vacancy of a certain buffer FB _i1 at the i-th stage is confirmed, the state of that buffer is changed to The system and the standby system match (FIG. 8 (a)). However, as long as the output of the other i-th buffer FB _i2 connected to the (i + 1) -th buffer FB _{(i + 1)} does not match, the (i + 1) -th buffer FB _{(i + 1)} FB
It doesn't make sense to check the availability of _{(i + 1)} .

In other words, the i-th stage buffers FB _i1 , F i connected to the (i + 1) -th stage buffer FB _{(i + 1)}
For all B _i2 , when the input state matches between the active system and the standby system, and when the i-th buffers FB _i1 and FB _i2 are vacant, it is the first time that the (i + 1) -th buffer FB _i1 is used. It can be said that the input to _{(i + 1)} matches between the active system and the standby system. Then, the (i + 1) -th stage buffer FB
_{Due to} the vacancy of _{(i + 1)} , it can be confirmed that the output matches between the active system and the standby system.

In summary, all buffers of the current standby system are made empty by a system switching request, input cells are multicast to the current operating system and the current standby system, the same cell flow is added to both systems, and reading is performed in both systems. Performs in the same manner, selects a cell from the active system as an output to each outgoing line, and monitors, for each of all output links of all of the preceding switch modules, the availability of the preceding buffer that shares the output link. When it is confirmed that all the buffers in each output link of the preceding stage are simultaneously vacant, the operation of monitoring the vacancy of the buffer sharing the output link is performed for each of the output links of all the switch modules in the next stage, and so on. Monitors the availability of the last-stage buffer sharing the outgoing line for each output link (outgoing line) of all the last-stage switch modules When all the buffers sharing a predetermined output line are simultaneously vacant, cells from the current standby system are selected and output for the output line, and similarly, the simultaneous vacancy of the buffer is confirmed for each output line. As a result, the cell from the current standby system is selected and output, and the operation state of the active system and the standby system is switched.

In this case, when it is confirmed that the buffers are simultaneously vacant for all the outgoing lines, the cells from the current standby system are collectively selected and output to all the outgoing lines, and the operating states of the active system and the standby system are checked. Can also be switched.

(F) Fifth Embodiment of the Present Invention The multi-path multi-stage buffer type ATM communication path shown in FIG. 13 forms a multi-path three-stage buffer type ATM path. When the fourth embodiment is applied, instead of monitoring that all buffers of the first stage that share the output link of the first stage are simultaneously vacant, the output link of the first stage ( It can be replaced by monitoring whether all buffers in the second stage coupled to the second stage input link) are simultaneously free. FIG.
In the multi-path three-stage buffer type ATM communication path,
A self-routing switch module having a buffer on the intersection of three input links and three output links (FIG. 1).
5) are arranged in parallel to form one stage,
This is provided in three stages. Then, the j-th output link of the preceding i-th self-routing switch module is
I of the next j-th self-routing switch module
Connected to the second input link.

In the case of the multi-path three-stage buffer type ATM path, the fact that all buffers in the first stage that share the output link of the first stage are simultaneously vacant is determined by the output link in the first stage (the second stage). Can be determined based on the fact that all the buffers in the second stage coupled to the input link are simultaneously free. FIG. 9 is a simplified representation of a second-stage predetermined self-routing switch module in a multi-path three-stage buffer type ATM path, in which all first-stage buffers sharing the first-stage output link #i ( (Not shown) are simultaneously vacant because the output link #i of the first stage (the input link # 1 of the second stage)
2) All buffers FM1i, FM2i, F of the second stage
It can be determined from the fact that M3i is simultaneously empty.

Therefore, a multi-path three-stage buffer type ATM
In the case of a passage, switching of the system is performed by confirming the coincidence of the states of the active system and the standby system in the following steps. In other words, all buffers of the current standby system are vacated by the system switch request,
The input cells are multicast to the current working system and the current standby system, and the same cell flow is added to both systems.Reading is performed in the same manner in both systems, and a cell from the current working system is selected as an output to each outgoing line. Ith in the second stage (i = 1,
The j-th (j = 1, 2, 2, 3) switch module of (2, 3)
3) It is monitored whether all the buffers connected to the input link are simultaneously vacant. When the simultaneous vacancy of all the buffers is confirmed for each of the input links of all the switch modules in the second stage, the second stage i It monitors that all buffers connected to the k-th (k = 1, 2, 3) output link of the (i = 1, 2, 3) switch module are simultaneously vacant, and monitors all switches in the second stage. When it is confirmed that all buffers are simultaneously vacant for each output link of the module, the i-th output link (outgoing line) #i of the k-th (k = 1, 2, 3) switch module in the third stage It monitors whether all the coupled buffers have become empty at the same time, and when the empty is confirmed, selects and outputs the cell from the current standby system for the outgoing line #i, and outputs the buffer for each outgoing line at the third stage. Check simultaneous availability of Switching the operational state of the cell selection and output to the operational system and a standby system from the current reserve system by.

In this case, when it is confirmed that the buffers are simultaneously vacant for all the outgoing lines # 1 to # 3 of the third stage,
It is also possible to switch the operating state between the active system and the standby system by selecting and outputting cells from the current standby system at once for all outgoing lines.

(G) Time required until the buffer becomes empty According to the present invention, it is necessary to wait for system switching until the buffer becomes empty. Easily evaluate that time. Assuming that the use rate of the outgoing line is a, for example, assuming an M / M / 1 queuing model, the probability that the buffer becomes empty is (1−
a). When one (1) buffer memory is shared by a plurality of (= K) outgoing lines, the probability that this buffer becomes empty is (1-a) ^K. Therefore, the probability Pe that the buffer becomes empty at least once during the cell time at the N outgoing lines is as follows. Pe = 1- [1- (1-a) ^K ] ^N

FIG. 10 shows the probability Pe of encountering at least one buffer vacancy, the utilization rate a and the number k of shared outgoing lines on the vertical axis, and the observation period (outgoing cell time: number of cells) N on the horizontal axis. This is shown. For example, if the usage rate is 0.8 and the number of shares is 1,
As for the vacancy of the buffer for each outgoing line, the buffer vacancy state is encountered with a probability of about 90% after 10 cell times have elapsed. Therefore, the preparation period for system switching does not matter, and the system can be switched quickly. FIG. 10 shows a case of one stage. Therefore, in the case of m stages with the same configuration of each stage, a = 0.8,
When k = 1, a buffer empty state is encountered with a probability of about 90% after 10 · m cell time.

(H) Distinguishing between the case where simultaneous empty space needs to be checked and the case where it is not necessary The present invention provides that the active system buffer and the current standby system will be completely As long as the cells arrive in the same pattern and read out the cells in the same pattern, the basic principle is that the resident cells of both systems completely match and the output cell flows also completely match. When a plurality of buffers are connected to one outgoing line, the outputs of both systems may coincide only when the availability of these buffers of the active system can be confirmed at the same time. The output of both systems may be identical if the buffer is vacant.

When it is sufficient to check the free space of the buffer independently In the case of the VP shaper VSH shown in FIG. 6, the reading of each buffer FB1, FB2,. Only. Therefore, once a buffer in the active system becomes empty once, the output cell flow of that buffer is completely identical between the active system and the current standby system. In such a case, the vacancy of each buffer FB1, FB2,... FBn is independently monitored, and if any of the buffers becomes empty at least once, the VP shaper VSH multiplexes the output of each buffer. It can be considered that the state of the output link of completely matches.

In the case where it is necessary to confirm the simultaneous vacancy of all the buffers, as shown in FIG. In a concentrator where each buffer is read-accessed in the order in which cells arrive and output to one outgoing line #i, reading depends on the input pattern of all buffers. Therefore,
Even if a buffer in the active system becomes empty, the next access timing to this buffer differs between the active system and the standby system depending on the arrival of another cell. In such a system, by confirming that all the buffers FMi1 to FMim become empty at the same time, it can be said that the outputs are completely the same in both systems. Incidentally, the simultaneous vacancy of all the buffers can be easily checked by the vacancy of the arrival order management FIFO 51. The case where the self-routing switch module and the VP shaper are used as the switch modules has been described above, but other configurations may be used.
As described above, the present invention has been described with reference to the embodiments. However, the present invention can be variously modified in accordance with the gist of the present invention described in the claims, and the present invention does not exclude these.

[0084]

As described above, according to the present invention, the standby system buffer is emptied by the system switching instruction, and thereafter, the same cell flow is added to the active system and the standby system, and the active system buffer is simultaneously emptied. When the system is configured to switch between the active system and the standby system, system switching can be performed without instantaneous interruption without providing a redundant buffer amount, and even when system switching is stopped, cell discard does not occur. Even if the standby system is found not to be operating normally, the cell is not discarded even if the standby system is returned to the original state, and the service can be improved.

Further, according to the present invention, in the case of a single-path multi-stage buffer type ATM communication path in which N stages of buffered switch modules are connected in series between an incoming line and an outgoing line, the buffer of the last stage switch module is (N− 1) The cell from the current standby system is selected and output to the outgoing line #i when the cell is continuously vacant during one cell transfer timing, so that the single path multi-stage buffer type ATM communication path is used. Even in this case, the system switching can be performed without an instantaneous interruption, and even when the system switching is stopped, no cell discard occurs, and therefore, when the standby system is found to be not operating normally, Even if it returns to the state, the cell is not discarded, and the service can be improved. Further, in this method, system switching can be realized with a simple hardware configuration without increasing the number of system confounding points.

Further, according to the present invention, in the case of a single-path multi-stage buffer type ATM communication path in which a plurality of stages of buffers are provided between an incoming line and an outgoing line, after confirming that the preceding stage buffer is empty, Since the operation of confirming the availability of the buffer in the next stage is performed, and the availability of the buffer in the final stage is confirmed in the same manner, the cell from the current standby system is selected and output to the outgoing line #i. Single path multi-stage buffer type A
Even in the case of the TM communication path, it was found that the system switching could be performed without an instantaneous interruption, and that even if the system switching was stopped, no cell was discarded, and therefore the standby system did not operate normally. Even if the state is returned to the original state at the time, the cell is not discarded, and the service can be improved. Further, according to this method, the number of system confounding points does not increase, the system can be switched with a simple hardware configuration, and the ATM with the VP shaper is provided.
The present invention can also be applied to system switching of a communication path.

Further, according to the present invention, there are provided a plurality of paths between a certain incoming line and a certain outgoing line, and a plurality of buffered switch modules between each incoming and outgoing line. It can also be applied to system switching. That is, for each output link of all the switch modules in the preceding stage, the availability of the buffers in the preceding stage sharing the output link is monitored, and when the simultaneous availability of all the buffers in each output link in the preceding stage is confirmed, the next stage is monitored. For all the output links of all the switch modules, the vacancy monitoring operation of all the buffers sharing the output link is performed. Thereafter, similarly, for all the output links (outgoing lines) of the last-stage switch modules, Monitors the availability of the last-stage buffer sharing the outgoing line, and when the buffer sharing the predetermined outgoing line becomes empty at the same time, selects and outputs the cell from the current standby system for that outgoing line. In the same manner, the cells from the current standby system are selected and output by confirming the simultaneous vacancy of the buffer for each outgoing line, and the operation status of the active system and the standby system is switched. Because the way, never system inter-woven points is increased, the switching can be realized a system of multi-path multi-stage buffer type ATM speech path with a simple hardware configuration.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a schematic explanatory diagram of a first embodiment of the present invention.

FIG. 3 is a configuration diagram of a first embodiment.

FIG. 4 is a configuration diagram of a second embodiment.

FIG. 5 is a configuration diagram of a third embodiment.

FIG. 6 is an explanatory diagram of an application example of the third embodiment.

FIG. 7 is an explanatory diagram of a limit of the second embodiment.

FIG. 8 is a schematic explanatory diagram of a fourth embodiment.

FIG. 9 is an explanatory diagram of a fifth embodiment.

FIG. 10 is a chart showing the probability of encountering at least one buffer vacancy.

FIG. 11 is a configuration diagram of an ATM cell.

FIG. 12 is a schematic explanatory diagram of an ATM network.

FIG. 13 is a configuration diagram of a multi-path multi-stage buffer ATM switch.

FIG. 14 is an explanatory diagram of a routing header added to an ATM.

FIG. 15 is a configuration diagram of a self-routing switch module.

FIG. 16 is a simplified representation of a self-routing switch module.

FIG. 17 is a self-routing ATM switch (in the case of one stage).
FIG.

FIG. 18 is a configuration diagram of a single-path multi-stage buffer type ATM switch.

FIG. 19: ATM in the proposed system switching method
It is a schematic block diagram of a communication path.

FIG. 20 is an explanatory diagram of a proposed system switching method.

FIG. 21 is an explanatory diagram of a system switching method in a common buffer type ATM communication path.

FIG. 22 is a diagram illustrating a problem of the proposed system switching method.

[Explanation of symbols]

51 ... ATM ATM communication path FM ... A buffer in the active ATM communication path 51 '... ATM ATM communication path in the standby system FM' ... A buffer in the ATM communication path in the standby system 52. Monitoring unit 53... System switching unit 61... ATM line of active system FMi... One buffer in ATM line of active system 61 ′... ATM line of standby system FMi ′... ATM line of standby system One buffer 62 in... A continuous idle monitoring unit 63... A system switching unit 71... A single ATM buffer 71 ′ in an active ATM communication channel FMi. One buffer 72 in the standby ATM communication path 72 ·· Each stage empty monitoring unit 73 ··· System switching unit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Ezaki 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. 72) Inventor Kazuo Hatsukano 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. Fujitsu Limited (72) 1015 Ueodanaka, Nakahara-ku, Kawasaki City Inventor Akira Chugo 1015 Ueodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. Address Fujitsu Limited (56) Reference JP-A-3-26038 (JP, A) JP-A-4 49735 (JP, A) JP flat 2-246646 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB name) H04L 12/28 H04L 12/56

Claims (7)

(57) [Claims] 1. A redundant configuration in which two identical ATM communication paths are arranged in parallel, a current operating system is used as a standby system,
In a system switching method for an ATM switch in which the current standby system is switched to the active system and the operation state is switched, all buffers of the current standby system are once emptied by a system switching request, and then the input cells are multicast to the current operating system and the current standby system. The same cell flow is applied to both systems, and reading is performed in the same manner in both systems, and cells from the active system are continuously selected as outputs to each outgoing line, and connected to the outgoing line of the active system. It monitors whether the number of storage cells in all buffers has become 0 (buffer empty), and after the buffer connected to a predetermined output line becomes empty even once, the current standby system The operation system for the outgoing line is switched by starting to select a cell from the outgoing line. Similarly, for the other outgoing lines, it is confirmed that all buffers connected to the outgoing line have become free even once. From the current spare System switching method of ATM switching system to select a cell and switches the operation state of the operation system and a standby system from. 2. When the vacancy of all buffers is confirmed at least once for each of all outgoing lines, cells from the current standby system are output to all outgoing lines in a lump and the operation status of the active and standby systems is checked. 2. The method according to claim 1, wherein the switching is performed. 3. The ATM communication path according to claim 1, wherein the ATM communication path is a single-path multi-stage buffer type ATM communication path in which N-stage buffered switch modules are connected in series between an input line and an output line.
In the step of emptying the spare buffer, the N
Empty all buffers of switch module with buffer
Check that the buffer connected to the predetermined output line of the last-stage switch module is continuously free for a period corresponding to the time required for cells to be transferred from the first-stage switch module to the last-stage switch module. 3. The system switching of the ATM exchange according to claim 1 or 2, wherein the cell selection for the outgoing line is changed from the current operation system to the current protection system to perform instantaneous interruption switching. How . 4. If the ATM communication path is a single path multi-stage buffer type ATM communication path in which a plurality of buffered switch modules are provided between an incoming line and an outgoing line,
In the step of emptying the buffer of the auxiliary system, the N stages
Free all buffers of switch module with buffer
To, to start a free checking operation of the next stage of the buffer after it is confirmed that the front stage of the buffer of the current operating system has become empty, continue to check the free of buffer one after another in the same way below,
2. The method according to claim 1, further comprising, after a vacancy of a buffer coupled to a predetermined output line of the last stage switch module is confirmed, switching a cell to the output line from the current operation system to the current standby system. 3. A method for switching a system of an ATM exchange according to claim 2. 5. A multi-path multi-stage buffer type ATM communication path in which a plurality of paths exist between one input port and one output port, and a plurality of buffered switch modules exist between each input / output port. It has a duplex configuration in which two are arranged in parallel, and the current operating system is used as a standby system,
In a system switching method for an ATM switch in which the current standby system is switched to the active system and the operation state is switched, all buffers of the current standby system are vacated by a system switching request, and input cells are multicast to the current operating system and the current standby system to be the same cell. The current is applied to both systems, and readout is performed in the same manner in both systems, and cells from the current operation system are continuously selected as outputs to the respective output lines. Monitors the simultaneous vacancy of all buffers connected to the line, and checks the simultaneous vacancy of all buffers connected to each outgoing line. Performs the operation of monitoring the availability of all buffers in the next stage connected to each output line, and thereafter, in the same manner, for all output lines of all switch modules in the final stage. Monitors the availability of all buffers connected to the outgoing line, and when all the buffers connected to a given outgoing line become empty at the same time, selects and outputs cells from the current standby system for that outgoing line. In the same manner, the system switching of the ATM switching system is characterized in that the cells from the current standby system are selected by switching the operating status between the active system and the standby system by confirming the simultaneous availability of all buffers for each outgoing line. How . 6. When it is confirmed that all buffers are simultaneously vacant for all the outgoing lines of all the switch modules at the last stage, cells from the current standby system are output to all outgoing lines at once and the active system is connected to the active system. 6. The method according to claim 5, wherein the operation state of the standby system is switched. 7. A self-routing switch module having a buffer at an intersection of m input links and m output links is arranged in parallel to form one stage, and
A multi-path three-stage buffer type ATM path in which three stages are provided, and the j-th output link of the i-th self-routing switch module of the preceding stage is connected to the i-th input link of the j-th self-routing switch module of the next stage. 2
In the system switching method of an ATM switch, which has a duplex configuration arranged in parallel with each other and switches the current operation system to the standby system and switches the operation state by setting the current standby system to the active system, all buffers of the current standby system are requested by the system switching request. Is vacated, the input cells are multicast to the current working system and the current standby system, the same cell flow is added to both systems, and reading is performed in the same manner in both systems, and the output from the working system is output to each outgoing line. Select a cell and monitor whether all buffers coupled to the j-th input link of the ith switch module in the second stage are simultaneously free, and for each of the input links of all the switch modules in the second stage, When it is confirmed that the buffers are simultaneously vacant, all buffers connected to the k-th output link of the ith switch module in the second stage become vacant at the same time. When the simultaneous freeness of all buffers is confirmed for each of the output links of all the switch modules of the second stage, the output link is connected to the i-th output link (outgoing line) of the k-th switch module of the third stage. It is monitored whether all the buffers are empty at the same time. When the empty is confirmed, the cell from the current standby system is selected and output for the i-th outgoing line.
The cells from the current standby system are selected and output by confirming the simultaneous vacancy of the buffer for each outgoing line in the stage, and the operating state of the active system and the standby system are switched. ATM switch characterized in that when simultaneous availability of buffers is confirmed, cells from the current standby system are collectively selected and output to all outgoing lines to switch the operating state between the active system and the standby system. System switching method .