JP3125467B2 - Digital demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for demodulating an FM-modulated luminance signal reproduced from a video tape, and more particularly to an apparatus for demodulating an FM-modulated luminance signal.
The present invention relates to a digital demodulator that converts an M-modulated luminance signal into a digital signal and demodulates the signal.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional digital demodulator. The FM-modulated luminance signal reproduced by the reproducing head 1 is amplified by the amplifier 2 and converted into a digital signal a by the A / D converter 3, and then the 0-degree phase shifter 4 and the 90-degree phase shifter constituting the Hilbert converter are used. Input to the container 5.
If the digital signal a is expressed as, for example, cosωt, the output signal b of the 0-degree phase shifter 4 is expressed as cosωt, and the output signal c of the 90-degree phase shifter 5 is expressed as sinωt.

A demodulator 6 demodulates a luminance signal from the output signals b and c. This is performed by obtaining the angle of the FM modulation luminance signal from the value of arctan obtained from the values of cosωt and sinωt, and differentiating this angle.

The signals b and c output from the phase shifters 4 and 5 are, as shown in FIG.
, That is, a band of 2 fc, that is, the sampling frequency is at least 4 fc from the principle of sampling.
(Basic sampling frequency) required.

[0005]

Since the power consumption of a digital circuit is proportional to the number of level inversions of a signal, it is proportional to the sampling frequency. The lower the sampling frequency, the lower the power consumption.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital demodulator capable of reducing the power consumption by lowering the sampling frequency of a digital signal.

[0007]

According to the present invention, there is provided a digital demodulator for converting a reproduced FM modulated luminance signal into a digital signal and demodulating the digital signal.
Low-frequency conversion means for performing low-frequency conversion on a complex digital signal obtained by complex-converting the digital signal by a frequency lower than a basic sampling frequency which is a predetermined multiple of a carrier frequency of the FM-modulated luminance signal; Sampling means for sampling the complex digital signal at a frequency lower than the basic sampling frequency.

[0008]

The digital demodulator according to the present invention, as shown in FIG. 1, cos ωt × cos (ωs / ωs) which is the result of multiplication of the signal b of cos ωt and the signal d of cos (ωs / 4).
4) is output from the multiplier 7, and the signals c and c of the sin ωt
sinω which is the result of multiplying the signal d of os (ωs / 4) with the signal d
t × cos (ωs / 4) is output from the multiplier 8 and
cosωt × sin (ωs / 4), which is the result of multiplying the signal b of sωt and the signal e of sin (ωs / 4),
And the signal c of sinωt and sin (ωs /
4) sinωt × sin which is the result of multiplication with the signal e
(Ωs / 4) is output from the multiplier 10.

Therefore, the value of the output signal f of the adder 11 is
(Cosωt × cos (ωs / 4) + sinωt × si
n (ωs / 4)) = cos (ω−ωs / 4) t, and the value of the output signal g of the adder 12 is (sinωt × cos)
(Ωs / 4) −cosωt × sin (ωs / 4)) = si
n ((ω−ωs / 4) t) The signals f and g are signals obtained by shifting the signals b and c by ωs / 4, as shown in FIG. Is only required to be at least fs / 2 = 2fc This sampling frequency is 1/2 of the basic sampling frequency fs required when the frequency is not shifted, and the power consumption is reduced by half as compared with the case where the frequency is not shifted.

[0010]

Next, an embodiment of a digital demodulator according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Each of the phase shifters 4 and 5 outputs a signal b, s of cos ωt.
The process up to the point where the signal c of inωt is output is the same as that in FIG.

The signal b of cosωt and cos (ωs / 4)
Is input to the adder 1 by the multiplier 7 which receives the result of multiplication of the signals b and d by cos ωt × cos (ωs / 4).
1 and the signal c of sinωt and cos (ωs / 4)
Is input to the adder 1, and the multiplier 8 receives the signal c and the result of multiplying the signal c by the signal sinωt × cos (ωs / 4).
Output to 2.

The signal b of cos ωt and sin (ωs
/ 4) is input to the multiplier 9, and the multiplier 9 outputs cosωt × sin (ωs / 4), which is the result of multiplication of the signals b and e, to the adder 12, and outputs the signal c and sin (ωs) of sinωt.
/ 4) receives the signal e and the signal c.
Is output to the adder 11 as the result of multiplication by sinωt × sin (ωs / 4).

Therefore, the value of the output signal f (complex digital signal subjected to low-frequency conversion) f of the adder 11 is given by: (cosωt × cos (ωs / 4) + sinωt × sin (ωs / 4)) = cos (ω−ωs / 4) t (1), and the value of the output signal (complex digital signal subjected to low-frequency conversion) g of the adder 12 is (sin ωt × cos (ωs / 4) −cosωt × sin (ωs / 4)) = Sin ((ω−ωs / 4) t (2)

As can be seen from equations (1) and (2), the signals f and g are signals obtained by shifting the signal b of cos ωt and the signal c of sin ωt by ωs / 4, and the signal band is as shown in FIG. become. As can be seen from FIG.
The band frequency of g is up to the carrier frequency fc, and the minimum value of the required sampling frequency is the basic sampling frequency f
Half of s, fs / 2 = 2fc.

Therefore, the power consumed by the sample rate converters (sample means) 13 and 14 and the demodulator 6 in FIG. 1 is halved compared to the case where the frequency shift of ωs / 4 is not performed. Further, since the sampling frequency is low, the response speed of a semiconductor element or the like constituting the digital demodulation device may be low, and the cost is reduced.

In FIG. 1, multipliers 7 to 10 and adder 1
1 and 12 constitute low-frequency conversion means.

Here, sin (ωs) in equations (1) and (2)
/ 4), sin (ωs / 4) is as shown in FIG. 4, and when sampling at sampling frequency fs / 2, for example, sin (ωs / 4) as shown at times t1 and t2
If sampling is performed at a time when the value of (ωs / 4) becomes zero, the second term of the equations (1) and (2) becomes unnecessary, and if this is shown in a block diagram, it becomes as shown in FIG. The circuit can be greatly simplified.

[0019]

As described above, the digital demodulator according to the present invention down-converts a complex digital signal by a frequency lower than the basic sampling frequency, and converts the low-frequency-converted complex digital signal to a frequency lower than the basic sampling frequency. Since sampling is performed at a low frequency, power consumption in the device can be reduced in accordance with the degree of reduction in the sampling frequency.

In addition, since the sampling frequency of the low-frequency-converted complex digital signal can be reduced, the response speed of the semiconductor elements and the like constituting the device can be reduced, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital demodulation device according to the present invention.

FIG. 2 is a characteristic diagram showing a band frequency when a complex digital signal is frequency-shifted.

FIG. 3 is a block diagram showing an apparatus obtained by simplifying the apparatus shown in FIG. 1;

FIG. 4 is an explanatory diagram of a sampling example in the apparatus of FIG. 1;

FIG. 5 is a block diagram showing a conventional digital demodulation device.

6 is a characteristic diagram showing a band frequency of a complex digital signal in the device of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Reproduction head 2 Amplifier 3 A / D converter 40 0 degree phase shifter 5 90 degree phase shifter 6 Demodulator 7-10 Multiplier (low frequency conversion means) 11, 12 Adder (low frequency conversion means) 13, 14 samples Rate converter (sample means)

Claims (1)

(57) [Claims] 1. A digital demodulator for converting a reproduced FM-modulated luminance signal into a digital signal and demodulating the digital signal, wherein a complex digital signal obtained by complex-converting the digital signal is converted into a carrier frequency of the FM-modulated luminance signal. Low frequency conversion means for performing low frequency conversion by a frequency lower than the basic sampling frequency which is a predetermined multiple; and sampling means for sampling the low frequency converted complex digital signal at a frequency lower than the basic sampling frequency. A digital demodulator characterized by the following.