JP3125886B2 - Playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, for example, a reproducing apparatus in a digital data transmission system such as an image transmission system.

[0002]

2. Description of the Related Art In an image recording system for digitally recording an image signal on a magnetic tape, an image transmission system using a digital telephone line or the like, a transmitting device (or a recording device) is used.
Is a method of dividing image data into blocks of a predetermined number, adding a synchronization code SYNC, an identification code ID, and a parity for error correction in block units, and transmitting the data to a transmission line after predetermined modulation. On the receiving device (or reproducing device) side, the timing of each data separation is determined by the synchronization code. Then, the arrangement of the received (reproduced) data is determined based on the identification code, and is written to the corresponding address of the data memory,
A predetermined reproduction process is performed.

Consider a digital image recording / reproducing apparatus as an example. FIG. 2 shows the format of one synchronization block. 10
Is a synchronization code SYNC, 12 is an ID representing an upper address of data, 14 is an error detection code of ID 12, 16 is image data, and 18 is an error detection and correction code of image data 16.

In a magnetic recording / reproducing system, dust or the like adheres to a magnetic head, so that the output of the magnetic head is dropped (dropout). At the time of reproduction, when the analog recording / reproducing apparatus detects this dropout, it performs dropout compensation by substituting the signal of the horizontal line immediately before having correlation, but the digital recording / reproducing apparatus prohibits writing to the data memory. Then, the defective data dropped out is invalidated, and the dropout is compensated by operating the address of the data memory.

FIG. 4 is a block diagram showing the basic structure of a conventional example. Reproduced synchronous blocks having a format as shown in FIG. 2 are sequentially input to the input terminal 20. The synchronization detection circuit 22 detects a synchronization code SYNC from a code string input to the input terminal 20, and applies a synchronization detection signal 22a to the timing generation circuit 24. According to the synchronization detection signal 22a, the timing generation circuit 24 outputs the I
D signal that defines the D detection timing (hereinafter, I signal
Abbreviated as DT signal. ) 24a is supplied to the ID detection circuit 32. The timing signal generation circuit 24 internally has a symbol counter 26 for counting the number of symbols (for example, 207 symbols) in one synchronization block, a block counter 28 for counting the number of synchronization blocks, and a channel, a field, and a frame. An upper counter 30 is provided. The symbol counter 26 is initialized by a synchronization detection signal 22a from the synchronization detection circuit 22.

An ID detection circuit 32 detects an ID code from a reproduced code string at the input terminal 20 in accordance with the IDT signal 24a, and outputs an ID load timing signal (hereinafter abbreviated as IDL signal) 32a in the timing signal generation circuit 24. Apply to block counter 28. Block counter 2
Reference numeral 8 reads ID information (block number and line number) from the reproduction code string of the input terminal 20 according to the IDL signal 32a. The timing signal generation circuit 24 outputs the counter values of the symbol counter 26, the block counter 28, and the upper counter 30 that operate based on the synchronization detection signal 22a and the IDL signal 32a as a memory address signal 24b. A write request (WRQT) signal 24c for requesting write permission is output.

When a dropout occurs, the request mask circuit 34 outputs a WRQT signal 24 based on a dropout (DOS) signal from a dropout detection circuit (not shown).
c is masked and passed through when no dropout occurs, and applied to the memory circuit 40. Memory circuit 4
0 outputs a write permission (WACK) signal after arbitration processing inside the memory circuit 40 in response to a write request signal from the request mask circuit 34. Data latch circuit 36
The address latch circuit 38 is enabled by the WACK signal, and latches the data portion of the reproduced code string at the input terminal 20 and the addresses output from the counters 26, 28, and 30, respectively. The data held by the latch circuit 36 is written at a predetermined timing to a storage location of the memory circuit 40 specified by the address held by the latch circuit 38.

[0008]

In the above-mentioned conventional example, the masking of the write request signal 24c is controlled only by the presence or absence of dropout. Therefore, in the conventional example,
When the synchronization code SYNC or the identification code ID is erroneously detected, the counters 26, 28, 30
Is written to the address where
There is a problem that data stored in the memory circuit 40 is destroyed.

An object of the present invention is to provide a reproducing apparatus which solves such a problem.

[0010]

According to the present invention, there is provided a reproducing apparatus for reproducing a data string comprising a plurality of synchronous blocks each having synchronous data, ID data and a predetermined amount of information data. A synchronization detecting means for detecting the synchronization data from the data string;
D data is detected and the ID data is detected.
ID detection means for outputting a status signal indicating whether or not the information is good, a memory for storing the information data, and a write address of the information data in the memory based on outputs of the synchronization detection means and the ID detection means. Output from the specified address generating means and the ID detecting means
And a controlling means for prohibiting the writing of the information data pair to the memory in response to said state signal.

[0011]

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention. The same reference numerals are given to the same circuit elements as in FIG. Reference numeral 42 denotes a synchronization detection circuit, and the synchronization detection signal 22
a as well as the synchronization code SY
Detection state signal 42b indicating whether or not the detection state of NC is good
Is output. An ID detection circuit 44 outputs a detection state signal 44b indicating whether or not the ID detection state is good, in addition to an ID detection signal 44a similar to the ID detection signal 32a.
Reference numeral 46 denotes a mode (MODE) indicating the status signals 42b and 44b, a dropout signal, and a reproduction (or reception) mode.
A request mask circuit that passes or masks the write request signal 24c according to the signal.

The synchronization detection circuit 42 detects a synchronization code SYNC from the reproduced code string at the input terminal 20, supplies a synchronization detection signal 42a to the timing signal generation circuit 24, and sends a status signal 42b indicating the detection state to a request mask circuit. Output to 46. The timing generation circuit 24 outputs the IDT signal 24a to the ID detection circuit 44 according to the synchronization detection signal 42a. Also, the symbol counter 26
Initialized by the synchronization detection signal 42a.

The ID detection circuit 44 detects an ID code from the reproduced code string at the input terminal 20 in accordance with the IDT signal 24a, outputs an ID signal 44a to the block counter 28 in the timing signal generation circuit 24, and detects the ID. The signal 44b is output to the request mask circuit 46. As in the conventional example, the block counter 28 reads the ID information (block number and line number) from the reproduced code string of the input terminal 20 according to the IDL signal 44a, and the timing signal generation circuit 24 sets the counters 26, 28, The counter value of 30 is output as a memory address signal 24b,
Write request for memory write permission (WRQT)
The signal 24c is output.

The request mask circuit 46 includes a dropout (DOS) signal, a MODE signal, and status signals 42b, 4
4b, the WRQT signal 24c is passed or masked. The detailed operation of the request mask circuit 46 will be described later. In response to the write request signal from the request mask circuit 34, the memory circuit 40 outputs a write permission (WACK) signal after arbitration processing inside the memory circuit 40. Latch circuit 3
6 and 38 are enabled by the WACK signal, and the data portion (including the error correction code portion) and the counters 26, 28, and 30 of the reproduced code string at the input terminal 20, respectively.
Latch the address output from. Latch circuit 36
Is written at a predetermined timing to a storage location of the memory circuit 40 specified by the address held by the latch circuit 38.

FIG. 3 is a flowchart showing the operation of the request mask circuit 46. First, it is checked whether or not the synchronization detection and the ID detection are good (S1, 2, 3).
If both detections are good (S1, S2), a pass state is established in which the write request signal WRQT24c from the timing signal generation circuit 24 is supplied to the memory circuit 40 as it is.

If the synchronization detection is good and the ID detection is bad (S1, S2), the presence or absence of dropout is checked by the DOS signal (S5). If there is a drop-out, a mask state is set to mask the write request signal WRQT24c (S8). In other words, when the normal reproduction is not performed, that is, in the case of the special reproduction such as the search reproduction or the slow reproduction, since the erroneous writing into the memory is performed, the mask state is set (S8).

If the ID detection is good because the synchronization detection is bad (S1, 3), the presence or absence of dropout is checked by the DOS signal (S5, 6). If there is no dropout, the synchronization detection failure is regarded as having no trouble and the state is passed (S
4) If there is a dropout, it is checked whether or not it is normal reproduction by the MODE signal (S7). If it is normal reproduction, it becomes a passing state (S4). If it is not normal reproduction, it is like search reproduction or slow reproduction. In the case of special trick play, a mask state is set (S8).

If both the synchronization detection and the ID detection are defective (S1, 3), a mask state is set regardless of the reproduction mode and the presence or absence of dropout.

The functions described with reference to the flowchart shown in FIG. 3 can be realized by a combinational logic circuit, or of course, can be realized by software.

[0022]

As can be easily understood from the above description, according to the present invention, memory writing is prohibited in accordance with synchronization detection, ID detection, dropout, and playback (reception) mode. Memory writing can be properly prevented. Therefore, in the case of an image reproducing device,
A high-quality reproduced image can be obtained.

[Brief description of the drawings]

FIG. 1 is a basic circuit configuration block diagram of one embodiment of the present invention.

FIG. 2 is a configuration diagram of a synchronization block.

FIG. 3 is an operation flowchart of the request mask circuit 46 of FIG. 1;

FIG. 4 is a circuit configuration block diagram of a conventional example.

[Explanation of symbols]

20: input terminal 22: synchronization detection circuit 22a: synchronization detection signal 24: timing generation circuit 24b: memory
Address signal 24c: Write request (WRQT) signal 26: Symbol counter 28: Block counter 30: Upper counter 32: ID detection circuit 32
a: ID load timing signal 34: request mask circuit 36, 38: latch circuit 40: memory circuit 4
2: synchronization detection circuit 42a: synchronization detection signal 42b: detection state signal 44: ID detection circuit 44a: ID detection signal 44b: detection state signal 46: request mask circuit

Claims (2)

(57) [Claims] 1. An apparatus for reproducing a data string comprising a plurality of synchronization blocks each having synchronization data, ID data, and a predetermined amount of information data, comprising: synchronization detection means for detecting the synchronization data from the data string; ID detection means for detecting the ID data from the data string and outputting a status signal indicating whether or not the detection state of the ID data is good ; memory for storing the information data; address generating means for designating a write address of the information data in the memory based on an output of the ID detection means, the writing of the information data pair to the memory in response to the state signal outputted from the ID detection means Prohibit
And a control unit. 2. The method according to claim 1 , wherein each of the plurality of blocks is
Error detection data for detecting errors in D data
And an error for correcting an error in the information data.
2. The method according to claim 1, wherein the data has correction data.
Playback device.