JP3129043B2 - Switched capacitor integrator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor integrator using an amplifier, and more particularly to a switched capacitor integrator excellent in suppressing noise.

[0002]

2. Description of the Related Art Conventionally, a switched capacitor integrator has
A switched-capacitor integrator (hereinafter referred to as a positive-phase switched-capacitor integrator) for performing a positive-phase integration operation shown in FIG. 3 and a switched-capacitor integrator for performing a negative-phase integration operation shown in FIG. Phase-type switched capacitor integrator).

However, in FIGS. 3 and 4, 3-1 and 4-
1 indicates switch 1, 3-2 and 4-2 indicate switch 2, 3-3 and 4-3 indicate switch 3, 3-4 and 4
-4 indicates a switch 4. 3-5 and 4-5 indicate operational amplifiers, 3-6 and 4-6 indicate first capacitors, and
-7 and 4-7 indicate a second capacitor. 3-8, 4-
8 indicates a control means, 3-9 and 4-9 indicate constant potential sources, 3-10 and 4-10 indicate input terminals, 3-11,
Reference numeral 4-11 denotes an output terminal. 3-12 is switch 3-
Reference numerals 1 to 3 denote first signals for controlling switches 3-2 and 3-3. 4
-12 indicates a first signal for controlling the switches 4-3 and 4-4, and 4-13 indicates a second signal for controlling the switches 4-1 and 4-2.

The switches 1, 2, 3, and 4, as shown in FIG. 9, are composed of a P-channel MOS transistor (abbreviated as PMOS) and an N-channel MOS transistor (abbreviated as NMOS). However, 5-1 indicates an NMOS, and 5-
2 indicates a PMOS, and 5-3 indicates an inverter.

In FIG. 7, switches 3-1 and 3-4 are set to the first position.
And the switches 3-2 and 3-3 are controlled by the second signal 3-13. Switches 3-1 and 3-4
Is in the ON state, charge is accumulated in the first capacitor 3-6. Next, the switches 3-1 and 3-4 are turned off. Further, when the switches 3-2 and 3-3 are turned on, the electric charge accumulated in the first capacitor 3-6 is transferred to the second capacitor 3-7 and functions as a positive-phase integrator. FIG. 11 shows the timing of the switches 3-1, 3-2, 3-3, and 3-4.

In FIG. 8, switches 4-3 and 4-4 are set to the first position.
And the switches 4-1 and 4-2 are controlled by the second signal 4-13. Switches 4-3 and 4-4
Is in the ON state, the electric charge stored in the first capacitor 4-6 is discharged. Next, switches 4-3 and 4-4
Is turned off. Further, when the switches 4-1 and 4-2 are turned on, the charge is transferred from the second capacitor 4-7 to the first capacitor 4-6, and functions as a negative-phase integrator. Switches 4-1, 4-2, 4-3, 4-
The timing of No. 4 is shown in FIG.

[0007]

However, in the integrator shown in FIG. 3, when the switches 3-2 and 3-3 of the switched-capacitor integrator are simultaneously turned on, the switches 3-2 and 3-3 are respectively turned on. The noise caused by the parasitic capacitance and the like added to the output terminal 3-11 has a problem that these noises are further increased by the synergistic action and appear at the output terminal 3-11.

Similarly, in the integrator shown in FIG. 4, when the switches 4-1 and 4-2 are simultaneously turned on,
Noise is generated due to parasitic capacitance and the like added to each of the switches 4-1 and 4-2, and at the output terminal 4-11,
The problem is that a synergistic effect of noise occurs.

The present invention has been made to solve such a problem, and has as its object to provide an integrator in which noise at an output terminal is suppressed.

[0010]

To achieve this object, a positive-phase switched-capacitor integrator according to a first aspect of the present invention comprises a first signal having a fixed period, and the switches 1, 4 being driven by a first signal having a constant period. A second signal synchronized with the first signal periodically turns on or off when the switches 1 and 4 are off, and the switches 1 and 4 are turned on when the switches 1 and 4 are off. Delay means for periodically controlling the switch 2 to be in an on state or an off state so as to be in an off state when in an on state, and delaying the second signal;
The second signal is input to the delay means, delayed by the delay means from the second signal, and turned on when the switches 1 and 4 are off, and the switches 1, 4 Is off when is on
And a control means for periodically controlling the switch 3 to be turned on or off by the above signal.

Further, in the switched capacitor integrator according to the second aspect, the switches 3, 4 are periodically turned on or off by the first signal, and the second capacitor is in the second state.
The switch 2 is controlled by the signal (1), and the switch 1 is controlled by the third signal.

[0012]

According to the first aspect of the present invention, in the positive-phase integration operation of the switched capacitor circuit, the switch 2 and the switch 3 are not in phase, and the switch 3 is delayed.

In the conventional configuration in which the switches 2 and 3 are simultaneously turned on, the noise amplitude at the output terminal when the switch 2 is turned on is the noise amplitude at the output terminal when the switch 3 is turned on. If the amplitude is equal to 1 and the magnitude is 1, the noise at the output terminal when the switches 2 and 3 are simultaneously turned on is √ (2 × 2) = 2.

On the other hand, in the invention according to the first aspect of the present invention in which the switch 3 is delayed with respect to the switch 2 and the switch 3 is delayed, the switch 3 is switched on. The noise at the output terminal is √ (1 × 1 + 1 × 1) = √2. However, the amplitude of the noise at the output terminal when the switch 2 was turned on was equal to the amplitude of the noise at the output terminal when the switch 3 was turned on, and the magnitude was 1.

As a result, according to the first aspect of the present invention, noise at the output terminal is reduced, and a synergistic effect of noise when the switches are simultaneously turned on can be eliminated.

According to the second aspect of the present invention, in the negative phase integration operation of the switched capacitor circuit, the switch 1
And switch 2 are not made in phase and switch 1 is delayed. For this reason, the synergistic effect of noise when the switch 1 and the switch 2 are turned on can be eliminated for the same reason as described in the first aspect.

[0017]

【Example】

(Embodiment 1) FIG. 1 shows the configuration of an embodiment of an integrator according to claim 1 of the present invention. However, 1-1, 1-2, 1-
Reference numerals 3 and 1-4 denote switches 1 in the conventional example,
2, 3, and 4. 1-5 indicates an operational amplifier;
-6 indicates a first capacitor, 1-7 indicates a second capacitor, 1-8 indicates control means, 1-9 indicates a constant potential source, 1-10 indicates an output terminal, 1-11 Denotes a delay unit, 1-12 denotes a first signal, 1-13 denotes a second signal,
1-14 indicates the third signal.

In the in-phase type switched capacitor integrator according to the embodiment shown in FIG. 1, the first signal 1-13 having a constant period generated by the control means 1-8 is used for the switch 1-.
1, 1-4 are periodically turned on or off,
In addition, the second signal 1-14 synchronized with the first signal turns on when the switches 1-1 and 1-4 are off, and turns on the switches 1-1 and 1-4. , The switch 1-2 is periodically turned on or off so as to be in the off state, the second signal is input to the delay means 1-12, and the output of the delay means is switched to the switch 1- 3, the delay is longer than the second signal 1-14, and the switches 1-1 and 1-4 are turned on when the switches 1-1 and 1-4 are off, and the switches 1-1 and 1-4 are turned on. The switch 1-3 is periodically controlled to the on state or the off state using the third signal 1-15 controlled to be in the off state at the time of.

Switches 1-1, 1-2, 1-3, 1-4
3 is shown in FIG. In this embodiment, as described above, the switch 1-2 and the switch 1-3 are not set to the same phase.
The switch 1-3 is delayed.

The operation of this embodiment is as follows.
Now, assuming that the magnitude of the noise at the output terminal 1-11 coming from the switch 1-2 is the same as the noise coming from the switch 1-3, and normalizing the magnitude to 1, in the conventional case, When 1-2 and 1-3 are simultaneously turned on, the noise at the output terminal 1-11 becomes 2 (see FIG. 6).
reference).

However, in the case of the present invention, と な り 2 times (see FIG. 5), the switch 1-2 and the switch 1-
3 can be reduced.

Further, as shown in FIG. 10, the MOS type switches have parasitic capacitances 6-4, 6-5, 6-6, 6-7.
Is added.

If the switches 1-2 and 1-3 are simultaneously turned on as in the prior art, the potentials at both ends of the switch 1-2 become unequal, and as a result, the electric charge stored in the first capacitor is reduced. Is transferred to the second capacitor, the charges are also transferred to the parasitic capacitances 6-4 and 6-5,
The charge transferred to the second capacitor does not match the charge stored in the first capacitor. This difference results in noise at the output terminal 1-11.

Therefore, as shown in this embodiment, the parasitic capacitances 6-4 and 6-5 are charged by turning on the switch 1-2 prior to the switch 1-3. Next, when the switch 1-3 is turned on, the first capacitor 1-6 is turned on.
Is transferred to the second capacitor 1-7 as it is. As a result, the parasitic capacitance 6−
The problem of noise at the output terminal 1-11 derived from 4, 6-5 is solved.

(Embodiment 2) FIG. 2 shows the configuration of an embodiment of the integrator according to claim 2 of the present invention. However, 2-1 and 2
-2, 2-3, and 2-4 are switches 1 described above,
It has the same function as 2, 3, and 4. 2-5 is an operational amplifier, 2-6 is a first capacitor, 2-7 is a second capacitor, 2-8 is control means, 2-9 is a constant potential source, 2-10
Is an input terminal, 2-11 is an output terminal, 2-12 is delay means, 2-13 is a first signal, 2-14 is a second signal, 2-14.
-15 indicates the third signal.

In the inverted-phase switched-capacitor integrator shown in FIG. 2, the switches 2-3 and 2-4 are periodically turned on by a first signal 2-13 having a fixed period generated by the control means 2-8. A switch 2-3, which is controlled to a state or an off state and is synchronized with the first signal, by a second signal 2-14.
The switch 2-2 is periodically turned on or off so that the switch 2-2 is turned on when the switch is off, and turned off when the switches 2-3 and 2-4 are turned on. And the second signal is input to the delay means 2-12,
By using the output as the third signal for controlling the switch 2-1, the output is delayed from the second signal 2-14,
The switch 2-1 is turned on when the switches 2-3 and 2-4 are off, and turned off when the switches 2-3 and 2-4 are on.
Is periodically controlled to an on state or an off state.

The switches 2-1, 2-2, 2-3, and 2
The timing of -4 is shown in FIG. In this embodiment, as described above, the switch 2-1 and the switch 2-2 do not have the same phase, and the switch 2-1 is delayed.

Now, the output terminal 2- coming from the switch 2-2
Assuming that the magnitude of the noise at 11 is the same as the noise coming from the switch 2-1 and normalizing the magnitude to 1, the switches 2-1 and 2-2 are simultaneously turned on in the conventional example. Then, the noise at the output terminal 2-11 becomes 2.

However, in the case of this embodiment, √2 holds, and
The synergistic effect of noise originating from the switch 2-1 and the switch 2-2 can be eliminated.

Further, as shown in FIG. 10, the MOS type switches have parasitic capacitances 6-4, 6-5, 6-6, 6-7.
Is added. Switches 2-1 and 2-2 as in the prior art
Are turned on at the same time, the potentials at both ends of the switch 2-2 become unequal. As a result, when the charge stored in the first capacitor is transferred to the second capacitor, the parasitic capacitance 6-4 And 6-5, the charge transferred to the second capacitor does not match the charge stored in the first capacitor. This difference results in noise at the output terminal 2-11.

Therefore, as shown in this embodiment, the parasitic capacitances 6-4 and 6-5 are charged by turning on the switch 2-2 before the switch 2-1. Next, when the switch 2-1 is turned on, the first capacitor 2-6 is turned on.
Charge stored in the second capacitor 2-
7 is transferred. As a result, the parasitic capacitances 6-4, 6
The problem of noise at the output terminal 2-11 resulting from -5 is solved.

[0032]

According to the present invention, the switch 3 is delayed with respect to the switch 2 in the case of the normal phase type, and the switch 1 is delayed with respect to the switch 2 in the case of the reverse phase type. The effect can be eliminated, and the S / N ratio can be improved because the parasitic capacitance of the switch 2 does not affect the amplifier.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a positive-phase switched-capacitor integrator according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an inverted-phase switched-capacitor integrator according to a second embodiment of the present invention.

FIG. 3 is a schematic timing diagram of switches 1, 2, 3, and 4 of a positive-phase switched-capacitor integrator according to the first embodiment of the present invention.

FIG. 4 is a schematic timing diagram of switches 1, 2, 3, and 4 of a reversed-phase switched-capacitor integrator according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram showing an amplitude of noise at an output terminal when a switch 2 and a switch 3 of the in-phase type switched capacitor integrator of the present invention are turned on.

FIG. 6 is a schematic diagram showing the amplitude of noise at an output terminal when a switch 2 and a switch 3 of a conventional in-phase type switched capacitor integrator are turned on.

FIG. 7 is a configuration diagram of a conventional positive-phase switched-capacitor integrator.

FIG. 8 is a configuration diagram of a conventional reversed-phase switched-capacitor integrator.

FIG. 9 is a schematic diagram showing a MOS switch.

FIG. 10 is a schematic diagram showing a MOS switch in consideration of a parasitic capacitance;

FIG. 11 is a schematic timing diagram of switches 1, 2, 3, and 4 of a conventional positive-phase switched-capacitor integrator.

FIG. 12 is a schematic timing diagram of switches 1, 2, 3, and 4 of a conventional reversed-phase switched-capacitor integrator.

[Explanation of symbols]

 1-1, 1-2, 1-3, 1-4 switch 2-1, 2-2, 2-3, 2-4 switch 3-1, 3-2, 3-3, 3-4 switch 4- 1, 4-2, 4-3, 4-4 Switch 1-5, 2-5, 3-5, 4-5 Amplifier 1-6, 1-7 Electric capacity 2-6, 2-7 Electric capacity 3- 6, 3-7 Electric capacity 4-6, 4-7 Electric capacity 1-8, 2-8, 3-8, 4-8 Control means 1-9, 2-9, 3-9, 4-9 Constant potential Source 1-10, 2-10, 3-10, 4-10 Input terminal 1-11, 2-11, 3-11, 4-11 Output terminal 1-12, 2-12 Delay means 1-13, 2- 13, 3-12, 4-12 First signal 1-14, 2-14, 3-13, 4-13 Second signal 1-15, 2-15 Third signal 5-1 NMOS 5-2 PMOS 5-3 Inverter 6 -1 second signal 6-2 first capacitor 6-3 second capacitor 6-4, 6-5, 6-6, 6-7 parasitic capacitance

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Seikatsu Maruyama 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-61-109313 (JP, A) JP-A-64-17176 (JP, A) JP-A 1-272312 (JP, A) JP-A 3-117113 (JP, A A) JP-A-4-175891 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06G 7/186 H03H 19/00

Claims (2)

(57) [Claims] 1. A first capacitor, and a switch connected between one end of the first capacitor and an input terminal.
A switch 2 having one end connected to the other end of the first capacitor, a switch 3 connected between one end of the first capacitor and a constant potential source, and a second end of the first capacitor. An impedance circuit composed of a switch 4 connected between the switch and the constant potential source; one end of a second capacitor connected to the other end of the switch 2 of the impedance circuit and an inverting input terminal of an operational amplifier; A switched capacitor integrator having a feedback load circuit having a terminal connected to an output terminal of the operational amplifier and a non-inverting input terminal of the operational amplifier connected to the constant potential source;
The switches 1 and 4 are periodically controlled to be in an on state or an off state by the signal, and are turned on when the switches 1 and 4 are in the off state by a second signal synchronized with the first signal. A control means for periodically controlling the switch 2 to be in an on state or an off state so that the switch 1 is in an off state when the switches 1 and 4 are in an on state;
And delay means for delaying the second signal, and the switch 3 is periodically turned on or off by a third signal output from the delay means. And a switched capacitor integrator. 2. A switch according to claim 1, wherein said first signal controls said switches, said second signal controls said switch, and said third signal controls said switch. Switched capacitor integrator.