JP3131016B2 - Method of forming negative resist pattern - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a negative resist pattern for forming a gate electrode of a semiconductor device.

[0002]

2. Description of the Related Art Recently, miniaturization of a gate length has been promoted in a gallium arsenide (GaAs) IC or the like for speeding up. However, there has been a problem that as the gate length becomes smaller, the resistance becomes larger. In order to solve this, a document: "A novelelectron bea"
m exposure technology for
0.1 μm T-shaped gate fabric
nation "N. Samoto et al. , J. et al.
Vac. Sci. Technol. B8 (6) No
v. / Dec. 1990. , Pp1335 disclose a gate electrode having a T-shaped cross section taken along the gate length direction. FIG. 6 is a perspective view schematically showing this electrode structure. In this gate electrode structure, the gate length L is shortened and the gate width M is increased. As a result, the gate electrode has a T-shaped structure in which the lower layer is narrow and the upper layer is enormous. Such a gate electrode includes a so-called 電極 (gamma) type, a mushroom type and the like in addition to the T-shaped gate electrode.

As a method for producing this type of gate electrode, the above-mentioned document discloses the following method.

That is, as shown in FIG. 7, a lower resist layer 12 is coated with a low molecular weight PMMA (polymethyl methacrylate) having a thickness of 0.25 μm on a base 10, and then a lower resist layer 14 is coated with a thickness of 1 μm. High molecular weight P
MMA is coated (FIG. 7A).

[0005] Next, after exposing only the upper resist layer 14 with an electron beam with an exposure amount, the groove 18 defining the upper layer portion of the gate electrode is formed by developing (FIG. 7B). )).

Next, the lower resist layer 12 is similarly exposed to an electron beam and then developed to form a groove 20 defining a lower layer of the gate electrode (FIG. 7C).

Finally, a metal is deposited to fill the grooves 20 and 18 to form a metal layer 22 (FIG. 8A). Thereafter, the upper resist layer 14 is lifted off.
And an unnecessary portion of the metal layer thereon is peeled off, so that the desired gate pattern 24 (the lower layer portion 24a and the upper layer portion 24a
Indicated by b. ) Is obtained (FIG. 8B).

In this manner, the gate electrode 24 including the lower layer portion 24a for determining the gate length and the upper layer portion 24b having a length larger than the gate length of the lower layer portion is obtained.

[0009]

However, the above-described exposure method using an electron beam has a problem that the apparatus is expensive and the productivity is low.

An object of the present invention is to provide gallium arsenide (GaAs).
s) A negative type for forming a gate electrode having a structure in which the upper layer has a larger volume than the lower layer by using an inexpensive apparatus and increasing the productivity by using a low-cost apparatus for speeding up ICs and the like. An object of the present invention is to provide a method for forming a resist pattern.

[0011]

[0012]

[0013]

According to the present invention, there is provided a gate electrode comprising a lower layer for determining a gate length and an upper layer having a length larger than the gate length of the lower layer. (A) forming an exposed portion and a non-exposed portion on a lower resist layer formed on a base substrate by using a phase shifter method to form a negative resist pattern for forming a negative resist pattern; Forming a mixing prevention layer on the exposed lower resist layer; and (c)
Forming an upper resist layer having a third groove pattern on the mixing preventing layer, the groove bottom being longer than the length of the non-exposed portion in the gate length direction and defining at least a part of the upper layer; (D) removing a portion of the mixing preventing layer exposed to the third groove pattern to form a second groove pattern; and (e) exposing the non-exposed light to the second groove pattern. Removing the portion to form a first groove pattern, thereby forming a gate groove pattern for defining the gate electrode with the first, second, and third groove patterns.

[0014]

According to the structure of the present invention, a negative resist is used.
A lower resist layer is formed, exposed using a phase shifter method, and then developed to form a first groove pattern defining a lower layer portion of the gate electrode. Then, as a step before the development, an intermediate layer is provided as a mixing preventing layer in order to prevent mixing with a negative resist to be applied in the next step. A negative resist is formed thereon again as an upper layer, and the resist is exposed to light using a normal exposure mask and then developed to form a third groove pattern defining an upper layer portion of the gate electrode. Thereafter, the portion of the mixing preventing layer exposed in the third groove pattern is removed, and then the unexposed portion of the lower resist layer is removed to form a second groove pattern. Thus, a negative resist pattern having a gate groove pattern defining the gate electrode by forming the first, second and third groove patterns in communication with each other is formed.

[0015]

As described above, according to the present invention, two negative resist layers are formed, and a mixing preventing layer for both negative resist layers is provided therebetween. Then, the lower resist layer is formed into a fine groove pattern defining a lower layer portion of the gate electrode by a photolithography process using a phase shifter method.
Since the phases of the light passing through the portion where the phase shifter exists and the portion where the phase shifter does not exist are inverted, the light shielding portion can be formed only by the edge of the shifter. That is, an extremely thin linear light-shielding portion can be formed along the edge of the shifter due to a sharp change in light intensity. Here, since a negative resist is used as the resist, an extremely thin linear light-shielding portion is removed as a non-exposed portion, and a fine groove pattern is formed. In addition, a groove pattern defining an enormous upper layer portion of the gate electrode is formed by a photolithography process using an ordinary exposure method on the upper resist layer. Therefore, according to the method of the present invention, a resist pattern for forming a gate electrode having a finer gate length is formed.
It can be formed using an inexpensive device, and the throughput can be further increased.

[0017]

Embodiments of the present invention and reference examples will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the shapes, sizes, and arrangements of the components so that the present invention can be understood. Further, the following Examples and Reference Examples are merely preferred examples. Therefore, numerical values, materials, and other conditions described in these Examples and Reference Examples are merely examples, and are not limited to these exemplified conditions. It is not something to be done.

Reference Example 1 FIG. 1 is a view for explaining a reference example of a negative resist pattern forming method of the present invention. FIG. 1A shows a resist pattern for forming a gate electrode. It is sectional drawing.

FIG. 1B is a cross-sectional view showing a gate electrode having an enormous head formed by using the resist pattern shown in FIG. 1A, for example, a T-type gate electrode.

First, a semiconductor substrate 50 is prepared as a base, and a negative resist layer is applied and formed on one of the main surfaces. Next, the resist layer is exposed by using a phase shifter method to form an exposed portion and a non-exposed portion. Thereafter, development is performed to provide a first groove pattern 54 for defining a lower layer portion of the gate electrode in the resist layer to form a lower resist layer 52. In this case, the material of the resist layer may be any negative resist material. Further, the development for forming the first groove pattern 54 may be performed following the exposure of the negative resist layer, or may be performed in the final step of the negative resist pattern forming step of the present invention. Well. It may be performed at a suitable stage according to the design.

Next, on the lower resist layer 52, a mixing preventing layer 5 for preventing the resist of the layer 52 from mixing with the resist of the upper resist layer formed in a later step.
6 is provided. The mixing prevention layer 56 has a second groove pattern 58 communicating with the first groove pattern 54.
The length of the second groove pattern 58 in the gate length direction is the first length.
The length is set to the length of the groove pattern 54 or more. In order to form the mixing preventing layer 56, first, an appropriate material for preventing mixing is applied to form a film (not shown) having a flat upper surface. If the first groove pattern 54 has already been formed in the lower resist layer 52,
This film is formed so as to fill the groove pattern 54.
Then, after forming an upper resist layer on this upper side,
The second groove pattern 58 may be formed using an appropriate etching process or a peeling process.

Then, an upper resist layer 60 is formed on the mixing preventing layer 56. This upper resist layer 60
Has a third groove pattern 62 for defining an upper layer portion of the gate electrode. The length of the third groove pattern 62 along the gate length direction is made longer than the length of the first groove pattern 54. In order to form the upper resist layer 60, after forming a film with a mixing preventing material, a negative resist material is applied on the upper surface of the film to form a resist layer once. Thereafter, the upper portion of the first groove pattern in the resist layer is exposed to light while shielding light over a wider range than the length of the first groove pattern along the gate length direction. Then, the third groove pattern 62 is formed by developing the resist layer.

After forming the third groove pattern 62, the groove 62
The second groove pattern 58 is formed by removing or removing the mixing prevention layer 56 which is exposed to the outside. After that, if the first groove pattern 54 has already been formed and the mixing prevention material is embedded in the groove 54,
The first groove pattern 54 is recovered by removing the mixing preventing material at the same time as the above-described etching removal or peeling. Alternatively, if the first groove pattern 54 remains unexposed, the second groove pattern 58 is formed and then the first groove pattern 5 is developed by developing the unexposed portion.
4 is formed. Thus, finally, FIG.
A negative resist pattern as shown in FIG.
Can be formed on.

The negative resist pattern 6 shown in FIG.
After vapor deposition using an appropriate gate metal material according to the design on 4, the upper resist layer 60 and the lower resist layer 52 are removed by a lift-off method to obtain a gate electrode 68. The gate electrode 68 is connected to the lower layer 6
8a and an upper layer portion 68b (FIG. 1B).

Thus, a negative resist pattern having a required groove pattern can be formed by two photolithography steps, one mixing-preventing layer forming step, and the etching-removing step of the mixing-preventing layer.
Therefore, a negative resist pattern can be formed with high productivity using an inexpensive apparatus.

<Reference Example 2> Next, a second reference example of the present invention will be described more specifically. (A) to (D) of FIG. 2 and (A) to (A) of FIG.
(C) is a process diagram provided for explanation of the second reference example. Each figure shows a cross section of the structure obtained in the main process step, which is cut along the gate length direction.

First, a GaAs substrate 50 is used as a semiconductor base.
Is prepared, and a wafer alignment mark is formed thereon (not shown).

Next, a first groove pattern 54 for defining the lower part of the gate electrode is formed in the lower resist layer 52 on the substrate 50 by a phase shifter method. For this reason,
The first resist layer 70 is coated with a thickness of about 0.3 μm. As the negative resist material of the first resist layer 70, for example, FSMR (FSMR is a trade name of Fuji Pharmaceutical Co., Ltd.) is used. Next, this structure was baked on a hot plate at 70 ° C. for 140 seconds to obtain a structure shown in FIG.
(A) is obtained.

Next, the baked first resist layer 70
(Reduction projection exposure apparatus) RA
Set to 101-VL (manufactured by Hitachi, Ltd.). A phase difference mask is used as an exposure mask used for this stepper. In particular, in this reference example, it is preferable to form a light-shielding pattern, that is, a non-exposed portion (also referred to as an unexposed portion) on the first resist layer 70 using the edge of the shifter of the phase difference mask. According to this method, a fine light-shielding pattern can be obtained. Next, in this reference example, the first
After exposing the resist layer 70 for 0.5 second, the FSMR
The non-exposed part is removed by developing the resist with a developing solution. As a result, the first groove pattern 5 is formed in the first resist layer 70.
4 is formed, and a lower resist layer 52 is obtained. The first groove pattern 54 is also called a well. A structure having a lower resist layer 52 on a substrate 50 is shown in FIG.

Next, in order to form a mixing prevention layer 56 on the substrate 50 including the lower resist layer 52, PVA (polyvinyl alcohol) is spin-coated to a thickness of about 0.05 μm as a mixing prevention material (FIG. 2). (C)). The surface of the mixing preventing layer 56 is made flat. Then, the mixing prevention layer 56 can prevent the respective resists of the upper resist layer and the lower resist layer 52 formed thereon in a later step from being mixed. At this time, the separation of the mixing prevention layer 56 is not performed.

Subsequently, a second resist layer 72 is formed on the mixing preventing layer 56. In this example,
The resist material in this case is also formed by spin coating using the above-mentioned FSMR with a layer thickness of about 0.5 μm. Thereafter, the second resist layer 72 is heated to about 70 ° C.
Baking for about 140 seconds (FIG. 2D).

Next, a third groove pattern 62 for defining at least a part of the upper layer of the gate electrode is formed on the second resist layer 72. Therefore, a phase difference mask or a mask provided with a normal light-shielding pattern is mounted on a stepper of the same type as the above-described stepper, and the second resist layer 72 is exposed for 0.5 second.
Bake at a temperature of ° C. for about 140 seconds.

By this exposure, a non-exposed portion 74 and an exposed portion 76 are formed in the second resist layer 72. In this case, the length of the non-exposed portion 74 at the portion in contact with the mixing prevention layer 56 is longer than the length of the first groove pattern 54 in the direction along the gate length direction.
Is preferably exposed so as to completely cover the first groove pattern in the gate length direction. FIG. 3A shows the state of the second resist layer 72 after this exposure.

Subsequently, the FSMR developer was used for 40 seconds.
The exposed second resist layer 72 is developed and rinsed with pure water for 30 seconds to form a third groove pattern 62 (FIG. 3B). The third groove pattern 62 is also called a well. The resist layer on which the third groove pattern 62 has been formed in this manner is referred to as an upper resist layer 60.

Next, the portion of the mixing preventing layer 56 exposed in the third groove pattern 62 is removed. In this reference example, this removal is performed by peeling off by washing with water. At this time, the upper resist layer 60 and the lower resist layer 5
A part of the mixing prevention layer 56 sandwiched between the second resist pattern 60 and the second groove pattern 54 is also slightly removed so as to bite below the upper resist layer 60 in the lateral direction. Is also removed. By this removal, a second groove pattern 58 is formed. Thus, the first, second and third groove patterns 54, 58 and 62 communicate with each other. In the reference example, the second groove pattern 58 also defines a part of the upper layer of the gate electrode. The gate groove pattern 80 is obtained as described above. A negative resist pattern including the gate groove pattern 80 is indicated by 82 (FIG. 3C).

Finally, a metal deposition apparatus EVC-1501
A structure provided with a negative resist pattern 80 on a semiconductor base 50 is set in a (Nidec Anelva Co.), and aluminum (Al) is made to have a thickness of about 6000 A ° (angstrom) on a plane by, for example, electron beam evaporation. Vapor deposition is performed. Next, the structure on which the vapor deposition layer (not shown) is formed is immersed in, for example, dimethylformamide solution for about 10 minutes, and then a gate electrode pattern 68 is formed by lift-off (FIG. 3D). The lower layer portion of the gate electrode 68 is indicated by 68a, and the upper layer portion is indicated by 68b. In this manner, by using the negative resist pattern formed according to the present invention, it is possible to form a gate electrode whose head is larger than its lower part in a cross-sectional view along the gate length direction. In addition, when the metal is deposited, it does not penetrate even to a slight biting portion on both sides of the second groove.

<Example> Next, an example of the present invention will be described. FIGS. 4 and 5 are views for explaining a step of forming a negative resist pattern for forming a T-shaped gate electrode, as in the second reference example. Each drawing is represented by a cross section cut along the gate length direction as in FIGS. 2 and 3.

In the drawings, the same components as those shown in FIGS. 2 and 3 are denoted by the same reference numerals.

First, as in the process of FIG.
After forming a wafer alignment mark (not shown) on the aAs substrate 50, the first resist layer 7
0 is formed. This layer 70 is formed by coating FSMR (manufactured by Fuji Pharmaceutical Co., Ltd.) with a thickness of 0.3 μm and baking it at 70 ° C. for 140 seconds on a hot plate (FIG. 4A).

Next, the substrate 50 having the first resist layer 70 is set on a stepper RA101-VLII (manufactured by Hitachi, Ltd.) in the same manner as in the step of FIG.
Exposure is performed by the phase shifter method. Also in this case, a phase difference mask is used. The exposure in this case is performed for about 0.5 seconds, and the exposed portion 52a and the unexposed portion 52 are formed on the first resist layer 70.
b is formed (FIG. 4B). In this exposure, the pattern of the unexposed portion is preferably formed by using the edge of the shifter of the phase difference mask. In this manner, a light-shielding pattern having a fine length in the gate length direction can be formed.

Next, in order to prevent mixing with FSMR which is a resist material of the second resist layer applied to the base 50 in the next step, PVA is used as a mixing preventing material.
(Polyvinyl alcohol) is spin-coated on the first resist layer 70 to a thickness of about 0.05 μm,
6 is formed (FIG. 4C).

Subsequently, an upper resist layer 60 having a third groove pattern 62 is formed on the mixing preventing layer 56 (FIG. 5B). Therefore, in this embodiment, first, FSMR is applied as a negative resist material to a thickness of about 0.5 μm by spin coating to form a second resist layer 72 (FIG. 4D). Subsequently, after baking the second resist layer 72 at about 70 ° C. for about 140 seconds, the second resist layer 72 is baked with respect to FIG.
Exposure is performed by a method similar to that described above. In this way, a structure as shown in FIG. In the figure, reference numeral 76 denotes an exposed portion, and 74 denotes a non-exposed portion (also referred to as an unexposed portion). In this case, the unexposed portion 74
The length of the portion in contact with the mixing prevention layer 56 in the gate length direction is the length of the unexposed portion 52 of the first resist layer 52.
It is preferable that the length be longer than the length b and that the unexposed portion 52b be completely covered in the gate length direction. FIG. 5A shows such a state.

Subsequently, in the same manner as described with reference to FIG. 3B, the second resist layer 72 is developed with an FSMR developer for 40 seconds, and further rinsed with pure water for 30 seconds to form a third groove pattern. (Also referred to as a well) 62 (FIG. 5)
(B)). Thus, an upper resist layer 60 having a resist groove pattern defining at least a part of the upper layer of the gate electrode is obtained.

Next, the mixing preventing layer 56 exposed in the third groove pattern 62 is peeled off by washing with water to form a second groove pattern 58. The second groove pattern 58 is formed in a state in which the second groove pattern 58 extends slightly to the lower side of the upper resist layer 60 in the lateral direction, as described in the second reference example. Subsequently, the unexposed portion 52 of the lower resist layer 52 is formed.
b is removed with an FSMR developer to form a first groove pattern 5
4 is formed. As a result, a negative resist pattern 82 having a gate groove pattern 80 in which the first, second, and third groove patterns 54, 58, and 62 communicate is obtained (FIG. 5).
(C)).

In this embodiment, the second groove pattern 58 also defines a part of the upper layer of the gate electrode. Further, the first groove pattern 54 defines a lower layer portion of the gate electrode.

Finally, aluminum (Al) is deposited to a thickness of 6000 ° (angstrom) on a plane by the same electron beam evaporation method as described in the second reference example. Next, the resist layers 60 and 52, which are the bases of the vapor deposition layer, are immersed in a dimethylformamide solution for about 10 minutes, and then lift-off is performed so that the lower layer 68a and the upper layer 68
A gate pattern 68 of b is formed (FIG. 5D).

It is clear that the present invention is not limited to the embodiments described above, but that many variations or modifications can be made. For example, in the above-described embodiment, a method of forming a negative resist pattern for forming a gate electrode having a T-shaped cross section has been described. The present invention can be applied to any resist pattern. Numerical values, materials, and other conditions can be appropriately modified according to the design.

Further, in the above-described embodiment, the phase shifter method using the mask including the edge has been described. However, it is obvious that another phase shifter method may be used depending on the design.

[0049]

As is clear from the above description, according to the method for forming a negative resist pattern of the present invention, the method of
Resist coating two times, photolithography by two exposure methods, one formation of a mixing prevention layer, and its removal, it is possible to use a negative resist pattern having a required groove pattern by using a cheaper apparatus than before. Becomes possible,
Moreover, productivity is improved. Therefore, according to the present invention,
By a simple process, a T-shaped gate electrode having a gate length of 0.2 μm or less can be easily formed.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic first reference example of a method for forming a negative resist pattern according to the present invention.

FIG. 2 is a first half process diagram illustrating a second reference example of the method for forming a negative resist pattern according to the present invention;

FIG. 3 is a process drawing following FIG. 2;

FIG. 4 is a first half process diagram illustrating an embodiment of a method for forming a negative resist pattern according to the present invention;

FIG. 5 is a process drawing following FIG. 4;

FIG. 6 is an explanatory diagram of the present invention and a conventional gate electrode.

FIG. 7 is a first half process diagram for explaining a conventional method of forming a resist turn for forming a gate electrode.

FIG. 8 is a process drawing following FIG. 7;

[Explanation of symbols]

 10: Underlayer (substrate) 12: Lower resist layer 14: Upper resist layer 18: Upper groove 20: Lower groove 22: Deposited metal 24: Gate electrode 24a: Lower gate electrode 24b: Upper gate electrode 50: Semiconductor substrate 52: Lower resist layer 54: First groove pattern 56: Mixing prevention layer 58: Second groove pattern 60: Upper layer resist layer 62: Third groove pattern 64: Negative resist pattern 68: Gate electrode 68a: Gate electrode lower part 68b: Gate electrode Upper part 70: first resist layer 72: second resist layer 74: non-exposed part 76: exposed part

Continuation of the front page (56) References JP-A-2-46738 (JP, A) JP-A-2-65140 (JP, A) JP-A-2-65139 (JP, A) JP-A-3-177784 (JP) (A) JP-A-2-191347 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 21/027 H01L 21/28 H01L 29/812

Claims (1)

(57) [Claims] In forming a negative resist pattern for forming a gate electrode including a lower layer portion for determining a gate length and an upper layer portion having a length longer than the gate length of the lower layer portion: (B) forming an exposed portion and a non-exposed portion on the lower resist layer formed on the substrate by using a phase shifter method, and (b) forming a mixing prevention layer on the exposed lower resist layer; c) On the mixing preventing layer, an upper resist layer having a third groove pattern for defining at least a portion of the upper layer portion, the groove bottom portion being larger than the length of the unexposed portion in the gate length direction is formed. (D) removing the portion of the mixing preventing layer exposed to the third groove pattern to form a second groove pattern; and (e) exposing the second groove pattern to the second groove pattern. Non-dew Forming a first groove pattern by removing the portion, thus the first, second
And forming a gate groove pattern for defining the gate electrode with a third groove pattern.