JP3131266B2 - NV-DRAM device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile random access memory device, that is, an NV-DRAM (Non-VRAM).
olite Random Access Mem
ory) device, for example , a volatile memory cell (DR)
AM; Dynamic RAM) and a non-volatile memory cell (EEPRO) using a floating gate circuit element.
M; Electrically Erasable P
programmable Read Only Mem
or the NV-DRAM device configured by combining the two.

[0002]

2. Description of the Related Art An example of this type of NV-DRAM device has been proposed by the present applicant in Japanese Patent Application No. 2-202958. The configuration will be described below together with the operation.

As shown in FIG. 5, this NV-DRAM device comprises a memory array 1, a read / write timing circuit 4, a recall timing circuit 5, a store timing circuit 6, and an external input signal. And an input circuit 11 for receiving and converting the level. The operating state holding means includes a recall store logic circuit 9.
And a recall / store / latch circuit 10, and further includes a power supply voltage monitoring circuit 12.

The memory array 1 is configured by arranging on a chip memory cells formed by combining a DRAM section 1a and an EEPROM section 1b. The read / write timing circuit 4 includes a bar CE (bar chip enable) signal externally input via the input circuit 11 and a bar NE.
(Vernon volatile enable) signal, bar OE
(Bar output enable) signal and bar WE
(Bar write enable) signal, the DRAM of each memory cell of the memory array 1 is determined based on the level ("H" level or "L" level) of each of these input signals.
Reading, writing, or refreshing of the data of the section 1a is performed sequentially.

Each memory cell to be read, written and refreshed by the read / write timing circuit 4 is designated by an address counter 8 updated by a timer 7 or an external address (for example, an external address pad). Specifically, when a recall enable signal REC and a store enable signal STR, which will be described later, are not latched in the recall store latch circuit 10, the signal CE, the signal OE, and the signal WE are each at "L". , "L", and "H" levels, the read operation is performed, and when the "L", "H", and "L" levels are obtained, the write operation is performed.
The refresh operation is performed when "L", "H", and "H" are taken, respectively.

The recall timing circuit 5 is used when the recall enable signal REC is held in the recall store latch circuit 10 and the signal CE signal,
When the OE signal becomes “H” and “L”, respectively, the recall operation of each memory cell of the memory array 1 is sequentially performed. This recall operation is performed for each page in units of word lines specified by the address counter 8.

[0007] The store timing circuit 6 has a recall
Upon receiving the store enable signal STR from the store latch circuit 10, the store operation of each memory cell of the memory array 1 is performed collectively based on the generation timing of the store enable signal STR. Then, store the timing circuit 6 when the store operation is completed, the output at that time the store operation end pulse phi ₂ to recall store latch circuit 10.

[0008] power supply voltage monitoring circuit 12, to the recall store latch circuit 10, while outputting the power ON detection pulse phi ₁ indicating that should be performed when the power is turned ON recall operation, the power supply potential below a certain value outputs the power OFF detection signal phi ₃ indicating that when lowered (including at power OFF) to perform the store operation. The power supply voltage monitoring circuit 12 is realized by, for example, the configuration shown in FIG.

That is, NMO is connected between the power supply and GND.
The S transistors 161 and 162 and the resistor 163 are connected in series in this order, and the resistor 164 and the NMOS transistor 165 are connected in order. Furthermore, to connect the connection point J ₁ of the NMOS transistor 162 and a resistor 163 to the gate of the NMOS transistor 165, resistor 164 Toko of NM
Inverter to the connection point J ₂ of the OS transistor 165 1
66 and 167 are connected.

[0010] In the circuit configuration described above, in the power OFF state NMOS transistor 165 has OFF, the potential at the connection point J ₂ is at the GND level. When the power supply potential from this state rises, the potential at the connection point J ₂ rises immediately. Then the potential of the connection point J ₁ NMOS transistor 161 is turned ON by rises, thereby NMO
When the S transistor 165 turns ON, the potential at the connection point J ₂ becomes G
Return to ND level. Therefore, the inverters 166, 167
, The power ON detection pulse φ ₁ can be output to the recall / store latch circuit 10.

[0011] The recall store logic circuit 9 includes a bar CE signal input from the outside through the input circuit 11,
In response to the NE signal, the OE signal, and the WE signal, these input signals become "H", "L", "
When the level becomes H or L, a store operation start signal φ ₄ indicating that the store operation should be started is output to the recall / store latch circuit 10.

Each of the above input signals is "
L "," H "," H "," H recall indicating that it should end the recall operation when taking the level of the "latch-reset signal phi ₅ recall store latch circuit 10
Output to Further, each of the above input signals is "
H "," L "," L "," outputs the recall latch set signal phi ₆ indicating that should begin recall operation when taking the level of H "to recall store latch circuit 10. These Each of the signals φ ₄ , φ ₅ and φ ₆ is a relatively short pulse signal.

FIG. 7 shows a recall store latch circuit 10.
The details are shown below. The recall store latch circuit 10
Store latch unit 110 and recall latch circuit unit 1
30. The details of each part will be described below together with the operation.

The store / latch unit 110 includes the inverter 1
13, 114 are connected in anti-parallel, and these inverters 1
The power supply ON detection pulse φ ₁ and the NMOS transistors 111 and 112 driven by the store operation end pulse φ ₂ are connected between the connection point J ₃ between the connection points ₁₃ and 114 and GND, while the other connection point J ₄ is connected. Between power supply and GND
NMOS driven by the FF detection signal φ ₃ and the store operation start signal φ ₄ via the pulse generation circuits 117 and 118
The transistors 115 and 116 are connected to each other.

The connection point J ₄ is connected to the inverter 119 and the NAND
(Negative AND) A circuit 121 and an inverter 122 are connected to the output terminal T ₁ of the store / latch unit 110. GND level connection point J ₃ when the inverter 113 and 114 to the power supply ON detection pulse phi ₁ or store operation end pulse phi ₂ is entered, the connection point J ₄ power level (V
_(CC level). Also, the power-off detection signal φ ₃
Or a store operation start signal phi ₄ power level connection point J3 when the inputted holds the connection point J ₄ to the GND level.

The NANAD circuit 121 inverts the level of the connection point J ₄ via the inverter 119 and receives the inverted recall enable signal REC from the recall latch unit 130 via the inverter 120. Operate. Therefore, the store / latch unit 11
0 indicates that the recall enable signal REC from the recall latch unit 130 is not output (“L” level)
Only when the store enable signal STR ("H" level)
Can hold the output terminal T _1.

The details of the recall latch 130 are as follows. Connect the inverter 139 and 140 in anti-parallel connection point J ₅ and GN between the inverters 139 and 140
D, a pulse generation circuit 135 by a recall / latch / reset signal φ ₅ and a store operation start signal φ ₄ .
NMOS transistor 13 driven via 136
9, 138 are connected respectively. In addition, an NMOS transistor 141 driven by a store operation end pulse φ ₂ , a power ON detection pulse φ ₁ , and a recall latch set signal φ ₆ is provided between the other connection point J ₆ and GND.
142 and 143 are connected.

The connection point J ₆ is connected to the inverter 134 and the NAND
This recall is performed through a circuit 132 and an inverter 131
It is connected to the output terminal T ₂ of the latch 130. Inverter 139 and 140 holds the connection point J ₅ when the recall latch reset signal phi ₅ or store operation start signal phi ₄ is input GND, the connection point J ₆ to the power supply level. When the store operation end pulse φ ₂ , the power ON detection pulse φ ₁ or the recall latch set signal φ ₆ is input, the connection point J _{5 is set} to the power supply level, and the connection point J _{6 is set} to GN.
Hold at D level.

The NANAD circuit 132 inverts and receives the level of the connection point J ₆ via the inverter 134, and inverts and receives the store enable signal STR from the store / latch unit 110 via the inverter 133. Works. Therefore, the recall latch unit 13
0 can hold a store enable signal STR is not output from the store latch section 110 ( "L" level) only when the recall signal ( "H" level) to the output terminal T _2.

The recall enable signal REC and the store enable signal STR are output to the recall timing circuit 5 and the store timing circuit 6 as shown in FIG.
1 to the read / write timing circuit 4. Thus, when the recall enable signal REC is held at the output terminal T _2, or the store when the enable signal STR is held at the output terminal T _1, or recall enable signal REC and the store enable signal One of the three timing circuits 4, 5, and 6, ie, the recall timing circuit 6, the store timing circuit 5, and the read Only one operation of the write timing circuit 4 is permitted, and the operation of the remaining two timing circuits is prohibited.

As described above, in the NV-DRAM device previously proposed by the present applicant, once the recall operation is selected, the recall store latch circuit 10, which is an internal recall latch circuit, outputs a bar control signal, which is an external control signal. CE signal,
The configuration is such that the recall state is maintained until reset by the NE signal, the OE signal, the WE signal, or the like.

[0022]

Here, in order to protect data stored in the EEPROM unit 1b from an unintended store operation, a recall operation is performed over all desired memory areas of the memory array 1 when the power is turned on. It is necessary to do.

By the way, the NV proposed by the applicant of the present invention has been proposed.
-In the DRAM device, the power supply voltage monitoring circuit 1
Recall store latch circuit sets 10 by the power supply ON detection pulse phi _1, which is detected by the two, bars CE
Recall / store latch circuit 1 by an external control signal such as
Until resetting 0, the recall state is maintained, and the recalled data does not appear on the output pad, and the recalled data is designed to appear on the output pad only by the read operation from the DRAM unit 1a. ing.

In a system using a large number of such NV-DRAM devices, once the recall / store latch circuit 10 is set at power-on, as described above, all NV-DRAM devices are recalled by an external control signal. Until the store latch circuit is reset, the system will have a state in which NV-DRAM devices performing a recall operation and a DRAM operation (or a store operation) coexist.

By the way, in such a system,
In order to improve the usability, a recall operation of all desired memory areas is performed when the power is turned on, and after the recall operation is completed, the recall / latch state is automatically released.
It is preferable to have a system configuration in which all NV-DRAM devices in the system perform a DRAM operation state (including a refresh state). The reason is shown below.

Since the DRAM has been more widely used in the past than the NV-DRAM, it is preferable to use the DRAM in order to improve versatility and the like.

Generally, the cycle time is different between the recall operation and the DRAM operation.
This is because when DRAM devices are mixed, a waste time is generated, and efficient operation of the system cannot be expected.

For the above reasons, the conventional NV-D
At present, there is a limit in improving the usability of a system incorporating a plurality of RAM devices.

The present invention solves the above-mentioned problems of the prior art. When incorporated in a system, the NV-DRAM can greatly improve the usability of the system.
It is intended to provide a device.

[0030]

SUMMARY OF THE INVENTION NV-DRAM of the present invention
In an NV-DRAM device including a memory cell having volatile memory means and nonvolatile memory means, a latch circuit for storing a recall state and a means for setting the latch circuit in response to power-on An internal address counter circuit as determination means for determining the end of the recall operation; a means for resetting the internal address counter circuit in response to power-on; and an output state of the internal address counter circuit. Means for resetting the latch circuit is provided, whereby the object is achieved.

Further, the NV-DRAM device according to the present invention is an NV-DRAM device having a memory cell having a volatile memory means and a nonvolatile memory means, wherein a latch circuit for storing a recall state and a power-on state are provided. Means for setting the latch circuit accordingly, and termination of the recall operation
An internal counter circuit as counting means for determining whether
Means for resetting the internal counter circuit in response to power-on, and means for resetting the latch circuit in accordance with the output state of the internal counter circuit. Is achieved.

[0032]

[0033]

[Action] As described above, to determine the recall operation terminated by an internal address counter circuit, or by the internal counter circuitry to determine the recall operation end, according to the configuration to reset more latch circuits in the determination result, bar CE The latch circuit can be automatically reset without depending on an external control signal such as a signal.

Therefore, when applied to a system in which a plurality of NV-DRAM devices are incorporated, all NV-DRA
Since the recall operation of the M device is automatically reset at the same time, NV-DRAM devices performing the recall operation and the DRAM operation (or the store operation) are not mixed in the system, and the usability of the system can be improved.

[0035]

Embodiments of the present invention will be described below.

The entire structure of the NV-DRAM device of the present invention is the same as that of the NV-DRAM device shown in FIG.
Since the configuration is the same as that of the DRAM device, the description of the overall configuration is omitted. Corresponding portions of the recall / store / latch circuit are denoted by the same reference numerals, and only different portions will be described below.

FIG. 1 shows a recall store latch circuit 10 of the NV-DRAM device of the present invention. This recall store / latch circuit 10 is similar to the recall store / latch circuit 10 shown in FIG.
3 , 144 and a pulse generation circuit 145 are added. More specifically, the NMOS transistor 123
Are connected in parallel to the NMOS transistor 111 of the store / latch unit 110. The pulse generation circuit 145 is connected in parallel to the pulse generation circuit 135 of the recall / latch unit 130, and the reset pulse, which is the output pulse of the pulse generation circuit 145, is added to the newly added N
MOS transistor (transistor for reset) 14
4 gates.

The pulse generation circuit 145 normally supplies a GND level potential to the gate of the NMOS transistor 144, similarly to the pulse generation circuits 135 and 136, and receives a latch / reset signal from an internal address counter circuit 200 described later. When φ8 is applied, the power supply potential (Vcc level) is applied to the gate of the NMOS transistor 144.
In a short pulse waveform to reset the recall store latch circuit 10. FIG. 2 shows the internal address counter circuit 200. Note that the internal address counter times
The path 200 is used for refresh
Dresses are generated sequentially.

This internal address counter circuit 200
Uses the inverted signal of the power-on detection pulse φ1 shown in FIG. 5 as a reset signal, and outputs the output of the internal address counter circuit 200 when the power is turned on, that is, all the load counters CN constituting the internal address counter circuit 200.
The outputs of T _{1 to} CNT _n are reset to “0”, and from this state, every time the recall operation of the memory cell of the memory array 1 is repeated, the internal address counter circuit 200 counts up, and all the load counters CNT ₁
When to CNT _n, the state of the output address becomes "1", A is connected to the internal address counter circuit 200
The output φ8 of the ND circuit 280 is changed from “0” to “1”, and the latch / reset signal φ8 for notifying the pulse generation circuit 145 of the reset state of the recall operation is output.

That is, the internal address counter circuit 200 functions as a judging means for judging the end of the recall operation, and the recall store latch circuit 10 is reset according to the output state.

The internal address counter circuit 200 will be described below.
Will be described in detail. The address counter circuit 200 includes n load counters CNT _{1 to} CNT _n connected in cascade, and outputs _n 270 corresponding to A _{1 to} An.
Constructs a bit counter.

Each counter 210 has an output Q, a data input DATA, a clock (CK) input, a load signal (LD) input, and a set signal (SET) input. Counter CNT corresponding to the highest address
Except for _n, the output Q of the counter CNT ₁ ~CNT _n-1 are connected in the subsequent counter clock (bar CK) input, respectively.

[0043] In such a configuration, every time the clock count-up signal 230 to the (bar CK) input is input, the output A ₁ to A _n of each counter CNT ₁ to CNT _n is incremented by one. Also, the load signal (bar L
D) Each time 240 goes low, the input (AD _PD1
ＡＤAD _PDn ) 250 are loaded into outputs A _{1 to An} 20 respectively. These outputs (A ₁ -A _n ) 270 are decoded, and when all the output address states become “1”, the output φ8 of the AND circuit 280 is changed from “0” to “1”.
To change. It sets the output A ₁ to A _n to logic 0 by the last set signal bar SET "L" level.

In the case of the above embodiment, when the power is ON, the internal address counter circuit 200 to determine whether the recall operation is completed, confirming the completion by the internal address counter circuit 200 The generated latch / reset signal φ8 is supplied to the pulse generation circuit 1
45, whereby the recall operation is reset, so that all the desired memory areas are recalled after the power is turned on, and the recall / store / latch circuit 10 is automatically reset when the recall operation is completed. Therefore, when applied to a system in which a plurality of such NV-DRAM devices are incorporated, as in the conventional example, the bar CE is used.
It is not necessary to reset the recall / store / latch circuit 10 of each NV-DRAM device by an external control signal such as that described above, which greatly contributes to improvement of the usability of the system.

FIG. 3 shows another embodiment of the present invention. In this embodiment, the internal address counter circuit 200 above consisting of n counter CNT ₁ to CNT _n, added to the counter CNT _{n + 1} of one more, the counter CNT
Output φ8 of _{n + 1} (highest address) changes from “0” to “1”
, That is, the internal address counter circuit 2
00 changes from the address “00H” to “FFH”, the recall operation of all addresses is completed, and the internal address
When the counter circuit 200 counts up, the recall store latch circuit 10 is reset to reset the recall operation.

To explain a little more, also in this embodiment,
Using an inverted signal of the power supply ON detection pulse φ1 shown in FIG. 5 as a reset signal of the internal address counter circuit 200, the respective counters CNT ₁ ~CNT _{n + 1} output of the internal address counter circuit 200 when the power ON to "0" Reset, and each time the recall operation is repeated from this state,
The internal address counter circuit 200 counts up and resets the recall store latch circuit 10 when the output φ8 of the counter CNT _{n + 1} changes from “0” to “1”.

Parts corresponding to those in the embodiment shown in FIG. 2 are assigned the same reference numerals, and detailed description thereof is omitted.

FIG. 4 shows another embodiment of the present invention.
In this embodiment, apart from the internal address counter circuit 200 shown in FIG. 2, another set of another counter circuit 2 for counting the number of recall operations repeated by itself is provided.
5 is used as a reset signal for the counter circuit 200 'as an inversion signal of the power ON detection pulse φ1 shown in FIG. 5, and when the power is turned on, n + 1 counters CNT _{1 to} CNT constituting the counter circuit 200' are prepared. The output state of _{n + 1} is reset to "0", and each time the recall operation is repeated, the counter circuit 200 'counts up, and the internal address counter circuit 200 shown in FIG. When all "FFH" have been generated, the output φ8 of the counter circuit 200 'for measuring the number of recall operation repetitions is changed from "0" to "1" to reset the recall store latch circuit 10 described above. Configuration.

In this embodiment, the parts corresponding to those in the above-mentioned embodiment are given numbers with dashes, and the details are omitted.

[0050]

The present invention described above NV-DRAM device according to the present invention determines the recall operation end by an internal address counter circuit, or the recall operation end by the internal counter circuit
It discriminated, since a configuration to reset the more latch circuits in the judgment result, can automatically reset the latch circuit regardless of the external control signals such as bar CE signal.

Therefore, when applied to a system in which a plurality of NV-DRAM devices are incorporated, all NV-DRA
Since the recall operation of the M device is automatically reset at the same time, NV-DRAM devices that perform the recall operation and the DRAM operation (or the store operation) do not coexist in the system, and the usability of the system can be remarkably improved. .

[0052]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a recall store latch circuit of an NV-DRAM device of the present invention.

FIG. 2 is a circuit diagram showing an internal address counter circuit of the NV-DRAM device of the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the internal address counter circuit.

FIG. 4 is a circuit diagram showing a counter circuit according to another embodiment of the NV-DRAM device of the present invention.

FIG. 5 is a block diagram showing the overall configuration of an NV-DRAM device previously proposed by the present applicant.

FIG. 6 is a circuit diagram illustrating an example of a power supply voltage monitoring circuit.

FIG. 7 is a circuit diagram showing a recall store latch circuit of the NV-DRAM device shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 memory array 1a DRAM section 1b EEPROM section 10 recall store latch circuit 110 store latch section 130 recall latch section 144 NMOS transistor 145 pulse generation circuit 200 internal address counter circuit 210 counter 280 AND circuit φ1 power ON detection pulse φ2 Store operation end pulse φ3 Power off detection signal φ4 Store operation start signal φ5 Recall latch reset signal φ6 Recall latch set signal φ7 Store latch reset signal φ8 Recall reset signal REC Recall latch enable output signal STR Store・ Latch enable signal φ8 Latch reset signal

Claims (2)

(57) [Claims] In an NV-DRAM device including a memory cell having volatile memory means and nonvolatile memory means, a latch circuit for storing a recall state and a set of the latch circuit in response to power-on are provided. Means for determining whether the recall operation has been completed, means for determining the end of the recall operation, means for resetting the internal address counter circuit in response to power-on, and means for resetting the output state of the internal address counter circuit. Means for resetting the latch circuit in response to the request. 2. An NV-DRAM device comprising a memory cell having volatile memory means and nonvolatile memory means, a latch circuit for storing a recall state, and a set of said latch circuit in response to power-on. An internal counter circuit as counting means for determining the end of the recall operation; a means for resetting the internal counter circuit in response to power-on; and an operation of the latch circuit in response to an output state of the internal counter circuit. An NV-DRAM device comprising: means for resetting.