JP3131789B2 - Memory card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card used as an external memory device of information equipment such as an electronic still camera, a personal computer, and a word processor.
More particularly, the present invention relates to a memory card capable of storing still image data and a large amount of data.

[0002]

2. Description of the Related Art Recently, IC memory cards have been widely used in various technical fields. For example, IC memory cards may be used outside of information devices such as electronic still cameras, personal computers, and word processors. Used as a memory device. Regarding this IC memory card, for example, from the "Japan Electronics Industry Development Association", "IC Memory Card Guidelines (standard specification of memory card / pin connector for personal computer)", version 3 (May 1989) Mon) is proposed as the latest one. Conventionally, an IC memory card has a direct connection bus system in which input / output pins of an internal IC memory chip can be directly specified as interface signals.
An I / O bus system that can be easily connected to the input / output bus of the microcomputer is adopted. However, the former has a large number of pins and is difficult to connect to the input / output bus.
The bus system is often used.

The I / O bus type memory card has a built-in address register for indicating an arbitrary address of the internal memory chip. In the I / O bus system shown in version 3 of the above-mentioned guideline, this register has three bytes, and two bits are assigned to specify the three-byte register. This 2
Regarding the bits, address 0 (“0” “0”) is the lower address register, address 1 (“0” “1”) is the middle address register, and address 2 (“ 1 "" 0 ") are used to specify the upper address register. In addition, the third address (“1”
"1") is a memory access register, which is designated as "read" or "write" to read and write to the memory at the address specified by the address register. It can be performed.

However, since the conventional address register is 3 bytes (1 byte = 8 bits) as described above, the maximum address that can be represented is "2" to the 24th power, and 1
You can only specify up to addresses 6,777,216. In other words, this memory card can only have a storage capacity of 16 megabytes. As described above, in order to specify the 3-byte register, only two lines are required as the address lines.

[0005]

As described above, the conventional I / O bus type memory card according to the above guideline is used.
In the case of the flash memory, there is only a storage capacity of a maximum of 16 megabytes, and there is a disadvantage that the capacity becomes insufficient when used as a medium for storing a large amount of data such as an electronic still camera. In order to secure a storage capacity of 16 megabytes or more, it is conceivable to add an address register in the IC memory card. For example, if the address register is 4 bytes, the maximum address that can be handled is 2 32 = 4,294,967,29
Up to address 6, a large memory capacity can be handled. However, in this case, the number of control registers is required five, and eventually the number of pins is required three.
There is a disadvantage that the number of pins of the IC memory card increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory card which solves the above-mentioned drawbacks and can greatly increase the storage capacity without increasing the number of pins.

[0007]

To achieve the above object Means for Solving the Problems] In the present invention, Memorika is used by connecting to a fixed information device - in de various de - make storing data <br/> common A memory, an attribute memory for storing physical information of a card including a memory capacity of the common memory, and an attribute of the common memory and the attribute memory.
It includes an address register for specifying a dress, this
A control circuit for controlling writing / reading of these two memories , and further comprising:
For signals C0 and C1, read signal RD, and write signal WR
Therefore, the attribute memory is stored in C1 "low",
C1 “High” selects the common memory and C0 “Low”
In the address of attribute memory or common memory
Write / read address register to specify address
Mode, C0 "High" means attribute memory or
In the write / read mode of the common memory, C1 "
RD / WR input together with row ", C0" row "
Specify the address of attribute memory, and
C, RD / WR input with C0 “high”
Writing / reading of tributary memory, C1 "
B) RD / WR input with “0” and C0 “low”
Specify the address of the memory, C1 "high", C0 "
RD / WR input with "high"
A memory card is proposed which is configured to switch between writing and reading .

[0008]

According to the present invention, when the combination of control signals is changed and physical information of the card including the capacity of the common memory is stored in advance in the attribute memory, and the common memory is accessed for reading or writing. Then, the address of the common memory is set in the address register based on the physical information from the attribute memory. Sand
That is, when writing / reading the common memory,
RD / WR as control signals C0 "low" and C1 "high"
According to the physical information of attribute memory,
Register for the new address, and
Specify the service. In this state, C0 “high” and C1 “high”
By setting the common memory to the address register
Is written by RD / WR according to the specification of
Read. The address register is a bit width equal to the bus in accordance with Note <br/> Li capacity. Therefore, even if the common memory has a logically infinite memory capacity, it can be accessed from the outside.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the internal structure of a memory card according to the present invention. FIG. 2 is a diagram showing the correspondence of signals to the pins of the memory card, and basically follows the above guidelines.

The memory card 1 shown in FIG. 1 comprises an attribute memory 2, a common memory 3, a control circuit 4 for controlling these, a power supply control circuit 5, and a backup battery 6. The attribute memory 2 is, for example, an attribute memory.
Memory type (RO)
M, RAM, EEPROM, etc.), a memory for storing card physical information such as a read / write speed, a capacity of the common memory 3, etc., and a control line, an address line, and a data bus line for the control circuit 4. It is connected.

The common memory 3 is a memory mainly for storing data, and has a control line,
They are connected by address lines and data bus lines. The control circuit 4 is an external circuit (for example, a card controller).
In addition, the card enable CE, the control signals C0 and C1, the read signal RD, the write signal WR, and the ready signal RDY /
BSY, a write inhibit signal WP, and data / address buses D0 to D7 are connected so as to be able to input and output. The control circuit 4 has an address register that can set an address according to the capacity of the common memory 3.

As shown in FIG. 2, the memory card 1 has a pin number "1, 20" and a GND number "2".
Data address bus D0 to D7, number "10" at "9"
To power supply Vcc and number “11” to program supply Vp
p, ready signal RDY / BSY at number "12", card enable CE at number "13", numbers "14, 15"
Control signals C0 and C1, and the read signal R
D, a write signal WR is assigned to the number “17”, a write inhibit signal WP is assigned to the number “18”, and a battery check Vbat is assigned to the number “19”. Also, in FIG.
The control signals C0 and C1 of numbers "14 and 15" are control signals used in the embodiment of the present invention, and the details of the control contents will be described in the following description of FIG. The power supply control circuit 5 is connected to an external power supply via a power supply line Vcc and GND.
Also, a signal Vbat indicating the state of the battery is supplied to an external circuit, and further connected internally to a backup battery 6 to supply power to the attribute memory 2, the common memory 3, and the control circuit 4. Supply.

FIG. 3 is an explanatory view schematically showing an embodiment of the present invention. The circuit shown in FIG. 3 is configured inside the control circuit 4, and includes a plurality of address registers 41, 42, 43,... According to the capacity of the common memory 3. The address registers 41, 42, 43,...
Is large enough to specify the address of the capacity of the common memory 3.

FIG. 4 is an explanatory diagram for explaining the function assignment of the control signals C0 and C1 according to the present invention. Control signal C
1 designates attribute memory 2 with "0",
The common memory 3 can be designated by “1”. Then, the control signals C0, C1, and R / W are "0".
The address register of the attribute memory 2 is read by "0""R", and the control signals C0, C1, and R / W are read by the address register of the attribute memory 2 by "0""0""W". Can write. The control signal C
When 0, C1, and R / W are "1", "0", and "R", data is read from the attribute memory 2 and control signals C0,
C1 and R / W are "1""0""W" and attribute
Data is written to the memory 2. Further, the control signal C
If 0, C1, and R / W are "0", "1", and "R", the address register of the common memory 3 is read, and the control signals C0, C1, and R / W are set to "0", "1", and "W". If "", it is possible to write to the address register of the common memory 3.
The control signals C0, C1, R / W are "" 1 "" 1 "" R ""
If so, the data is read from the common memory 3 and if the control signals C0, C1, R / W are "" 1 "" 1 "" W "",
Data can be written to the common memory 3.

The operation of the embodiment will be described. FIG.
FIG. 6 is a time chart for explaining the read timing of the attribute memory 2 of the memory card, and FIG. 6 is a time chart for explaining the write timing of the attribute memory 2 of the memory card. FIG. 7 is a time chart showing the read timing of the common memory 3 of the memory card.
FIG. 8 is a time chart showing the write timing of the common memory 3 of the memory card.

{Read Operation of Attribute Memory 2} First, referring to FIG.
Will be described. A card controller (not shown) is provided for the memory card 1 with respect to the cardine.
The bull CE “1” is input (time t ₀ ).

Subsequently, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R / W are set to "0".
"0""WR (see also FIG. 4, hereinafter the same) by a" (time t ₁ ~t _2), Atoribyu - sets an address in the address register 41 and 42 of Tomemori 2 (time point t ₁ ~ t _2).

[0018] Subsequently, mosquito - Dokontoro - La, the control signal C0, C1, R / W is the "" 0 "" 1 "" R "" ((time t ₃ ~), Atoribyu - the contents of the Tomemori 2 Read sequentially from the set address (time t
₃ ~). Thus, the card controller can know the capacity, type, reading / writing speed, etc. of the attribute memory 2 and the common memory 3.

{Write operation of attribute memory 2} The card controller obtains an attribute from the above information.
When writing is required for the Tomemori 2, as shown in FIG. 6, Memorika - mosquito against de 1 - Doine - entering Bull CE "1" (time t _10).

Subsequently, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R / W are set to "0".
"0""W""(see also FIG. 4, hereinafter the same) by a" (time t ₁₁ ~t _12), Atoribyu - Tomemori 2
Setting an address in the register for the address 41, 42, 43 ... (time t ₁₁ ~t _12).

Subsequently, the card controller sets the control signals C0, C1, and R / W to "1", "0" and "W".
(Time t ₁₃ ~), Atoribyu - sequentially writing control from the set address for Tomemori 2. (Time t ₁₃ ~). Thus, necessary data is written into the attribute memory 2.

<< Read Operation of Common Memory 3 >>
The read operation of the common memory 3 will be described with reference to FIG. Ca - Dokontoro - La (not shown), Memorika - mosquito against de 1 - Doine - entering Bull CE "1" (time t _20).

Subsequently, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R / W are set to "0".
.. (At times t _{21 to} t ₂₂ ), the address is set in the address registers 41, 42, 43,... Of the common memory 3. (time t ₂₁ ~t _22). Thus, one of the address registers 41, 42, 43,... Is designated.

Subsequently, FIG.
As shown in FIG. 3, the control signals C0, C1, and R / W are "1".
"1""it becomes the R""(time t ₂₃ ~), according to the address written in the address register 41, 42, 43 ..., the common memory 3 Karade - data is read out (time t ₂₃ ~). As a result, the address registers 41, 42, 43,... Are obtained based on the data of the capacity of the common memory 3 stored in the attribute memory 2.
Since the required addresses can be set, the capacity can be theoretically expanded indefinitely. At this time, the address register 41,
, 42, 43,... Need to have as many as can specify the address.

<< Writing Operation of Memory Card to Common Memory 3 >> Next, a writing operation of the common memory 3 of the memory card 1 will be described with reference to FIG. Car
Dokontoro - La (not shown), Memorika 8 - force to de 1 - Doine - entering Bull CE "1" (time t _30).

Subsequently, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R / W are set to "0".
"1""W" (FIG. 4 See also, hereinafter the same) by a "(time t ₃₁ ~t _32), the address register 41 and 42
Addresses are written in 2, 43,... (Time t ₃₁
~t _32). This is because the larger the memory capacity, the more the data needs to be written in 8-bit units.

Next, FIG.
As shown in FIG. 3, the control signals C0, C1, and R / W are "1".
"1""W""and then (time t ₃₃ ~), according to the address written in the address register 41, 42, 43 ..., de with respect to the common memory 3 - Write data (time ₃₃ ~).

In setting the address of the common memory 3 in this manner, the capacity of the common memory 3 is known from the information from the attribute memory 2, and the address registers 41, 42, 43,. .. Can be written a plurality of times according to the size of the address, so that the common memory 3 is accessed even if the capacity of the common memory 3 is logically infinite. be able to.

The present embodiment operates in this way, and can theoretically expand the memory capacity to infinity without increasing the number of pins and without any electrical problems.

[0030]

As described above, according to the present invention, the combination of the control signals is replaced with the address for the attribute memory.
Write / read registers and attribute
Based on the information stored in the memory,
Address register that specifies the address
Therefore, without increasing the number of pins of the memory card,
The effect is that the memory capacity can be theoretically increased to an infinite memory capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card according to the present invention.

FIG. 2 is an explanatory diagram for explaining the correspondence of signals to pins of a memory card according to the present invention.

FIG. 3 is a diagram for explaining a main part of an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a configuration example of a control signal used in the embodiment of the present invention.

FIG. 5 is a time chart for explaining a write operation of the attribute memory.

FIG. 6 is a time chart for explaining a read operation of the attribute memory.

FIG. 7 is a time chart for explaining a write operation of the common memory.

FIG. 8 is a time chart for explaining a read operation of the common memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory card 2 Attribute memory 3 Common memory 4 Control circuit 5 Power supply control circuit 6 Backup battery 41, 42, 43 ... Address register

────────────────────────────────────────────────── ─── Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 7/00 315 G06F 3/08 G06K 19/07 WPI (DIALOG)

Claims (1)

(57) [Claims] In de various de - - 1. A Memorika used by being connected to a constant information equipment mosquitoes including a Como <br/> Nmemori which makes storing data, the memory capacity of the common memory -
Attribute memory for storing physical information of the
Addresses of the common memory and attribute memory described above.
Includes an address register for designating the scan, these
A control circuit for controlling writing / reading of the two memories , further comprising a control signal to be inputted
C0, C1, read signal RD, write signal WR
In C1 "low", the attribute memory is
1 "High" selects common memory, C0 "Low"
Is the address of attribute memory or common memory
Write / read mode of the address register that specifies
-Mode, C0 "High" means attribute memory or
In the write / read mode of the flash memory,
C, RD / WR input together with C0 "low"
Specify the address of tributary memory, and
C, RD / WR input with C0 “high”
Writing / reading of tributary memory, C1 "
B) RD / WR input with “0” and C0 “low”
Specify the address of the memory, C1 "high", C0 "
RD / WR input with "high"
A memory card characterized by being configured to switch between writing and reading .