JP3131849B2 - Digital recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recorder capable of digitally recording and reproducing an audio signal and the like, and further, capable of editing.

[0002]

2. Description of the Related Art It has been proposed to use an external recording device such as a large-capacity hard disk or a magneto-optical disk for recording an audio signal or the like (for example, Japanese Patent Application No. 2-123788 by the present applicant). . In this case, the audio signal is A
The signal is converted from an analog signal to a digital signal by the / D converter, and is temporarily stored in the buffer memory. The digital data stored in the buffer memory is transferred and recorded on a hard disk at a predetermined timing. On the other hand, even at the time of reading, digital data read from the hard disk is temporarily stored in the buffer memory, read from the buffer memory at a predetermined timing, and input to the D / A converter. The audio signal converted from a digital signal to an analog signal by the D / A converter is supplied to a speaker or the like. By controlling the access address of the hard disk, an apparatus having an advanced and flexible editing function can be realized.

[0003]

In order to realize such an apparatus at low cost, it is necessary to make the RAM as a buffer memory for absorbing the overhead of disk access at least a small capacity. On the other hand, during editing, for example, if a large number of looping playbacks are specified at extremely short time intervals, disk access is frequently performed, so a buffer memory with a very small capacity cannot absorb the disk access overhead. However, there has been a problem that data transfer cannot be made in time, causing inconveniences such as skipping of sound during reproduction.

[0004] In particular, when different media such as a hard disk and a magneto-optical disk are used as the external storage device (the hard disk is faster and the magneto-optical disk is slower), transfer to each disk is performed. Because of the difference in rates, it is difficult to standardize the capacity of the buffer memory. In particular, in the case of a multi-track configuration, if each track is fixed to a hard disk or a magneto-optical disk, respectively, it is only necessary to use a buffer memory of an optimum length, but each track is fixedly associated with a medium. When a different medium is randomly accessed even when one track is reproduced, a buffer memory having an optimal length must be used in real time.

Also, at the time of editing, it is not possible to determine whether the editing is capable of absorbing the overhead, and as a result of actually listening to the sound, it is determined that the overhead is not absorbed. In such a case, there was a problem that the editing operation had to be performed again.

The present invention has been made in view of such circumstances, and uses a plurality of external storage devices having different transfer rates.
When performing editing work where recording and playback operations are repeated
Ensure adequate buffer capacity to absorb overhead
To provide a digital recorder that can
And

[0007]

According to the present invention , input data is
While storing in the temporary storage means,
Transfer the input data to external recording means for recording
On the other hand, the recording data read from the external recording
While storing in the time storage means, the recording data is stored from the temporary storage means.
In a digital recorder that reads and plays back data,
At the time of reproduction, the reading of the total storage capacity of the temporary storage
The effective capacity of the temporary storage means is
The amount is determined, and at the time of recording, the total storage capacity of the temporary storage means
From the amount of input data to the effective capacity of the temporary storage means
Determining means for determining
A new storage area in the temporary storage means according to the effective capacity.
Allocating means for addressing

[0008]

[0009]

[0010]

According to the present invention, a record waiting to be read during reproduction is stored.
From the amount of recorded data, the effective capacity of the temporary storage means
Determine the effective capacity of the temporary storage means from the input data amount,
New storage area in temporary storage means according to the specified effective capacity
Addressing the storage area of the temporary storage means
Is effectively changed by dynamically changing
Recording operation using multiple external storage devices with different rates
Overhead when performing editing work that repeats the playback operation
It is possible to secure the appropriate buffer capacity to absorb the buffer
become.

[0011]

[0012]

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the digital recorder according to the present invention will be described below with reference to the drawings.

<Overall Configuration> FIG. 1 shows the overall configuration of an embodiment of a digital recorder according to the present invention. In this embodiment, recording and playback operations for up to three tracks can be performed simultaneously. . The whole is CP as shown
It is divided into a U part (left part in the figure) and a DMA unit (audio recording / reproducing processing device) (right part in the figure).

The CPU section includes a CPU 1, a program ROM 2 storing a program (to be described in detail later) for defining the operation of the CPU 1, an area storing various data,
A RAM 3 including an area for storing a current pointer of a track, a work area, and the like;
It has a keyboard 4 including various function keys and data input keys as peripheral devices connected to the port, a display device 5 including a CRT or LCD and its driver and performing various displays.

As will be described later, during real-time operation (recording / reproducing, etc.), the CPU 1 sets the address bus and the data bus of the DMA unit to idle time when necessary.
The components of the MA unit are controlled, and during editing, rearrangement of data blocks, manipulation of a disk access pointer, and the like are performed. Recording / recording of each track (hereinafter referred to as Tr) is performed from the keyboard 4 as described later.
You can set playback mode, start, stop, locate, and specify edit points. Program ROM2, RAM
3 is connected to an address terminal of the CPU 1 via an address bus.
And an output terminal thereof is connected to the CPU 1 or the transceiver 7 via the data bus.

That is, in order to connect the CPU unit and the DMA unit, the buffer 6 and the transceiver 7
It is provided in the unit. The buffer 6 is connected to the CPU 1 via an address bus, and further connected to an address bus in the DMA unit. The transceiver 7 is a CPU
1 and a data bus, and further connected to a data bus in the DMA unit. In the DMA unit,
Audio input / output device 8-1 for Tr1, audio input / output device 8-2 for Tr2, audio input / output device 8-3 for Tr3
Are provided, and analog audio signals can be input and output independently of each other.

Inside each of the audio input / output devices 8-1 to 8-3, there are provided a converter for selectively executing A / D conversion and D / A conversion, a low-pass filter for removing sampling noise, and a sampling device. A clock circuit that generates a clock with a period is included. These audio input / output devices 8
In -1 to 8-3, if the track is set to the record state, an external analog audio signal is appropriately filtered for each sampling period, and
/ D conversion to obtain digital audio data. Conversely, if the track is set to the play (playback) state, the digital audio data read in advance is
After being subjected to / A conversion and appropriately filtered, it is output as an analog audio signal.

Each audio input / output device 8-1 of Tr1 to Tr3
8-3 correspond to the corresponding buffers 9- via the data bus.
1 (BUF1), a buffer 9-2 (BUF2), and a buffer 9-3 (BUF3), respectively, for exchanging digital audio data. The buffers 9-1 to 9-3 correspond to Tr1 to Tr3, respectively.
Data transfer between -1 to 8-3 is performed by direct memory access (DM
A) The method is performed.

Each of the audio input / output devices 8-1 to 8-3 includes:
At the time of recording, the audio input / output devices 8-1 to 8-3 are transmitted to the DMA controller 10 at a sampling period.
Transfer (single transfer) of digital data related to one sampling in the direction from the buffer to the buffers 9-1 to 9-3
Request (request) and send a DRQ signal (Tr1
DRQ1, DRQ2 for Tr2, DRQ for Tr3
3) to the DMA controller 10)), D
Answer from MA controller 10 (Acknowledge is
Tr1 receives DAK1, Tr2 receives DAK2, and Tr3 receives DAK3 as DAK3), and the actual data transfer is executed. At the time of play, a request for DMA transfer (single transfer) of digital data relating to one sampling from the buffers 9-1 to 9-3 in the direction of the audio input / output devices 8-1 to 8-3 in the sampling cycle is received by the audio input. Data is transferred from the output devices 8-1 to 8-3 by the DMA controller 10 in the same manner as described above.

Each of the buffers 9-1 to 9-3 has a capacity capable of storing digital audio data once or a plurality of times. For example, the RAM is divided into three parts Tr1 to Tr3, and each of the buffers is divided into a ring buffer (last address and first address). Is used as a buffer that is virtually connected to the
It is configured to function as an O buffer. The addresses for the buffers 9-1 to 9-3 are specified by the DMA controller 10 or the like via an address bus. That is, when the DMA transfer is performed, the DMA controller 10 occupies the address bus, the data bus, and the control signal line in the DMA unit.

The buffers 9-1 to 9-3 exchange data with disks such as the hard disk 120 and the magneto-optical disk 121 (hereinafter simply referred to as the disk 12) under the control of the device controller 11 via the data bus. . The disk 12 and the device controller 11 are connected via a data bus and a control signal line, and all read / write accesses to the disk 12 are performed by the device controller 11. Each disk has a storage area divided into three tracks of Tr1 to Tr3, and data transfer with the buffers 9-1 to 9-3 is performed by the DMA controller 10. This is done by the device controller 11 issuing an interrupt (INT) to the CPU 1 when the transfer of one data block is completed, and instructing the CPU 1 to transfer the next data block. CPU 1 is a device controller 1
When the interrupt signal INT is received from the CPU 1, the DMA controller 10 and the device controller 11 are set to desired states or programmed, and
Make the transfer. Details of this operation will be described later.

When playing, the DMA controller 10 reads out a predetermined amount (for a plurality of sampling periods) of digital audio data from the disk 12 and then
It operates to perform DMA transfer (block transfer) to a designated buffer among the buffers 9-1 to 9-3, and at the time of recording, a predetermined amount (for a plurality of sampling periods) from the designated buffer. It operates to read digital audio data and perform DMA transfer (block transfer) to a designated position on the disk 12.

This disk 12 and buffers 9-1 to 9-
When transferring data to / from the device controller 1,
1 to the DMA controller 10 by request signal DREQ
Is output (received as DRQ4 on the DMA controller 10 side), and when the transfer becomes possible, the answer signal DACK is received (outputted as DAK4 on the DMA controller 10 side), whereby the actual transfer state is set.

As described above, the DMA controller 10
3 channels between audio input / output devices 8-1 to 8-3 of Tr1 to Tr3 and buffers 9-1 to 9-3 (C to be described later)
H1 to CH3) data transfer and one-channel (CH4) data transfer between one of the buffers 9-1 to 9-3 selected in order and the disk, for a total of four channels in time division. Perform data transfer operation.

The CPU 1 supplies an address signal to the buffer 6 via an address bus and manages a designation signal of each component to the decoder 13 via the buffer 6 in order to manage the function and operation of each component in the DMA unit. Supply,
Each of the designation signals CS is transmitted to each of the audio input / output devices 8-1 to 8-
3, buffers 9-1 to 9-3, DMA controller 1
0, given to the device controller 11. At the same time, various data are exchanged with the CPU 1 via the transceiver 7 and the data bus.

Further, each of the voice input / output devices 8-
A designation signal WR for designating a record state (write state) or a play state (read state) is supplied to the IOWR terminals 1 to 8-3 via the buffer 6.

Each of the buffers 9-1 to 9-3, DMA
The designation signal (write signal) WR and another designation signal (read signal) RD are also supplied from the CPU 1 to the controller 10 and the device controller 11 via the buffer 6 to read data from the respective constituent elements. Conversely, data is written. Also, DMA
The controller 10 outputs these designation signals RD and WR in the DMA transfer state. The relationship between these signals and the function and operation of each component will be described later.

The DMA controller 10 sets the DMA enable signal DMAENB to "1" and outputs it when the DMA transfer is being performed between the constituent elements. As a result, the output of the AND gate 14 to which the signal DMAENB is applied via the inverter 16 becomes “0”,
The enabling signal E is supplied to the buffer 6 and the transceiver 7.
Is given as "0", so that data and addresses cannot be transferred between the CPU unit and the DMA unit. At this time, if a "1" signal is given to the AND gate 15 from the decoder 13, the output of the AND gate 15 becomes "1" and the wait signal WAIT is supplied to the CPU 1.

That is, when the CPU 1 supplies a predetermined signal to the decoder 13 in order to open the buffer 6 and the transceiver 7 in order to manage the DMA unit, that is, the decoder 13 outputs "1" to one input terminal of the AND gate 14. 1 ”signal is supplied (the CPU 1
-1 to 9-3, the DMA controller 10, the device controller 11, and the address signal for accessing any of the audio input / output devices 8-1 to 8-3, the output of the decoder 13 becomes active and the AND gate 1
The output to one input terminal of each of 4 and 15 is "1"),
When the DMA transfer starts, the CPU 1 waits (WAI
T), and after the DMA transfer is executed with priority, the operation of the CPU 1 is restarted with the release of the wait.

Conversely, the DMA controller 10
When executing the A transfer, the CPU 1
Even if an attempt is made to access controller 10, wait signal WAIT is supplied from AND gate 15 and CPU 1
Execution cycle is extended halfway, buffer 6,
Transceiver 7 will be closed during that time.

After all, the reason why the CPU 1 can access each component of the DMA unit is that the CPU 1 has issued an address for accessing each component of the DMA unit. The signal DMAENB is inactive ("0"), that is, the data bus of the DMA unit is free. Is satisfied when the two conditions are satisfied, but as described above, the CPU 1
Processing can be advanced without considering whether to access the A unit.

When the CPU 1 wants to immediately change the operation state of the DMA unit in response to a key input or a trigger of control data, the CPU 1 is not limited to the DMA controller 10 regardless of the state of the DMA controller 10. A command DMAEND for interrupting the DMA transfer can be output (this is given to the DMA controller 10 as an END signal).

<Main Configuration of DMA Controller 10> Next, an example of the configuration of the DMA controller 10 will be described. D
The MA controller 10 has a transfer capability in which one bus cycle is several hundred nanoseconds. Therefore, the time for transferring the sampling data for three tracks is 1 to 2 microseconds.

When the sampling frequency fs is 48 KHz, one sampling time interval is about 21 microseconds, and most of the sampling time interval is between the buffers 9-1 to 9-3, the device controller 11, and the disk 12. The time for data transfer and the programming time of each component from the CPU 1 can be allocated.

FIG. 2 shows the main configuration of the specific example. The DMA controller 10 has an input (IN) address buffer 1 connected to an address bus.
01 and an output side (OUT) address buffer 102. The contents specified by the register selector 103 change according to the address signal applied to the input side address buffer 101, and the desired registers existing in the address register 104 and the control register 105 are specified.

The address register 104 and the control register 105 have areas of four channels CH1 to CH4.
This is a register for performing DMA transfer between -1 to 9-3, and the channel CH4 has buffers 9-1 to 9-3.
Between the specified buffer and the disk 12
This is a register for performing A transfer. The registers of the channels CH1 to CH4 in the address register 104 are as follows.
The control register 105 has an area for storing at least the current addresses and start addresses of the corresponding buffers 9-1 to 9-3 and the designated buffer.
In the area of each of the channels CH1 to CH4, for example,
Control data for designating the direction of the DMA transfer is stored.

The contents of the address register 104 and the control register 105 can be input / output to / from a data bus via a data buffer 106. These components are controlled by the timing control logic 107, the service controller 108, and the channel selector 109.

The service controller 108 has a hardware logic or microprogram control structure, and receives signals from the timing control logic 107, audio input devices 8-1 to 8-3, and DMA request signals DRQ1 to DRQ4 from the device controller 11. And C
Upon receiving a DMA suspend command END (DMAEND) from PU1, answer (acknowledge) signals DAK1 to DAK4 for the above-described components, and a DM indicating that DMA transfer is in progress
In addition to outputting the A enable (enabling) signal DMAENB, it also issues various commands to the timing controller 107 and outputs a channel select signal to the channel selector 109. The channel selector 109 selectively designates a register corresponding to each of the channels CH1 to CH4 in the address register 104 and the control register 105.

Timing control logic 107
Receives the designation signal CS from the decoder 13, the control signal from the control register 105, and the control signal from the service controller 108, controls the input / output of the address buffer 102 and the data buffer 106, and operates the address incrementer 110. Then, the current address register of the designated channel in the address register 104 is incremented. When the current address register reaches the final address of the buffer assigned to the channel, the current address register is reset to the start address of the buffer assigned to the channel.

An area data register 111 as monitoring means for managing and controlling buffer area information.
And the area data buffer 112 are used.

In the area data register 111 and the area data buffer 112, the top (head) and tail (end) addresses of the buffer area allocated to the channel are stored. Each time the address incrementer 110 increments the current address, the address incrementer 110 refers to the area data register 111 of the channel currently being serviced, and if the increment result of the address reaches the tail address, the address is incremented to the top address to circulate the buffer. Reset. Alternatively, the change from the tail address to the top address may be performed by a program control process of the DMA controller 10 as described later (FIGS. 6, 6-16, 6-1).
7).

<Overall Operation of CPU 1> The operation of this embodiment will be described below. 3 and 4 are flowcharts showing the operation of the CPU 1. This is the program (software) stored in the program ROM 2
FIG. 3 shows a main routine, and FIG.
Interrupt signal IN from device controller 11
7 shows an interrupt routine executed in response to the arrival of T.

First, in FIG. 3, it is judged whether the mode set by the keyboard 4 is the play / record mode or the edit (edit) mode (step 3-1). If it is in the edit mode, the process proceeds to 3-2, and the track or the point to be edited,
The CPU 1 determines what kind of editing is to be performed (for example, shifting, correcting, or deleting the timing of a sound recorded at a designated point for a certain time),
Control data for this is generated and stored in the RAM 3 (3-3), and after performing various editing operations, the process returns to 3-1 again.

Although this editing operation is not described in detail, a program of an access point for reading from the disk 12 to the device controller 11 and the DMA controller 10, transfer to the RAM 3, various editing using the RAM 3, and post-editing The operation of restoring the digital audio data to the disk 12 and the designation of the access point
It is executed under the control of PU1.

When the CPU 1 judges that the current mode is the play / record mode, the process proceeds from 3-1 to 3-4, and the operation mode of each of the three tracks is set according to the input instruction of the keyboard 4, and In 5, the A / D
Conversion or D / A conversion is performed by each audio input / output device 8.
-1 to 8-3 execute, buffer 6, decoder 1
The IOWR is given and set while sequentially transmitting the designation signal CS via 3. Now, for example, for Tr1, the play state (therefore, the D / A conversion operation state), Tr1
2 and Tr3 are each in the record state (therefore, the A / D conversion operation state). FIG. 10 is a conceptual diagram of a schematic operation when such a mode is set.

In 3-5, the DMA controller 10 sends a buffer 9-
The addresses 1 to 9-3 are initialized. That is, the channels CH1 to CH1 are controlled by the address buffer 101, the register selector 103, and the channel selector 109 in FIG.
The initial setting data is input and set via the data buffer 106 while specifying each register of the H3 (the address register 104 and the control register 105).

Here, the buffers 9-1 to 9-3 are cyclically used as ring buffers. Initially, the buffers 9-1 to 9-3 correspond to the start addresses of the buffers 9-1 to 9-3. Set to match the address.

Subsequently, the CPU 1 executes the processing of 3-6,
A disk access pointer corresponding to each of the tracks Tr1 to Tr3 of the disk 12 located in the work (work) memory area in the RAM 3 is initialized.

Next, the CPU 1 controls each audio input / output device 8-1.
To start the A / D conversion operation or D / A conversion operation of 8-3 (3-7). Subsequently, in 3-8, a software interrupt is issued, and the device controller 11 issues a program request for data transfer between the disk 12 and any of the buffers 9-1 to 9-3 (the device controller 11 issues a request to the CPU 1). The same processing as that performed when interrupt INT is performed (described later) is performed.

Specifically, the operation according to the flowchart shown in FIG. 4 is executed in 3-8. For example,
In this case, Tr1 is used as a channel of the DMA controller 10 in order to DMA-transfer digital audio data from the disk 12 to the buffer 9-1.
Is determined (4-1). Subsequently, the start address of this CH1 (3 as described above)
(Initial setting at -5) is copied as the start address of CH4 (4-2). The operation of the DMA controller 10 at this time will be described later. Then, in this case, the number of data transfers is calculated from the start address of CH1 and the current address (4-3).

Since this is the initial state, no data has been transferred to the buffer 9-1 for Tr1 so far, so that data transfer from the disk 12 to the entire memory area of the buffer 9-1 is not possible. it can.
Of course, if there are multiple tracks when playing,
Since the digital audio data previously stored in the plurality of buffers must be transferred from the disk 12 at an early stage,
Without transferring data to one buffer in full, D
MA transfer may be performed for each track. Alternatively, after the data is completely transferred from the disk 12 to the necessary buffers 9-1 to 9-3 in advance,
The play / record operation may be started synchronously.

Next, in 4-4, in this case CH1
Is copied to the start address of CH4. In this case, the initial address is eventually the start address. As described above, the CPU 1 sets 4-1
After performing each setting / control on the DMA controller 10 in 4 to 4-4, the process proceeds to 4-5.
The H1 area data is stored in the CH4 area data register 1.
11 and proceed to 4-6. RA in 4-6
The disk access pointer of Tr1 is now taken out from the working memory of M3. Further, at 4-7, the operation mode of Tr1 (now play mode) obtained according to the contents of the area of CH1 of the control register 105 of the DMA controller 10, and the Tr1 The device controller 11 is programmed based on the disk access pointer and the number of data transfers from the disk 12 to the buffer 9-1 determined in 4-3. The operation of the device controller 11 at this time will be described later in detail.

As a result, the device controller 11
In this case, a DMA transfer from the disk 12 to the buffer 9-1 is requested to the DMA controller 10 (DRE).
Q), and the DMA controller 10
A transfer will be performed. This operation will be described later in detail.

Subsequently, in 4-8, the CPU 1 sets the RA
The disk access pointer of Tr1 in the working memory of M3 is updated to a value that the disk access pointer will take as a result of executing the above-described transfer processing. That is, as can be seen from the above description, the disk 12 and the buffer 9
-1 after this, the DMA controller 1
0 is executed, and the CPU 1 sets the value taken by the access pointer of the disk 12 at 4-8 when the DMA transfer is completed. Then, the process returns to the main routine (FIG. 3).

As will be apparent from the following description, once the first interrupt routine (FIG. 4) is activated and the device controller 11 is operated once, thereafter, every time the transfer of the data block designated by the CPU 1 is completed, Since the interrupt is issued from the device controller 11 (the INT signal is given to the CPU 1), the CPU 1 executes the trigger which has ended the recording / playback operation, has received a key input, or has instructed the control data. It only determines whether or not it has occurred.

That is, the CPU 1 refers to the disk access pointer (RAM3) in 3-9 to judge whether or not the memory area is over, that is, whether or not to end (3-10). Output device 8-
The A / D conversion and D / A conversion operations of 1 to 8-3 are stopped (3-11), and if NO, the control data and key input state are referred to (3-12). 3-9 to check disk access pointer
And the following 3-9 to 3-13 are repeated.

If there is any change in 3-13, the process proceeds from 3-13 to 3-14, and the CPU 1
To temporarily suspend MA transfer and make new settings, DMA
DMA stop command (DMAEN) to the controller 10
D) is output. Then, according to new input instructions, etc.,
DMA controller 10, audio input / output devices 8-1 to 8-
3 (3-15), proceed to 3-16 to restart the DMA operation again, execute the routine of FIG. 4 similarly to 3-8 described above, and then return to 3-9.

As described above, at the time of play / recording, the CPU 1 performs the initial setting of 3-4 to 3-8, and then performs 3-9, 3-10, 3-12, and 3-13. 3-
14 to 3-16 are repeatedly executed, and a change instruction on the keyboard 4 (for example, pause (A / D,
D / A interruption) or punch-in / out (A / D,
In response to a change in the control data obtained at the time of editing, the DMA transfer control is immediately interrupted, the program is changed, and the same processing is executed again. I do.

<Operation of Audio Input / Output Devices 8-1 to 8-3>
Next, an operation state of the audio input / output devices 8-1 to 8-3 will be described with reference to FIG. This flowchart may be based on microprogram control or hard logic control, and various means for implementing functions can be selected.

At 5-1 it is judged whether or not the designation signal CS of the voice input / output device has arrived from the CPU 1 (active).
In 2, the CPU 1 sets an operation state (record, play, stop, etc.). This is the CPU 1 in FIG.
In response to 3-5 and 3-15 in the main routine. Then, if a determination of NO is made in 5-1, in 5-3, the voice input / output devices 8-1 to 8-3 are used.
Is in a record state or a play state.
Proceeds to the processing of 5-9, and if it is determined that the playing state is reached, 5-1
It proceeds to the processing of 0-5-15.

First, the operation of the audio input / output devices set in the record state (the audio input / output devices 8-2 and 8-3 in this case) will be described. At 5-4, it is determined whether or not the sampling time has come, and this 5-4 is repeated until the sampling time comes. The determination of the sampling time may be performed by the output of a hard timer in each of the audio input / output devices 8-1 to 8-3, or a common hard timer may be provided and each audio input / output device may be provided in accordance with the output. May operate. As will be understood from the following description, each of the audio input / output devices 8-1 to 8-3.
It is also possible to use different sampling frequencies.

When the determination of YES is made in 5-4, the applied analog audio signal is sampled and held (S / H) in 5-5 and A / D converted. Subsequently, in 5-6, the DMA controller 10 activates and outputs the DMA transfer request DRQ to the DMA controller 10.

The DMA controller 10 receives the request signal DRQ and outputs an answer signal DAK for performing DMA transfer (the detailed operation in this case will be described later). Therefore, the audio input / output devices 8-1 to 8-3 (the audio input / output devices 8-2 or 8-
3) If the determination at 5-7 is YES, the process proceeds to 5-8, where the digital audio data obtained by A / D conversion is output to the data bus, and the corresponding buffers 9-1 to 9-3 (now Is sent to the buffer 9-2 or 9-3). And 5-
At 9, the DMA transfer request DRQ is made inactive. Therefore, in this case, the audio input / output devices 8-2, 8-
3, the analog audio signal supplied from the outside is converted into a digital audio signal for each sampling period, and the current addresses of the buffers 9-2 and 9-3 specified by the DMA controller 10 are described later. Transfer to

If it is determined in step 5-3 that the player is in the play state, the process proceeds to step 5-10 to activate the DMA transfer request DRQ to the DMA controller 10 and wait for an answer signal DAK from the DMA controller 10 (step 5-5). 1
1) fetch digital audio data on the data bus (5
-12), the request DRQ is made inactive (5)
-13). The operation of the DMA controller 10 at this time will be described later, but in this case, the buffer 9 corresponding to Tr1
-1 current address content (this is the content of the Tr1 area of the disk 12 already transferred and recorded)
Are input and set to the voice input / output device 8-1 by the above operation. Then, it is determined whether or not the sampling time has come (5-14). The detection of the arrival of the sampling time is performed in the same manner as in the case described in 5-4.

If the answer is YES in 5-14, 5-1
Proceed to 5 to execute D / A conversion and low-pass filtering, and then output an analog audio signal to the outside.

The operation at one sampling time in the case of the record state and the case of the play state has been described above. However, the processing returns to 5-1 after the completion of each processing of 5-9 and 5-15, and so on. The processing for the sampling time is executed one after another.

<Operation of DMA Controller 10>
The operation of the DMA controller 10 will be described with reference to FIG. The flowchart of FIG. 6 may represent that the service controller 108 of FIG. 2 operates under microprogram control, or the function of the DMA controller 10 may be realized by hard logic.

First, in 6-1, the designation signal CS from the CPU 1 has arrived (it is active).
It is determined whether the read signal RD or the write signal WR is given from the CPU 1 in 6-2 if YES, and if the read signal RD, 6-3
To output via the data bus the contents of the registers 104 and 105 designated by the address signal given via the address bus so that the CPU 1 can read the contents.
Conversely, if it is a write signal WR, the process proceeds to 6-4, and desired data is input and set to the designated register via the data bus. The processes of 6-3 and 6-4 correspond to processes of 3-5 and 3-15 of the main routine of the CPU 1. Accordingly, each register 1 in FIG.
Desired data is set in 04 and 105.

The DMA from the CPU 1
When the access to the controller 10 or the program is completed, the designation signal CS is made inactive, and 6-1 to 6
The process proceeds to -5.

In 6-5, each of the audio input / output devices 8-1 to 8-8
-3, the DMA transfer requests DRQ1 to DRQ3 have been received, or the device controller 11
It is determined whether or not the EQ (DRQ4) has arrived. If there is a request from any of them, the process proceeds to 6-6, the DMA enable signal DMAENB is set to "1" (active), and the address bus and the data bus in the DMA unit are set. Is made exclusive to the DMA controller 10 and access from the CPU 1 is not accepted. Subsequently, for a plurality of requests, a channel is selected according to the priority order of the channels CH1 to CH4 (6-7).

Subsequently, the current address (address register 10) of the selected channel (now, for example, CH2) is set.
4 (the content of the current address register of CH2) is output to the address bus (6-8). Then, the control register 1 of the selected channel (now, for example, CH2)
05, it is determined in which direction the DMA transfer is to be performed (6-9). If the data is to be transferred from the buffers 9-1 to 9-3 to another element (I / O), the processing is to be performed from 6-10. 6-11
Then, the read signal RD is given to the buffer selected from among the buffers 9-1 to 9-3, and conversely, the transfer is performed from another element (I / O) to the buffers 9-1 to 9-3. If so, the process proceeds to 6-12, and the write signal WR is sent to the buffer.
give.

After that, the answer signal DAK is activated (6-13). As a result, in this case, the audio input / output device 8-2 of the Tr2 sends out the sampled audio data to the data bus by the processing of 5-7 and 5-8 (FIG. 5), and outputs the data to the buffer 9-2. The DMA controller 10 writes data in the area of the current address. 6-
In 14, since the data transfer is completed, the read signal RD or the write signal WR and the answer signal DAK are made inactive, and in 6-15, the corresponding channel (now CH 2)
Current address (address register 104 in FIG. 2)
(1) or reset to the buffer start address. By the operation of 6-15, the count is incremented each time new sampled audio data is written into the buffers 9-1 to 9-3 or each time new audio data is read.

After performing the processing of 6-15, the DMA controller 10 judges whether the tail address of the corresponding channel is lower than the current address or not, and if not, the processing proceeds to 6-1. Returning, if YES, proceed to 6-17, replace the current address with the top address of the channel, and return to 6-1. That is, thereby, the buffers 9-1 to 9-3 are used in a ring shape.

For example, audio input / output device 8 for Tr2 and Tr3
Assuming that a data transfer request has been made to the DMA controller 10 from -2 and 8-3, and data transfer has been executed only for Tr2, the following 6-5
Is determined to be YES. Hereinafter, regarding Tr3, data transfer from the audio input / output device 8-3 to the buffer 9-3 is performed in the following manner: 6-7 to 6-10, 6-12 to 6-1.
7 is performed in the same manner as described above.

When such data transfer is completed, 6-5
From 6 to 18, the DMA enable signal is set to "0" (inactive), the DMA controller 10 stops occupying the data bus and address bus in the DMA unit, and the access from the CPU 1 can be accepted. To

With respect to Tr2 and Tr3, the audio input / output devices 8-2 and 8-3 transmit the corresponding buffers 9-2 and 9-3, respectively.
The data transfer to the audio input / output device 8-1 has been described above.
Is transferred by the DMA controller 10. In response, the DMA controller 10 executes 6-5 to 6-7 in the same manner as described above, and in 6-8, sends the address data indicating the address to be read from the buffer 9-1 via the address bus. give. 6-9,
By executing 6-10, the process proceeds to 6-11, in which the read signal RD is supplied to the buffer 9-1, and the answer signal DAK is set to "1" at 6-13.

As a result, the digital audio data at the designated address of the buffer 9-1 is transferred to the Tr1 via the data bus.
To the voice input / output device 8-1. Thereafter, through the processes of 6-14 to 6-17, 6-
Return to 1.

The DMA controller 10 also performs data transfer between the disk 12 and the buffers 9-1 to 9-3. In this case, the address register 104 and the control register 105 of the channel CH4 are used.
This operation is performed by the interrupt routine of the CPU 1 (FIG. 4).
, The setting / control operations 4-1 to 4-4 for the DMA controller 10 and the device controller 11
Are executed after programming operations 4-5 and 4-6 for.

The CP for the DMA controller 10
According to the setting / control operations 4-1 to 4-4 of U1, the DM
The A controller 10 performs the processing of 6-3 and 6-4. That is, the CPU 1 determines the track to which the data is to be transferred by the current channel CH4, and sets the start address of the buffer corresponding to the track (that is, the address next to the block data for which the data was previously transferred between the buffer and the disk 12) to CH4. The start address register (in the address register 104 in FIG. 2) is set in the start address register, and the current data transfer number for this track is set to the start address and the current address (the address that has been incremented after the previous data transfer with the disk 12). The CPU 1 obtains the current address of the track from the difference from the start address and copies the current address to the start address.

The CPU 1 performs data transfer between the buffers 9-1 to 9-3 corresponding to the operating track and the disk 12 sequentially for each track, and for each track, the previous data is transferred. Data transfer following transfer (block transfer) is performed. Then, the CPU 1
After the device controller 11 is programmed according to steps 5 and 4-6, an actual transfer request is generated from the device controller 11, and the DMA transfer is started.

When the DMA controller 10 detects that there is a transfer request from the device controller 11 in 6-5, the DMA controller 10 executes 6-6 to 6-9 in the same manner as described above, and then executes the buffers 9-1 to 9-. 6-10, a request for data transfer from the disk 3 to the disk 12 or a request for data transfer from the disk 12 to the buffers 9-1 to 9-3. 6-
After proceeding to 12, each processing of 6-13 to 6-17 is executed.

This disk 12 and buffers 9-1 to 9-
3 is transferred to the device controller 1
The operation 1 is also closely related, and will be further described later. When the DMA transfer is completed, the request signals DRQ1 to DRQ4
No longer arrives, proceed from 6-5 to 6-18, DMA
The enable signal DMAENB is set to “0” (inactive).

<Operation of Device Controller 11> Next, the operation of the device controller 11 will be described with reference to FIG. This device controller 11 may be realized by hardware logic or microprogram control, and in any case, implements the operation flow of FIG.

First, it is determined whether the designation signal CS is given from the CPU 1 (7-1). This is given by the interrupt routine of the CPU 1 (4-5, 4-6 in FIG. 4). In the case of NO, it returns to the original, but in the case of YES, 7-
Then, it is determined whether the read signal RD or the write signal WR is supplied from the CPU 1 at the time of reading, and at the time of reading, the designated data (contents of the address register, etc.) inside the device controller 11 is transferred to the data bus at 7-3. Output to CPU1 via

When the write signal WR is given, the process proceeds from 7-2 to 7-4, and the data transfer direction between the buffer and the disk 12 for DMA transfer on the channel CH4 of the DMA controller 10 this time is set. At 7-5, an access point of the disk 12 to be accessed is set. This is based on the access pointer of the track obtained by the CPU 1 from the RAM 3 (4-5 in FIG. 4).

Subsequently, in step 7-6, the number of transfer data (the number of digital audio data) is set in the internal counter of the device controller 11. This transfer data number is determined by the CPU 1
In the interrupt routine 4-6.

As described above, by executing 7-4 to 7-6, the device controller 11 is programmed under the control of the CPU 1, and thereafter, the device controller 11 requests the DMA controller 10 for data transfer ( 7-7). As you can see from this,
Upon receiving the interrupt signal INT from the device controller 11, the CPU 1 corresponds to the next track (that is, if all of Tr1 to Tr3 are operating now,
1, in the order of Tr2, Tr3, Tr1,...
Program the device controller 11. afterwards,
The CPU 1 is separated from the device controller 11 and the DMA controller 10 to execute an actual DMA transfer by mutual interaction.

The device controller 11 proceeds to 7-8 after 7-7, and repeats 7-8 until receiving the answer signal DACK (DAK4) from the DMA controller 10 (see 6-13 in FIG. 6). If the determination at 7-8 is YES, the process proceeds to 7-9, where the operation of CH4 of the DMA controller 10 transfers one sample of digital audio data, and the transfer counter set at 7-6 is down-counted by one. (7-10). In the following 7-11, judgment is made according to the contents of the transfer counter as to whether the data transfer for the number of transfer data set in advance is completed,
If NO, return to 7-8 again. Therefore, the DMA controller 10 continuously receives the transfer request DRQ4 until the transfer (block transfer) of the number of data set from the device controller 11 is completed, and according to this transfer request, 6-5 to 6-15 The device controller 11 executes the processing (FIG. 6) and responds thereto.
The side executes the processes of 7-8 to 7-11.

When the end of the transfer is determined in step 7-11, the process proceeds to step 7-12, in which a request D for data transfer from the device controller 11 to the DMA controller 10 is issued.
REQ (DRQ4) is set to “0” (inactive). Then, the device controller 11 sends an interrupt signal INT to the CPU 1 to cause the data transfer between the disk 12 and any of the buffers 9-1 to 9-3 for the next track (7-13). In response to this, the CPU 1 executes the interrupt routine (FIG. 4) as described above.

<Rewriting of Area Data> Next, the operation of transferring the contents of the area data buffer 112 of the DMA controller 10 to the area data register 111 will be described with reference to the flowchart of FIG. This may be based on hardware logic or microprogram control inside the DMA controller 10, and various means for realizing functions can be selected.

Of course, this processing is executed by the CPU 1
Software processing. First, it is assumed that each track is allocated to the buffers 9-1 to 9-3 as shown in FIG. In step 8-0 in FIG. 8, one of the areas (addresses) of the buffers 9-1 to 9-3
When it is determined that a rewrite request has occurred, the number of the smallest track (9-1, 9-
(In the order of 2, 9-3). This means that processing is performed sequentially from the track buffer assigned to the upper address.

Next, the rewrite request is further divided into a tail address and a top address rewrite request. When it is determined that there is a tail rewrite request, it is next determined in step 8-3 and thereafter whether the data storage state in the buffer is a state in which the tail or top address can be rewritten. That is, if the start address of the channel and the current address have a relationship of start address> current address, the data storage state shown in FIG.
This means that it is as shown in (1), so that judging only from this condition, the boundary of the area can be changed.
If this condition is not satisfied, the top address and the tail address cannot be rewritten, and the process returns to 8-0 and starts over from the beginning.

If the start address is larger than the current address, the magnitude relationship between the start address and the tail address of the area data buffer 112 (new tail address) is compared next at 8-4, where start address <tail address of the area data buffer 112. If it is an address (new tail address), the address can be rewritten, so the process proceeds to 8-5. However, if the start address is larger than the new tail address, rewriting becomes impossible as shown in FIG. Therefore, 8
If the judgment of -2 or 8-4 is NO, the process proceeds to the process (8-7) for the top address.

Up to this point, no determination has been made as to the case where the tail address rewrite becomes larger than the current one. However, the address rewrite is performed from the track buffer of the higher address in the order of 9-1, 9-2, 9-3. Since the rewriting is performed in order, the area of the next track buffer is not changed until the rewriting of one track buffer is completed. Therefore, when the tail becomes large, it means that the rewriting of the top of the track buffer of the (n-1) th channel in the previous order has been completed, and such a determination is unnecessary.

If all the conditions of 8-2 to 8-4 are satisfied, the tail address of the channel is replaced with the tail address (new address) stored in the area data buffer 112 at 8-5. Then, since the rewriting is completed, the rewriting request of the tail address of the channel is cleared in 8-6.

Next, at 8-7, it is judged whether or not there is a top address rewrite request. If there is a top address rewrite request, the process proceeds to 8-8. In 8-8, if the current address is smaller than the top address (new top address) of the area data buffer 112 (FIG. 10 (2)), it is impossible to rewrite the top address, so that it is determined. > If the top address (new top address) of the area data buffer 112 is satisfied, go to 8-9.

In step 8-9, the top address of the area data register 111 is compared with the top address of the area data buffer 112 in order to determine whether or not the top address is rewritten, so as to determine whether or not to go into the boundary of the n + 1 channel track buffer. If the top address of the data register 111> the top address of the area data buffer 112 is satisfied, the process proceeds to 8-10.
Skip 10 and go to 8-11.

In step 8-10, as shown in FIGS. 10 (3) and 10 (4), in order to determine whether rewriting the top address of the channel does not affect the track buffer of the subsequent channel (n + 1), The start address of the channel next to the current channel is compared with the current address of the current channel. Only when the start address is smaller than the current address and the start address is smaller than the new top address, 8-1.
Proceed to 1. As shown in FIG. 10 (3), when the start address of the n + 1 channel is smaller than the current address, or as shown in FIG. 10 (4), the start address of the n + 1 channel is smaller than the new top address. The data cannot be rewritten because it is affected.

At 8-11, the top address of the area data register 111 of the current channel is replaced with the top address of the area data buffer 112, and the rewriting is completed. Therefore, at 8-12, the top address rewriting request of the channel is cleared. I do.

When the top of the n channel is rewritten while satisfying the conditions of 8-10, the tail address of the n + 1 channel should be rewritten immediately. However, this operation flow is different from the case where the data storage state of the n + 1 changes. Since it is sufficiently fast, there is no problem if the tail address of the (n + 1) th channel is rewritten in the next loop.

<Determination of Track Buffer Area> FIG.
Is a process of the CPU for generating a buffer allocation request to each track, and is started periodically or intermittently by means such as a timer, but may be started after a disk transfer interrupt. .

The CPU 1 reads the buffer 9 from the address register 104 of the DMA controller 10 in 11-1.
The start address and the current address of -1 to 9-3 are read. Next, the margin (effective capacity) of the buffers 9-1 to 9-3 is calculated from the start address and the current address read in 11-2. In the buffer performing the reproducing operation, the margin can be represented by the unsound amount (the data amount which has been written but not read yet) with respect to the total capacity of the buffer. In a buffer performing a recording operation, it can be represented by an unrecorded amount (capacity of an area where data has not yet been written) with respect to the total capacity of the buffer.
In any case, this margin is determined by setting the current address to C, the start address to S, and the total capacity of the buffer to N.
When the current address is larger than the start address, it can be expressed by (N- (CS)) / N, and when the start address is larger than the current address, it can be expressed by (SC) / N. . When the margin is obtained in this way, the CPU 1 determines the area of each track buffer in 11-3.

After the area is determined in 11-3, the process proceeds to 11-4, where the area information (top address and tail address) of the track buffer to be changed is stored in the DMA.
Write to the area data buffer 112 of the controller. The data written in the area data buffer 112 in this manner is transferred to the area data register 111 as described above.

As described above, the load on the buffer fluctuates in the reproducing operation after the editing operation. However, in the case where the edited data is recorded while being reproduced, the load on the reproducing buffer depends on the load. Since the entire DMA transfer operation fluctuates in each buffer, for example, the load on the recording buffer also changes, the buffer state of the recording operation can also change the top and tail addresses in real time.

[0106]

As described above , according to the present invention, during reproduction,
Indicates that the temporary storage means is effective based on the amount of recording data waiting to be read.
When recording, determine whether or not temporary storage
Determines the effective capacity and temporarily stores it according to the determined effective capacity
Addressing the new storage area to the means
Effective use by dynamically changing the storage area of storage means
This allows a plurality of external storage devices with different transfer rates
Edit operation to repeat recording and playback operations using
Buffer capacity to absorb the overhead
Can be secured.

[0107]

[0108]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital recorder according to the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of a DMA controller in FIG. 1;

FIG. 3 is a flowchart illustrating a main operation of a CPU 1 of FIG. 1;

FIG. 4 is a flowchart illustrating the operation of an interrupt routine of CPU 1 of FIG. 1;

FIG. 5 is a flowchart illustrating the operation of the audio input / output devices 8-1 to 8-3 in FIG. 1;

FIG. 6 is a flowchart illustrating an operation of the DMA controller 10 of FIG. 1;

FIG. 7 is a flowchart illustrating an operation of the device controller 11 of FIG. 1;

FIG. 8 is a flowchart illustrating an operation of an area data register of the DMA controller 10 of FIG. 1;

FIG. 9 is a diagram for explaining allocation of capacity to buffers 9-1 to 9-3.

FIG. 10 is a diagram illustrating area conversion of a buffer in connection with the processing in FIG. 8;

FIG. 11 is a flowchart illustrating a process of writing area data to the DMA controller 10 of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 8-1 to 8-3 Audio input / output device 9-1 to 9-3 Buffer 10 DMA controller 11 Device controller 12 Disk

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 27/034 G06F 5/06

Claims (1)

(57) [Claims] And storing the input data in a temporary storage means.
First, the input data stored in the temporary storage
Recording to the external recording means.
While storing the read record data in the temporary storage means,
Read the recorded data from the temporary storage means and reproduce it
In a digital recorder, the readout of the total storage capacity of the temporary storage means at the time of reproduction is performed.
The effective capacity of the temporary storage means is
The amount is determined, and at the time of recording, the total storage capacity of the temporary storage means
From the amount of input data to the effective capacity of the temporary storage means
Determining means for determining, and according to the effective capacity determined by the determining means,
Addressing a new storage area in the temporary storage means
A digital recorder comprising the above means .