JP3132089B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a step of filling a trench. INDUSTRIAL APPLICABILITY The present invention is suitably used in a trench filling process such as a trench isolation, a trench capacitor, a trench plug (buried contact) and other structures.

[0002]

2. Description of the Related Art With miniaturization and high integration of semiconductor devices such as semiconductor integrated circuits, the method of separating elements has been replaced by the conventional LOCOS method having a large dimensional conversion difference, and has been replaced by a groove type element separation having no dimensional conversion difference. For example, a shallow trench method is being used, and its practical use is an important issue.

[0003] In order to form such groove-type element isolation with good performance, a technique capable of satisfactorily embedding grooves of various shapes is required. As a burying technique, a deposition technique (bias ECR-
The CVD method is typical).

In the bias ECR-CVD method, high-density plasma can be formed at low pressure, high-speed growth can be achieved at low temperature, and RF bias is applied to a substrate such as a semiconductor wafer to deposit on a substrate surface. Not only that, the surface of the substrate can be etched at the same time, and therefore, fine trenches (grooves) can be satisfactorily embedded, which is an indispensable technique as a method for embedding fine grooves.

[0005]

However, this embedding technique has the following problems. That is, when the trenches 2a to 2c shown in FIG. 6 are buried by taking advantage of the above advantages, the deposited shape to be formed is dependent on the underlying pattern.
That is, in a large area A on the surface of the substrate 1 such as a Si substrate,
Embedded material forming portion 37 other than the embedded portion to be removed
(Such as SiO ₂ ) remains thick. The reason for this is that in this method, the flattening is performed by using the sputter etching of Ar ions, whose etching speed has an angle dependence, and the deposition speed> the etching speed at the horizontal portion.

Therefore, a step of removing the buried material forming portion 37 to be removed, which is formed in an area other than the buried portion, by mask alignment is required. Therefore, first, at least a certain amount of removal is indispensable in order to secure a margin for mask alignment around the groove 2a. In response to this request, the present inventor has invented a method of securing a margin for resist alignment by using so-called horizontal return etching, and then etching and removing excess buried material (SiO ₂ ) to be removed. In the horizontal return etching method, the etching proceeds in the horizontal direction (horizontal direction in the figure) and the etching proceeds in the vertical direction (vertical direction in the figure) in which neither etching nor deposition proceeds. 37 (Japanese Patent Application No. Hei 1
-277929).

However, this horizontal return etching method requires a certain amount of time to adjust a mask used for removing an extra buried material forming portion 37 over a wide area, and has a problem that the production efficiency is reduced.

The inventor of the present invention has applied for a method of removing an excess filling material by polishing after filling a groove by a bias ECR-CVD method (Japanese Patent Application No. 3-89573).

However, there is a disadvantage that a wide portion of the embedding material tends to remain. For this reason, in the prior art, after filling the groove, a resist pattern is formed in the recess having the buried shape, a second resist is further formed on the entire surface, and the entire surface is substantially flattened with the resist. The protrusions of the material are flattened by polishing, and then etched back to flatten the grooves.
That is, this method uses ordinary CVD, so there is a limit in the filling capability of the groove, and the thickness of the filling material cannot be reduced to zero so as to form a projection at the upper corner of the groove, resulting in non-uniformity. Remains. Therefore, there is a drawback that an etch-back must be performed after polishing in order to sufficiently planarize.

In view of the above, the present invention provides a step of flattening a substrate surface, which has a high productivity without being dependent on the pattern shape of a buried material forming portion to be removed on the substrate after filling the groove formed in the substrate surface. It is an object to provide a method for manufacturing a semiconductor device having the same.

[0011]

The above object is achieved by forming a substrate surface.
Etching and deposition of the filling material into the formed groove
By the ECR-CVD method
In a method of manufacturing a semiconductor device having a
The first resist is applied on the groove where the embedding material is embedded.
Patterning and patterning this first resist
The second resist over the entire surface of the etched substrate to make it almost flat
Then, the entire surface of the substrate planarized by the second resist
Etch back the surface and leave it on the substrate after this etch back.
The first and second resists are completely removed, and the first and second resists are removed.
The problem is solved by a method of manufacturing a semiconductor device, characterized by polishing the upper part of the substrate from which the entire resist has been removed .

[0012]

According to the present invention, the first resist 4a is formed with high accuracy.
Putting on the embedding materials 31 to 33 of the grooves 21 to 23
Even if it is not coated, the second resist 4
b covers the filling materials 31 to 33 of the grooves 21 to 23
Is formed on the entire surface of the substrate 1 so that the resist 4a
Can be compensated by the resist 4b.
Therefore, there is no need to rely on the so-called horizontal return etching method.
And the filling materials 31 to 33 of the grooves 21 to 23 are formed in a predetermined shape.
Can be maintained. As a result, the pattern shape dependency of the buried material forming portion from which a wide pattern is to be removed can be eliminated.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are sectional views showing the steps of the first embodiment of the present invention. As illustrated in FIG. 1B, grooves 21 to 23 formed on the surface of a substrate 1 such as a semiconductor substrate are buried by a deposition means for simultaneously performing etching and deposition as illustrated in FIG. The grooves 21 to 23 are buried. Thereafter, a resist pattern 4a is formed in the concave portion of the buried portion to obtain a structure illustrated in FIG. 1C, and thereafter, the surface is substantially flattened with a second resist 4b to obtain a structure shown in FIG.
FIG. 2B shows a structure as illustrated in FIG. 2B, which is etched back on the entire surface (at this time, the rate of the filling material is increased). Thereafter, the resists 4a and 4b are removed to obtain the structure shown in FIG. 2C, and the structure shown in FIG. 3A is obtained only by polishing + etchback or polishing, and the poly-Si or oxide film is removed to obtain the structure shown in FIG. ). Hereinafter, more specific examples will be described.

Embodiment 1 This embodiment is directed to the manufacture of a miniaturized and integrated semiconductor device such as an VLSI device, in which trenches having active regions having different widths are buried and flattened by using a bias ECR-CVD method. The present invention is applied to the case where a step of forming trench isolation by performing

In the present embodiment, a substrate 1 made of a silicon substrate (an etching stopper layer 41 such as a polysilicon film,
And the polysilicon film has a SiO ₂ film or the like serving as an etching stopper layer 42 at the time of removal) a trench pattern is formed on the surface, the structure of Figure 1 having grooves 21 to 23 (a). For patterning, a photolithography technique using a normal resist process and a silicon dry etching technique can be used. At this time, a wide area A and a narrow area B are formed in the active area. However, although only two examples are shown in the figure for convenience, it goes without saying that there are regions of various widths, in particular, wide portions that are not shown in the figure but run out of space.

Next, the trenches 21 to 23 are buried and flattened by using the bias ECR-CVD method. For example, deposition is performed under the following conditions, and SiO ₂ is embedded.

Gas used: SiH ₄ / N ₂ O = 20/35 sccm Pressure: 7 × 10 ⁻⁴ Torr RF bias: 500 W Microwave: 800 W Thus, the structure shown in FIG. 1B is obtained. The embedding material embedded in the grooves 21 to 23, in this example, SiO ₂ is indicated by reference numerals 31 to 33, and the extra embedding material forming portions deposited on portions other than the embedding portion are indicated by reference numerals 34 to 36.

Next, a resist pattern 4a is formed in the recess. This used normal photolithography. Thus, the structure shown in FIG.

Next, a second resist 4b is formed on the entire surface, as shown in FIG. Further, this is entirely etched back. At this time, the buried material forming portions 34, 35 and 36 made of SiO ₂ to be removed are more etched than the resist.

Working gas: CHF ₃ = 80 sccm Pressure: 6.7 Pa RF application: 0.25 W / cm ² (13.56 MH)
z) Thereby, the shape of FIG. 2 (b) is obtained. Next, the remaining resists 4a and 4b are ashed to obtain FIG. 2C. Next, the remaining buried material forming portions 34 ', 35',
The protrusion 36 'is removed by polishing. The polishing conditions at this time were as follows: pressure: 7 psi, carrier rotation speed: 35 rpm, platen rotation speed: 17 rpm, and slurry: SC-1 (trade name). Thereafter, the remaining portions 34 ', 35', and 36 'are etched back under the conditions of the SiO ₂ polishing (FIG. 3A). At this time, poly-Si 41 is previously formed thick in anticipation of etching back SiO ₂ in the trench. Furthermore, SiO ₂ / poly-Si structure 4
1 and 42 are removed to obtain a flattened structure (FIG. 3B).

According to the present embodiment, in addition to embedding grooves having a high aspect ratio, horizontal reversion is not required, and only the protrusions are polished, so that there is no problem of polishing pattern dependency.

Embodiment 2 First, after going through the steps of FIGS. 1A to 2C as in Embodiment 1, the entire surface is polished under the conditions shown in Embodiment 1 and then etched back. no extra SiO ₂ burying material forming unit 34 to be removed consists of ', 35', removing the 36 'to obtain Figure 4 (a). After that, SiO ₂ / poly-
The Si structures 41 and 42 are removed. As a result, FIG.
(B) As shown in FIG.
A structure having a good withstand voltage can be obtained as element isolation in which 1, 32, and 33 are slightly protruded from the substrate 1. This condition exerts its power in a structure with few wide patterns. The same conditions as in the first embodiment can be used for all conditions.

[0024] Example 3 In the same manner as in Example 1 Figure 1 after a process shown in FIG. 2 (a) from (a), is etched back in the same conditions, a wide place SiO ₂
Are all removed. FIG. 5 shows the structure. After that, the resist is ashed, and the buried material forming portions 34 ", 35", 36 "to be removed, which are made of the remaining protruding SiO ₂ , are polished under the same conditions as in the first embodiment, and poly-Si, thin SiO 2
₂ is removed to obtain a preferable trench structure as shown in FIG.

In this case, since only protrusion-like SiO ₂ is polished, dependency on the polishing pattern can be eliminated. Similarly, the same conditions as in Example 1 can be used.

[0026]

According to the present invention, on the filling material of the groove portion,
After patterning the first resist on the substrate,
A second resist is formed on the entire surface of the substrate to make it approximately flat, and here
Etch back the entire surface of the flattened substrate, and then
After the first and second resists are completely removed, the upper portion of the substrate is ground.
It is made to polish. With this configuration, the first cash register
Is precisely patterned on the filling material of the groove.
Even if not, the second resist fills the groove.
It is formed on the entire surface of the substrate so as to cover the embedded material
Then, the displacement of the first resist is changed by the second resist.
Can be supplemented. Therefore, the so-called horizontal return etchin
The filling material of the groove can be specified without depending on the
Shape, good yield, and high productivity
And a semiconductor device can be obtained by a reliable substrate surface flattening process.

[Brief description of the drawings]

FIG. 1 is a first half process sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view of an intermediate step showing the first embodiment of the present invention.

FIG. 3 is a sectional view of the second half of the process showing the first embodiment of the present invention.

FIG. 4 is a process sectional view showing a second embodiment of the present invention.

FIG. 5 is a process sectional view showing a third embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a conventional problem.

[Explanation of symbols]

Reference Signs List 1 substrate 4a, 4b resist pattern 21-23 groove 31-33 filling material 34-36, 34'-36 'filling material forming portion to be removed

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/304 622

Claims (1)

(57) [Claims] 1. A method for manufacturing a semiconductor device, comprising the step of embedding an embedding material in a groove formed on a substrate surface by ECR-CVD, which is a deposition means for simultaneously performing etching and deposition. A first on the groove in which
Patterning the resist, and the entire surface of the substrate on which the first resist has been patterned;
A second resist is formed on the substrate, and the surface is substantially planarized.
Etching back, the first and second portions remaining on the substrate after the etch back.
The resist is entirely removed, and the upper portion of the substrate from which the first and second resists have been completely removed is removed.
A method for manufacturing a semiconductor device, comprising polishing .