JP3132168B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for compressing and expanding a digital video signal.

[0002]

2. Description of the Related Art In recent years, D1, D2 video tape recorders (hereinafter referred to as VT) for digitizing and recording / reproducing video signals.
Abbreviated as R. ) Has been developed. As consumer devices, video floppy capable of recording and reproducing digital still images and VTR capable of recording digital moving images have been developed. Examples of development of consumer digital VTRs include the Journal of the Institute of Television Engineers of Japan (Vol.45, No.7, pp813-
819, 1991). In this consumer digital VTR, the degree of redundancy of the video signal is recorded by compressing the data amount to about 1/5 using various methods.

[0003] A conventional video signal processing apparatus will be described below. FIG. 3 is a block diagram of a conventional video signal processing device. 4 is an explanatory diagram of the video signal subjected to the discrete cosine transform in FIG. 3, FIG. 5 is an explanatory diagram of quantization, (Table 1) is a table illustrating classification, (Table 2) is a table illustrating quantization, (Table 3) is a table for explaining the offset value, and (Table 4) is a table for explaining the quantization step Brn.

[0004]

[Table 1]

[0005]

[Table 2]

[0006]

[Table 3]

[0007]

[Table 4]

In FIG. 3, reference numeral 1 denotes an input terminal to which a digitized video signal is input, and 2 denotes a luminance signal (hereinafter abbreviated as Y signal) and a color difference signal (R) input to an input terminal 1.
-Y signal, BY signal) into a block of 8 × 8 pixels, and a DCT unit 3 for two-dimensional discrete cosine transform (hereinafter abbreviated as DCT) of an output signal of the shuffling unit 2. , 4 is 6 output from the DCT unit 3
A class discriminator for determining a class of a block from three AC component signals; 5, a first quantizer for quantizing a signal output from the DCT unit 3 based on class information; and 6, an input signal in units of 30 blocks From the result of quantization and variable-length coding of 16 in quantization steps, a quantization controller for obtaining the maximum quantization step with a data amount equal to or less than a predetermined data amount. First in the conversion step
The second quantizer 8 quantizes the signal output from the quantizer 5 of the above, and converts the signal output from the second quantizer 7 into a code of 3 to 16 bits using a Huffman code. The variable length encoder 9 is a formatter for adding an error correction code after formatting the compressed video supplied from the variable length encoder 8 into a predetermined format, and 10 is a VTR for recording and reproducing the output signal of the formatter 9. is there.

Reference numeral 11 denotes a deformatter which corrects an error of a signal reproduced from the VTR 10 and then returns the rearrangement processing performed by the formatter 9. Reference numeral 12 denotes a variable length decoding which decodes a variable length code which is an output signal of the deformatter 11. Bowl, 13
Is an inverse quantizer which multiplies the output signal of the variable length decoder 12 by the reciprocal of the quantization step at the time of recording, and 14 is an inverse quantizer 13
An IDCT unit for performing a two-dimensional inverse DCT operation on the 8 × 8 unit signal output from the
This is a deshuffling unit that converts the digital signal into a parallel signal of a signal, an RY signal, and a BY signal. The converted digital video signal is output to an output terminal 16.

First, the operation at the time of recording will be described. The video signal input to the input terminal 1 (one frame is a Y signal 7
20 × 480 pixels, the color difference signals of the RY and BY signals are each composed of 180 × 480 pixels, and each pixel has an 8-bit value) is supplied to the shuffling unit 2. The shuffling unit 2 blocks the input signal (Y signal, RY signal, BY signal) in units of 8 × 8 pixels. Each of the blocked signals is output to the DCT unit 3 where a two-dimensional DCT operation is performed. The operation of the DCT unit is performed with 12 bits. The operation result is output with a DC value of 9 bits and an AC value of 10 bits. The DCT unit 3 outputs the result of the two-dimensional DCT operation to the class discriminator 4 from a DC value with low horizontal and vertical frequency components to an AC value with high frequency (AC0 → AC1 →→ AC2 →...). FIG. 4 shows this state. Here, AC1 to AC5 are area 0, AC6 to AC20 are area 1, AC21 to AC42 are area 2, AC43 to A.
C63 is defined as area 3.

The class discriminator 4 classifies the signals in block units output from the DCT unit 3 based on the rules described in (Table 1). For example, when the Y signal is a DCT-calculated block and the maximum value of the AC signal in the block is 30, the class is determined to be 2.

When the class value is 3, the first quantizer 5 shifts down the AC value in the block by one bit (1/1).
2) to perform quantization. The quantization result is supplied to a first quantizer 5 and a quantization controller 6.

The quantization controller 6 uses a total of 30 blocks of 20 blocks of Y signal, 5 blocks of RY signal, and 5 blocks of BY signal output from the first quantizer 5 as one unit. The amount of data after quantization and variable length coding is estimated. There are nine types of quantization used in the second quantizer 5,
The contents are shown in (Table 2). Quantization is performed by bit shifting the AC signal in each area. Table 4 shows the relationship between the nine quantization numbers and the sixteen quantization steps Brn. An estimate of the data amount after quantization and variable length coding is obtained for each of the 16 quantization steps Brn. When the quantization step Brn is 0, each block is quantized with the quantization number indicated by the new quantization step Brn ′ obtained by adding an offset value (see (Table 3)) based on the class value of each block to the quantization step 0. I do. The quantization controller 6 compares the number of accumulated code words obtained when the variable-length coding is performed on the quantized signal with a predetermined target value, and sends the maximum quantization step Brn that does not exceed the target to the quantizer 7. Output. The second quantizer 7 performs quantization based on the quantization step value Brn supplied from the quantization controller 6. That is, the offset value of each block is added to this Brn (if the addition result is 15 or more, it is set to 15.), and quantization is performed using the quantization number corresponding to the new quantization step Brn ′.

The variable-length encoder 8 performs variable-length encoding using a Huffman code in which a combination of the number of consecutive zero values of an input signal and the subsequent value is assigned to a short bit length in order of occurrence probability. The AC value of each block is 3-1 except for the DC value.
It is variable-length coded into a 6-bit codeword. Each variable-length coded block includes a 9-bit DC value, a variable-length code, and an end flag (hereinafter abbreviated as EOB) indicating the end of the block. The output signal of the variable length encoder 8 is supplied to a formatter 9, and error correction signals ER0, ER1,.
It is formatted into a prescribed signal format together with class information, color information, and Brn. Then, the output signal of the formatter 9 is recorded on the VTR 10.

Next, the operation at the time of reproduction will be described. VTR
The signal reproduced from 10 is supplied to a deformatter 11. The deformatter 11 corrects errors using the error correction codes ER0 and ER1 added at the time of recording. Then, the compressed video signal is output to the variable length decoder 12. The variable length decoder 12 detects and decodes a codeword from the input signal. The output signal of the variable length decoder 12 is supplied to an inverse quantizer 13 and, based on the quantization conditions (class information, color information, area information, quantization step Brn), the reciprocal of the value used for quantization during recording. Is multiplied.

This processing is performed by the internal operation result "2" of the DCT unit 3.
In the following, an example will be described in which a 10-bit length “5” is output to the classifier 4 by rounding off the lower 2 bits (see FIG. 5). When the pixel belongs to the area 3 of the Y signal block and the quantization step Brn is 6, the first quantizer 5 and the second quantizer 7
Shifts down the input signal by one bit each. As a result, "1" is output to the variable length encoder 8. At the time of demodulation, the inverse quantizer 13 detects the quantization at the time of recording from the quantization conditions (class information, area information, quantization step Brn) and performs the inverse operation. That is, “1” is shifted up by 2 bits and “4” is output to the IDCT unit 14. IDC
The T unit 14 shifts this value up by 2 bits and converts it to 12 bits “16” to perform the IDCT operation. That is, in this case, a quantization error of "4" has occurred with 12-bit precision.

Next, an example will be described in which the internal calculation result "44" of the DCT unit 3 is output to the classifier 4 by rounding off the second least significant bit, thereby outputting "11" having a 10-bit length. Here, when the AC value belongs to the area 3 of the Y signal block of class 3 and the quantization step Brn is 4, the first quantizer 5 shifts down the input signal by one bit, and The shifter 7 shifts down by 2 bits.
As a result, "1" is output to the variable length encoder 8. At the time of demodulation, the quantization at the time of recording is detected from the quantization conditions, and the inverse operation is performed. That is, “1” is shifted up by 3 bits, and “8” is output to the IDCT unit 14. The IDCT unit shifts this value up by 2 bits to obtain 12 bits of “32”.
To perform the IDCT operation. That is, in this case, a quantization error of "12" has occurred with 12-bit precision.

As described above, the inversely quantized signal has the ID
The CT unit 14 performs a two-dimensional IDCT operation and outputs the result to the deshuffling unit 15. The deshuffling unit 15 rearranges the input signal in parallel with the Y signal, the RY signal, and the BY signal, and outputs the rearranged signal to the output terminal 16.

[0019]

However, in the above configuration, when quantization is performed by bit shift in both the first quantizer and the second quantizer, the quantization error accumulates and increases, and the image quality deteriorates. Cause.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a video signal processing apparatus for reducing a quantization error generated in a quantization and inverse quantization process.

[0021]

In order to achieve this object, a video signal processing apparatus according to the present invention inputs a signal which has been subjected to discrete cosine transform and quantizes the input signal based on a first characteristic of the input signal. A first quantizer to be transformed or passed; a second quantizer to which an output signal of the first quantizer is input and quantized based on a second characteristic of the signal subjected to the discrete cosine transform; The first based on the first and second characteristics
And whether the quantization has been performed by both the first and second quantizers from the additional signal supplied from the inverse quantizer and the inverse quantizer performing the inverse operation performed by the second quantizer. A configuration including a quantization discriminator that detects whether or not the signal is output and outputs a control signal, and a corrector that adds or subtracts a predetermined constant value to or from the output signal of the inverse quantizer based on the control signal of the quantization discriminator. have.

[0022]

According to the present invention, the quantization discriminator detects the quantization in each quantizer at the time of recording from the quantization conditions supplied from the inverse quantizer. If the quantization discriminator has a pattern that can correct the quantization error generated in the process of quantization and inverse quantization, it outputs a control signal to the corrector and outputs a predetermined value to the output signal of the inverse quantizer. Is added or subtracted. As a result, the quantization error is reduced, and the deterioration of the image quality is also reduced.

[0023]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a video signal processing device according to the present invention, and FIG. 2 is an explanatory diagram of quantization.

In FIG. 1, reference numeral 51 denotes an input terminal to which a digitized video signal is input, and 52 denotes a Y signal and a color difference signal (RY signal, BY signal) input to the input terminal 51, each of which has eight signals. A shuffling unit for blocking into a signal of × 8 pixels, a DCT unit for two-dimensional DCT of an output signal of the shuffling unit 52, and a class of a block from 63 AC component signals output from the DCT unit 53 The class discriminator 55 to be determined is a DCT unit 5 based on the class information.
A first quantizer for quantizing the signal output from 3;
Reference numeral 6 denotes a quantization controller for obtaining a maximum quantization step with a data amount equal to or less than a predetermined data amount based on the result of quantization and variable length coding of an input signal in units of 30 blocks in 16 types of quantization steps. The second quantizer 8 quantizes the signal output from the first quantizer 55 in the quantization step obtained by the quantization controller 56. The second quantizer 8 converts the signal output from the second quantizer 7 into a Huffman signal. A variable-length encoder 59 for converting after a code of 3 to 16 bits using a code;
A formatter for formatting the compressed video supplied from 8 into a predetermined format, and then adding an error correction code;
0 is a VTR for recording and reproducing the output signal of the formatter 59
It is.

Reference numeral 61 denotes a deformatter which corrects an error of the signal reproduced from the VTR and returns the arrangement conversion processing performed by the formatter 59. Reference numeral 62 denotes a variable length decoding which decodes a variable length code which is an output signal of the deformatter 61. 63, an inverse quantizer for multiplying the output signal of the variable length decoder 62 by the reciprocal of quantization at the time of recording, and 64, a quantization condition (Brn, class signal, color information) supplied from the inverse quantizer 63 , Area information), and a quantizer discriminator 65 for judging whether correction is necessary based on the control signal output from the quantizer discriminator 64, and assigns “1” to the output signal of the inverse quantizer 63. A corrector for adding and subtracting, 66 is an IDCT unit for calculating a two-dimensional inverse DCT of the 8 × 8 unit signal output from the corrector 65, and 67 is an ICT
The output signals of the DCT unit 66 are Y signal, RY signal, BY signal.
This is a deshuffling unit that converts the signal into a parallel signal, and the converted digital video signal is output to an output terminal 68.

First, the operation at the time of recording will be described. A video signal input to the input terminal 51 (one frame is composed of 720 × 480 pixels of Y signal, color difference signals of RY and BY signals are each composed of 180 × 480 pixels, and each pixel is an 8-bit value) is shuffled. It is supplied to the ring part 52. The shuffling unit 52 receives an input signal (Y signal, RY signal, BY signal).
Are divided into blocks of 8 × 8 pixels. Each of the blocked signals is output to the DCT unit 53, where a two-dimensional DCT operation is performed. The operation of the DCT unit 53 is performed with 12 bits. The calculation result is a DC value of 9 bits and an AC value of 10
Output in bits. The DCT unit 53 converts the result of the two-dimensional DCT operation from a DC value with low horizontal and vertical frequency components to an AC value with high frequency (AC0 → AC1 → AC2 →...)
To the classifier 54. FIG. 4 shows this state. Here, AC1 to AC5 are defined as area 0, AC6 to AC5.
20 is area 1, AC21-AC42 is area 2, AC
Areas 43 to 63 are defined as area 3.

The class discriminator 54 classifies the block unit signal output from the DCT unit 53 based on the rules described in (Table 1). For example, when the Y signal is a DCT-calculated block and the maximum value of the AC signal in the block is 30, the class is determined to be 2.

When the class value is 3, the first quantizer 55 shifts down the AC value in the block by one bit (1/1).
2) to perform quantization. The quantization result is supplied to a first quantizer 55 and a quantization controller 56. The quantization controller 56 outputs the Y signal 2 output from the first quantizer 55
0 blocks, 5 blocks of RY signal, 5 blocks of BY signal
The data amount of quantization and variable length coding is estimated using a total of 30 blocks as one unit. Nine types of quantization are used here, and the contents are shown in (Table 2). Quantization is performed by bit shifting the AC signal in each area.
Table 4 shows the relationship between the nine quantization numbers and the sixteen quantization steps Brn. Estimation of data amount after quantization and variable length coding is performed by 16 types of quantization steps B
rn for each rn. When the quantization step Brn is 0, each block is quantized with the quantization number indicated by the new quantization step Brn ′ obtained by adding an offset value (see (Table 3)) based on the class value of each block to the quantization step 0. I do. The quantization controller 56 compares the number of accumulated code words obtained when the 30 blocks are quantized and variable-length coded with a predetermined target value, and determines the maximum quantization step Brn that does not exceed the target by the second quantizer. 57. The second quantizer 57 performs quantization based on the quantization step value Brn supplied from the quantization controller 56. That is, the offset value of each block is added to this Brn (if the addition result is 15 or more, it is set to 15.), and quantization is performed using the quantization number corresponding to the new quantization step Brn ′.

The variable-length encoder 58 performs variable-length encoding by using a Huffman code in which a combination of the number of consecutive zero values of the input signal and the subsequent value is assigned to a short bit length in the order of occurrence probability. The AC value of each block is 3 to
It is encoded into a 16-bit codeword. Each variable-length coded block is composed of a 9-bit DC value and an end flag (hereinafter abbreviated as EOB) indicating the coding and the end of the block. The output signal of the variable length encoder 58 is supplied to a formatter 59 and is formatted into a prescribed signal format together with error correction signals ER0 and ER1, class information, color information, and Brn. The output signal of the formatter 59 is V
Recorded in TR60.

Next, the operation during reproduction will be described. VTR
The signal reproduced from 60 is supplied to a deformatter 61. The deformatter 61 corrects errors using the error correction codes ER0 and ER1 added at the time of recording. And
Thereafter, the compressed video signal is output to the variable length decoder 62. The variable length decoder 62 detects and decodes a codeword from the input signal. The output signal of the variable length decoder 62 is supplied to an inverse quantizer 63, and the quantization condition (class information, color information,
Based on the area information and the quantization step (Brn), quantization at the time of recording is detected, and the inverse processing performed in the quantization is performed.

This processing is referred to as an internal operation result of the DCT unit 3.
20 ", and the lower 2 bits are rounded off to 10
An example in which the bit length “5” is output to the classifier 54 will be described (see FIG. 2). Here, this AC value is class 3
Belong to area 3 of the Y signal block of
When rn is 6, the first quantizer 55 and the second quantizer 57 shift down the input signal by one bit each. As a result, "1" is supplied to the variable length encoder 58. At the time of demodulation, the inverse quantizer 63 detects the quantization at the time of recording from the quantization conditions (class information, area information, quantization step Brn), and performs the inverse operation. That is, "1" is changed to 2
The bit is shifted up and “4” is output to the corrector 65. At the same time, the quantization discriminator 64 supplied with the quantization condition from the inverse quantizer 63 determines that the quantization is performed by both the first quantizer 55 and the second quantizer 57, and A control signal is output to the compensator 65. The compensator 65 adds “1” when the control signal is input and the AC value supplied from the inverse quantizer 63 is positive, and subtracts “1” when it is negative. Therefore, in the case of this example, "5" is output from the corrector 65. The signal output from the corrector 65 is supplied to the IDCT unit 66. The IDCT unit 66 shifts this value up by 2 bits and converts it to 12 bits “20” to perform the IDCT operation. That is, in this case, no quantization error occurs with 12-bit precision.

Next, the internal operation result of the DCT unit 3 is "44".
An example will be described in which the lower 2 bits are rounded off and output to the classifier 54 with a 10-bit length of “11”. Here, when the AC value belongs to the area 3 of the Y signal block of class 3 and the quantization step Brn is 4, the first quantizer 5 shifts down the input signal by 1 bit, and The 2 quantizer 7 shifts down by 2 bits. As a result, "1" is output to the variable length encoder 58. At the time of demodulation, the quantization at the time of recording is detected from the quantization conditions, and the inverse operation is performed. That is, “1” is shifted up by 3 bits, and “8” is output to the corrector 65. The corrector 65 adds “1” to this value based on the control signal supplied from the quantization discriminator 64, and outputs “9” to the IDCT unit 66. The IDCT unit 66 shifts this value up by 2 bits and converts it to 12 bits “36” to perform the IDCT operation. That is, in this case, an error of "8" occurs at 12-bit accuracy, and the quantization error is reduced as compared with the case where no correction is performed.

When quantization is performed by both the first quantizer 55 and the second quantizer 57 as in this example, "1" is added to or subtracted from the output signal of the inverse quantization. The quantization error can be reduced as a whole.

The signal output from the compensator 65 is an IDCT
The two-dimensional IDCT operation is performed by the unit 66 and the deshuffling unit 6
7 is output. The deshuffling unit 67 rearranges the input signal in parallel with the Y signal, the RY signal, and the BY signal, and outputs the rearranged signal to the output terminal 68.

As described above, according to the present embodiment, the signal subjected to the discrete cosine transform is input, and the input signal is quantized or passed based on the first characteristic of the input signal.
A quantizer (55), a second quantizer (57) that receives an output signal of the first quantizer, and performs quantization based on a second characteristic of the signal subjected to the discrete cosine transform, An inverse quantizer (63) for performing an inverse operation performed by the first and second quantizers based on the first and second characteristics; and a first and a second signal obtained from the additional signal supplied from the inverse quantizer. A quantization discriminator (64) for detecting whether or not quantization has been performed by both of the second quantizers and outputting a control signal, and a control of the quantization discriminator for an output signal of the inverse quantizer. By providing a corrector (65) for adding or subtracting a predetermined constant value based on a signal, quantization errors can be reduced, and image quality degradation is reduced.

In the present embodiment, two quantizers used for recording are connected in series. However, two or more quantizers may be used, and the operation of the corrector may be performed with 12-bit precision.

[0037]

As described above, the present invention detects whether or not quantization has been performed by both the first and second quantizers from the additional signal supplied from the inverse quantizer, and outputs a control signal. And a corrector that adds / subtracts a predetermined constant value based on a control signal of the quantizer to the output signal of the inverse quantizer to provide several quantizers. By connecting in series, a quantizer having many quantization steps with a simple configuration such as a bit shift and having a small quantization error can be realized, and its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining quantization in the embodiment;

FIG. 3 is a block diagram showing a configuration of a conventional video signal processing device.

FIG. 4 is a schematic diagram for explaining a conventional discrete cosine transformed video signal.

FIG. 5 is an explanatory diagram for explaining conventional quantization.

[Explanation of symbols]

 Reference Signs List 51 input terminal 52 shuffling unit 53 DCT unit 54 class discriminator 55 first quantizer 56 quantization controller 57 second quantizer 58 variable length encoder 59 formatter 60 video tape recorder 61 deformatter 62 variable Long decoder 63 inverse quantizer 64 quantization discriminator

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 1-162085 (JP, A) JP-A 4-123587 (JP, A) JP-A 5-56275 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 7/24

Claims (1)

(57) [Claims] 1. A discrete cosine transformed signal is input,
A first quantizer that quantizes or passes the input signal based on a first characteristic of the input signal; and a first quantizer that receives an output signal of the first quantizer and that has a discrete cosine transformed signal. A second quantizer for quantizing based on the characteristic of No. 2, an encoder for performing variable length encoding on an output signal of the second quantizer, and a decoding for decoding a variable length code output from the encoder. An inverse quantizer that performs an inverse operation performed by the first and second quantizers on a signal output from the decoder based on the first and second characteristics; A quantization discriminator for detecting whether or not quantization has been performed by both the first and second quantizers from an additional signal supplied from the quantizer, and outputting a control signal; A predetermined constant based on the control signal of the quantization discriminator, Video signal processing device and a corrector for subtracting a.