JP3132212B2 - Crystal oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystal oscillation circuit, and more particularly to a low power consumption type crystal oscillation circuit constituted by complementary MSO transistors.

[0002]

2. Description of the Related Art FIG. 5A shows a basic circuit configuration of a conventional crystal oscillation circuit. As shown in FIG.
Channel MOS transistor 51 and N-channel MO
A CMOS inverter composed of an S transistor 52 is used as an amplifier, and a feedback circuit formed by a crystal oscillator 53, capacitors 54 and 55, and a resistor 56 is connected to the input / output terminal of the CMOS inverter to form a crystal oscillation circuit. I have. In FIG. 5A, the crystal oscillation circuit includes:
Are constituted by CMOS transistors, such as P-channel MOS transistor 51 and N-channel MOS transistor 52 as described above, since the gate voltage V _G of the CMOS inverter has a vibration waveform of a state of substantially sinusoidal, Each of the P-channel MOS transistor 51 and the N-channel MOS transistor 52 has a through current I _C (P-channel M
(OS transistors 51 → 401 and N-channel MOS transistors 52 → 402) flow, thereby increasing the current consumption of the crystal oscillation circuit. This through current I
_C, in order to increase by approximately proportional to the square of the supply voltage V _D, the power consumption also increases rapidly with the power supply voltage rises.

In order to suppress the increase in power consumption, a method of providing a constant voltage source and limiting the voltage applied to the crystal oscillation circuit has been used. In a crystal oscillation circuit,
Since generally the oscillation amplitude at the time of rising is small, in order to grow the oscillation in a short time, it is advantageous to directly apply the power supply voltage V _D to the crystal oscillation circuit. FIG.
Is the Japanese Patent Publication No. 60-281
This is a low power consumption type crystal oscillation circuit described in Japanese Patent Publication No. 62-62. In FIG. 6, when the power is turned on, the switch 69 is turned on to reset the flip-flop 64, and the power supply voltage V _D is applied to the crystal oscillation circuit 61. As a result, the oscillation of the crystal oscillation circuit 61 rapidly becomes stable. In the first frequency dividing circuit 62 and the second frequency dividing circuit 63, the oscillation output signal of the crystal oscillation circuit 61 is counted, inputted to the flip-flop 64 after a predetermined number is counted, and the flip-flop 64 is set.

When the flip-flop 64 is set,
The first switch 69 is turned off, and the low power supply voltage _{VDL which} is lower by the forward voltage drop of the diodes 67 and 68 is supplied to the crystal oscillation circuit 61, thereby reducing the current flowing into the crystal oscillation circuit 61. As a result, low power consumption has been achieved. Also, when the power supply voltage V _D is lowered by the power supply fluctuation or the like, this is detected by the voltage detection circuit 65, the switch 69 again via the OR circuit 66 is turned on, the power supply voltage V _D to the crystal oscillation circuit 61 Is supplied, and the stable operation state is automatically maintained.

[0005]

In the conventional crystal oscillation circuit shown in FIG. 6, the output of the crystal oscillation circuit is counted, and after a predetermined time, the voltage applied to the crystal oscillation circuit is reduced to a low voltage. However, if the count value at the time of switching is set to a low value, the power supply is switched while the oscillation amplitude is not sufficiently stabilized, and a certain time is required until oscillation stabilizes. .

If the count value at the time of switching is set to a high value, a high power supply voltage is directly applied to the crystal oscillation circuit for a while even after the oscillation amplitude is sufficiently stabilized, so that power consumption increases. There is a drawback that it is difficult to appropriately set the switching timing through the setting of the count value.

Further, diodes 67 and 68
Power supply voltage drop by the forward drop voltage of
When the power supply voltage increases, as shown in FIG. 4, as the power supply current increases, the voltage applied to the crystal oscillation circuit also increases, and the voltage dependence of the CMOS inverter, crystal oscillator, capacitance, etc. However, there is a drawback that high-precision frequency stability cannot be obtained.

[0008]

A crystal oscillation circuit according to the present invention comprises a crystal oscillator formed by a CMOS inverter, a resistor and a crystal oscillator, and a predetermined power supply voltage source and a power supply terminal of the crystal oscillator. N channels inserted and connected
Comprising a Le depletion MOS transistor, at the time of power-on for the crystal oscillator by the power supply voltage source, in response to the oscillation output of the crystal oscillator, the previous oscillation rising state in which the crystal oscillator reaches a normal oscillation state Detecting the oscillation stop state and outputting a first control signal, detecting the oscillation state when the crystal oscillator reaches a normal oscillation state and outputting a second control signal, and outputting the first and second control signals. the N Cha via two control signals
An oscillation stop detector for controlling the conduction state of the flannel depletion MOS transistor.

[0009]

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment employs a P-channel M
OS transistor 14, N-channel MOS transistor 15, resistor 16, crystal oscillator 17, capacitors 18 and 19
Oscillator Stop Detector 1
2 and an N-channel depletion MOS transistor 13. This embodiment and a conventional example (FIG. 5)
(Refer to (a)) is that the power supply to the crystal oscillator 11 is performed via the N-channel depletion MOS transistor 13 in the present invention. That is, the oscillation stop detector 12 is connected to the output terminal 71.

In FIG. 1, the threshold voltage V _TD of N-channel depletion MOS transistor 13 has an absolute value slightly larger than the sum of the threshold voltages of P-channel MOS transistor 14 and N-channel MOS transistor 15. Set to value. This is a voltage necessary for the crystal oscillation circuit to oscillate stably, and is usually around 2V. Immediately after the power supply voltage V _D is turned on,
Since the crystal oscillator 11 is still in the oscillation stop state, the oscillation stop detector 12 outputs an “H” level. Also, an N-channel depletion MOS transistor 1
No. 3 is always on because the voltage V _D is applied to the gate, so that the potential of the node A becomes V _D. Thus a state in which the power supply voltage V _D is applied directly to the crystal oscillator 11, a rapid oscillation is started. Crystal oscillator 1
With the start of the oscillation at 1, the oscillation stop detector 12 immediately outputs the "L" level, and the potential of 0 V is applied to the gate of the N-channel depletion MOS transistor 13 for a while. Since the N-channel depletion MOS transistor 13 is of a source follower type in which the drain is connected to the power supply, the potential of the source, that is, the potential of the node A is equal to the N-channel depletion M
The voltage drops to the threshold voltage V _TD (about 2 V) of the OS transistor 13. As a result, the voltage applied to the crystal oscillator 11 decreases, so that the power consumption of the crystal oscillator 11 is suppressed to a low value.

FIG. 2 is a circuit diagram showing a configuration example of the oscillation stop detector 12 described above. This circuit is a circuit example created by the inventor of the present invention (Japanese Patent Application No. 3-9872). 2 shows a circuit of an oscillation stop detector that can stably detect an oscillation stop with power consumption. In FIG. 2, when the oscillation of the crystal oscillator 1 is stopped (including when the oscillation rises after the power is turned on), since the clock of the oscillation output is not input from the clock input terminal 28, the inverter 21, the capacitor 22, and the diode are connected. The booster circuit composed of the N-channel MOS transistors 23 and 24 does not operate, and the potential on the input side of the inverter 27 becomes “L” level via the smoothing circuit composed of the resistor 25 and the capacitor 26, The output level becomes “H” level, and an “H” level potential is output from the oscillation stop detection output terminal 29. When the oscillation of the crystal oscillator 1 starts, a clock corresponding to the oscillation output is input from the clock input terminal 28, so that the booster circuit operates to charge the smoothing circuit. The potential on the input side becomes “H” level, and an “L” level potential is output to the oscillation stop detection output terminal 29 via the inverter 27.

FIG. 3 is a diagram showing a temporal change of the power supply voltage (the voltage at the node A) directly supplied to the crystal oscillator 11 in FIG. 3, the time of T = 0 of the time axis shows the timing of on of the power supply voltage V _D, T = T
_S indicates the timing corresponding to the end point when the output level of the oscillation stop detection output terminal of the oscillation stop detector 13 is kept at 0V. As shown in FIG. 3, in the time zone (T = 0 to T _S ) from when the power supply voltage V _D is applied to when a normal oscillation state is reached, the oscillation stop detector 1
2 is output as "H" level,
Since this "H" level potential is applied to the gate of the N-channel depletion MOS transistor 13 in FIG. 1, the N-channel depletion MOS transistor 13 is turned on, and the potential of the node A becomes V _D Becomes That is, in the oscillation stop time zone of T = 0 to T _S , the power supply voltage V _D is directly applied to the crystal oscillator 11 as shown in FIG. As a result, when the oscillation is started and a normal oscillation state is set, the output level of the oscillation stop detector 12 becomes "L" level, and the potential of this "L" level becomes N-channel depletion M in FIG.
Applied to the gate of the OS transistor 13. Thereby, the N-channel depletion MOS transistor 1
3, the potential at the node A, that is, the power supply voltage to the crystal oscillator 11 becomes equal to the absolute value of the threshold voltage V _TD of the N-channel depletion MOS transistor 13 as shown in FIG. The potential drops to approximately the same potential (about 2 V).

FIG. 4 is a graph showing the relationship between the power supply current and the power supply voltage in a crystal oscillation circuit in which no measures are taken to reduce current consumption, a conventional crystal oscillation circuit in which measures are taken to reduce current consumption, and a crystal oscillation circuit according to the invention. 401, 402 respectively
FIGS. 4A and 4B are diagrams clearly shown as 403 and are shown in a manner to compare and contrast the characteristic difference between the crystal oscillation circuits. In FIG. 4, in the case of a crystal oscillation circuit for which no countermeasures are taken, the value of the power supply current increases in proportion to the square of the power supply voltage, as is clear from the characteristic 401. In the case of the conventional example, as seen from the characteristic 402, the characteristic 40
1, the power supply voltage shifts to the higher side by the forward voltage (2V _F ) of the diode-connected N-channel MOS transistors 23 and 24, and although the power consumption is reduced by that amount, the power supply voltage is reduced. The degree to which the power supply current increases with the rise is extremely large. However, in the case of the characteristic 403 of the present invention, as shown in FIG. 3, after the power supply voltage reaches the absolute value of the threshold voltage V _TD of the N-channel depletion MOS transistor 13,
Even if the power supply voltage rises, the value of the power supply current is kept at a constant value. That is, in the present invention, it can be seen that low power consumption of the crystal oscillation circuit is realized over a wide power supply voltage range. In addition, since the power supply voltage directly supplied to the crystal oscillation circuit is kept constant over a wide power supply voltage range, the P-channel MOS transistor 14 and the N-channel MOS transistor In the circuit components such as the CMOS inverter 15 including the crystal oscillator 17, the crystal oscillator 17, the capacitors 18 and 19, the dependency on the supply power voltage does not appear. This also suppresses the power supply voltage dependence of the oscillation frequency, thereby realizing a crystal oscillator with high oscillation frequency accuracy.

[0016]

As described above, the present invention includes the oscillation stop detecting circuit for detecting the stop of the oscillation output, and the power supply voltage supplied to the crystal oscillator is controlled by a predetermined value when the oscillation of the crystal oscillator starts. By maintaining the potential at a constant potential, power consumption can be reduced over a wide power supply voltage range, and the oscillation frequency can be maintained with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing an oscillation stop detector according to the embodiment.

FIG. 3 is a diagram showing an operation including the oscillation stop detector.

FIG. 4 is a comparison diagram of power supply voltage versus power supply current characteristics.

5A and 5B are a circuit diagram of a crystal oscillator and a diagram showing a through current characteristic of the crystal oscillator.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

Reference Signs List 11 crystal oscillator 12 oscillation stop detector 13 N-channel depletion MOS transistor 14 P-channel MOS transistor 15, 23, 24 N-channel MOS transistor 16, 25 resistor 17 crystal oscillator 18, 19, 22, 26 capacity 21, 27 inverter 61 Crystal oscillation circuit 62 First frequency divider 63 Second frequency divider 64 Flip-flop 65 Voltage detector 66 OR circuit 67, 68 Diode 69, 70 Switch

Claims (1)

(57) [Claims] 1. A crystal oscillator formed by a CMOS inverter, a resistor and a crystal oscillator, and an N-channel depletion MOS inserted and connected between a predetermined power supply voltage source and a power supply terminal of the crystal oscillator.
When the power supply to the crystal oscillator is turned on by the transistor and the power supply voltage source, in response to the oscillation output of the crystal oscillator, an oscillation stop state including an oscillation rising state before the crystal oscillator reaches a normal oscillation state is set. And outputs a first control signal, detects an oscillation state when the crystal oscillator reaches a normal oscillation state, and outputs a second control signal, and outputs the first and second control signals. Through the
An oscillation stop detector for controlling a conduction state of the N-channel depletion MOS transistor.