JP3132895B2 - Random access memory test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (IC, LS)
I, VLSI, etc., and a plurality of random access memories (hereinafter, referred to as RAMs) incorporated in an IC.
And a RAM test circuit for performing a function test for the RAM test circuit.

[0002]

2. Description of the Related Art Conventionally, when performing a function test on a plurality of RAMs built in an IC, for example, test data is externally supplied to the IC using a tester, and each of the built-in RAMs is tested.
Each time, the writing operation and the reading operation for the test data are repeatedly performed, and the output of each RAM is output to the data bus to verify the function of the RAM.

[0003]

However, according to the conventional RAM testing method, when there are many RAMs built in the IC, the output of each RAM is sent to the data bus in order, and the output data on the data bus is output. Therefore, the output of each RAM output to the data bus cannot be verified at the same time. Therefore, there is a problem that the verification procedure becomes complicated due to an increase in verification data, and it has been difficult to solve them.
An object of the present invention is to provide a RAM test circuit which solves the problems of the prior art, that the function verification is complicated and the verification time of a plurality of RAMs is long.

[0004]

In order to solve the above-mentioned problems, the present invention provides test data to a plurality of RAMs incorporated in an integrated circuit, and performs a write operation and a read operation to each of the RAMs. In addition, in the RAM test circuit for verifying the function, a plurality of data outputs of each
Multi-level level that generates fewer multi-level voltage levels than
A multi-valued voltage level to a predetermined threshold voltage
, And the logic of the detection result is obtained
Multi-valued logic circuit for compressing data output
And a plurality of data compression circuits. The output side of each data compression circuit is connected to each bit of a data bus composed of a plurality of bits.

[0005]

According to the present invention, since the RAM test circuit is configured as described above, when a plurality of data written to each RAM is read, a plurality of data outputs are output to one data compression circuit. Ru is compressed to the output. That is, read from RAM
The plurality of output data are input to the multi-level level generation circuit.
Then, a multi-valued voltage level is generated, and the multi-valued voltage level is generated.
Level is detected by a multi-level logic circuit at a predetermined threshold voltage.
And the logic of the detection result is taken to one data output
Compressed. The data compressed by each data compression circuit is
At the same time, it is output to each bit of the data bus.

[0006]

FIG. 1 is a schematic block diagram of a RAM test circuit showing an embodiment of the present invention.

[0007] The RAM test circuit is, for example three, which are incorporated in an IC memory capacity 2 ^N × 32 bit RAM1-
This is a circuit for performing functional tests 1-1 to 1-3. Each RAM1-
Reference numerals 1 to 1-3 denote an address input terminal ADR connected to an N-bit address bus ABUS, a write enable terminal WE, and 32-bit data input terminals IN to which write data INA, INB, and INC are respectively input, and 32.
Each has a bit data output terminal OUT.
Two input OR gates 10-1 to 10-3 are connected to the write enable terminals WE of the RAMs 1-1 to 1-3, respectively. First of each OR gate 10-1 to 10-3
Are commonly connected to a test terminal TEST1, and a second input terminal is connected to the control terminals WEA, WEB, W
Each is connected to EC.

The data output terminal OUT of each of the RAMs 1-1 to 1-3 has 32- bit output terminals OUTA and OUT.
B and OUTC are connected respectively, and the input sides of the data compression circuits 20-1 to 20-3 are connected. Each of the data compression circuits 20-1 to 20-3 is provided with a RAM1-1.
To compress 32- bit data output from the data output terminals OUT of the first to third data into one data.
2-1 to 22-3. Each of the detection circuits 21-1 to 21-3 is activated by the signal of the test terminal TEST2, and the 32 bits of each of the RAMs 1-1 to 1-3 are activated.
Generating a voltage level of the multilevel from the data output of Tsu bets, a circuit for determining the logic of the detection result after detecting the voltage level by a predetermined threshold value, the RAM1-1~1-3
Data input terminal I connected to the data output terminal OUT of
N and a data output terminal OUT.
Each of the tri-state buffers 21-1 to 21-3 is connected to each of the detection circuits 20-1 to 20-3 by a signal of a test terminal TEST2.
This is a circuit for controlling whether or not to output the output data of 20-3 to, for example, a 32-bit data bus DBUS. The input terminals are connected to the data output terminals OUT of the respective detection circuits 21-1 to 21-3. In both cases, the output terminals are connected in order from the lower bit of the 32-bit data bus DBUS. This tri-state buffer 22-
The test terminals 1 to 22-3 operate as buffers for driving the data outputs of the detection circuits 21-1 to 21-3 when the test terminal TEST2 is "1". When the test terminal TEST2 is "0", the output terminals thereof operate. Becomes a high impedance state.

The operation of the RAM test circuit configured as described above will be described. First, the test terminal TEST1 is set to “1”.
Then, RA is output through the OR gates 10-1 to 10-3.
M1-1 to 1-3 become the write mode. An N-bit write address is transferred from the address bus ABUS to each RAM1-
1 to 1-3 address input terminals ADR and write data INA, INB, IN of 32 bits each.
When C is input to the data input terminal IN, the RAM
1-1 is the data INA and RAM1-2 is the data INB.
However, the data INC is written into the RAMs 1-3. Next, when the test terminal TEST1 is set to “0”, O
RAM 1-1 to RAM 1 by R gates 10-1 to 10-3
-3 is in the read mode, and the data written to the RAMs 1-1 to 1-3 specified by the address of the address bus ABUS is output from each data output terminal OUT.

When the test terminal TEST2 is set to "1",
The data compression circuits 20-1 to 20-3 are activated, and each of the RAMs 1-1 to 1-1 according to the address of the address bus ABUS is activated.
-3 output data from each of the data compression circuits 20-1 to 20-
After being compressed at 3, the data is output to the data bus DBUS. At this time, since the output data of each of the RAMs 1-1 to 1-3 output to the 32-bit data bus DBUS corresponds to each bit of the data bus DBUS, the output of each of the RAMs 1-1 to 1-3 is output. Transfer data to the data bus DB
It is possible to output to the US and read the output data at the same time. Therefore, function verification can be performed easily and quickly,
The RAMs 1-1 to 1-3 can be tested efficiently.

FIG. 2 shows each of the detection circuits 21-1 to 21-1 shown in FIG.
It is a circuit diagram which shows the example of a structure of 21-3. This detection circuit has 32-bit input terminals IN1 to IN32, to which a multi-level generation circuit 30 is connected, and further to the output side, a multi-level logic circuit 40 is connected. The multi-level generation circuit 30 is a circuit that generates a 16-bit multi-level voltage level from 32-bit data input from the input terminals IN1 to IN32, and has 32 gates that are gate-controlled by the signal of the test terminal TEST2. N-channel type M
OS transistors (hereinafter referred to as NMOS) 31-1 to
31-2. Each NMOS 31-1 to 31
The source of −32 is connected to each of the input terminals IN 1 to IN 32, and the drains thereof are commonly connected one by one to form a 16-bit input terminal N 1 to N 1 of the multi-valued logic circuit 40.
6 respectively. The multi-valued logic circuit 40 has one
A circuit for detecting a multi-level voltage level input to the 6-bit input terminals N1 to N16 by a predetermined threshold voltage and then calculating the logic of the detection result. Eight two-input NAND gates 41-1 to 41-8 and eight two-input NOR gates 41-9 to 41-16 are provided.

Eight NAND gates 41-9 to 41-8
Among the output terminals NN1 to NN8, a 4-input NOR gate 42-1 is connected to NN1 to NN4, and NN5 to NN
8 is connected to a 4-input NOR gate 42-2.
Output terminals N of eight NOR gates 41-9 to 41-16
Of N9 to NN16, NN9 to NN12 have 4 inputs A
The ND gate 42-3 is connected, and the 4-input AND gate 42-4 is connected to NN13 to NN16. Output terminals NNN of two NOR gates 42-1 and 42-2
A 2-input AND gate 43-1 is connected to 1, NNN2, and the output side is connected to the terminal ALL1. 2
Output terminals NNN of AND gates 42-3 and 42-4
3, a two-input AND gate 43-2 is connected to NNN4, and its output side is connected to the terminal ALL0. The output terminal OUT of the detection circuit is constituted by these two terminals ALL1 and ALL0.

3 (a) to 3 (c) are voltage waveform diagrams of the detection circuit shown in FIG. 2, wherein FIG. 3 (a) is a voltage waveform at the input terminal IN1, and FIG. 3 (b) is a voltage waveform at the input terminal IN2. The waveform and FIG. 3C are the voltage waveforms at the input terminal N1. The operation of FIG. 2 will be described with reference to these figures. First, when a voltage of logic "1" is input to the test terminal TEST2, the NMOSs 31-1 to 31-32 in the multi-level generation circuit 30 are started.
Is turned on. When 32-bit data output from the data output terminals OUT of the RAMs 1-1 to 1-3 in FIG. 1 are input to the input terminals IN1 to IN32, they are passed through the NMOSs 31-1 to 31-32 to form a NAND. Gates 41-1 to 41-8 and NOR gates 41-9 to 41
-16 are sent to the input terminals N1 to N16. here,
As shown in FIGS. 3A and 3B, the input terminals IN1 and I
The voltage of N2 is added by the NMOSs 31-1 and 31-2, and the output voltage becomes a voltage waveform as shown in FIG. 3C, and the NAND gate 41-1 and the NOR gate 41-1.
9 to the input terminal N1. Input terminals IN1 and IN2
Are both logic "1" voltages, a high voltage is sent to the input terminal N1, and when both input terminals IN1 and IN2 are logic "0" voltages, a low voltage is sent to the input terminal N1. When the input terminal IN1 is at a logic “1” voltage and the input terminal I
When N2 is a logic “0” voltage or when the input terminal IN1
Is a logic "0" voltage and the input terminal IN2 is a logic "1" voltage, an intermediate voltage is sent to the input terminal N1. For example, if the logical threshold voltages of the NAND gates 41-1 to 41-8 are set to the "1" detection level as shown in FIG. 3C, both the input terminals IN1 and IN2 have the logical "1" voltage. , The output terminal NN1 of the NAND gate 41-1
Output a logical "1" voltage. Similarly, output terminals NN2 of the other NAND gates 41-2 to 41-8
NN8 also output a logical "1" voltage or a logical "0" voltage. The NOR gate 42-1 performs a NOR operation on the voltages of these output terminals NN1 to NN4. Terminal NNN
The voltages of 1 and NNN2 are ANDed by the AND gate 43-1 and output from the terminal ALL1. Therefore, when all of the input terminals IN1 to IN32 are at the logical "1" voltage, "1" is output to the terminal ALL1.

On the other hand, NOR gates 41-9 to 41-16
Is set to the "0" detection level as shown in FIG. 3C, the output terminal NN9 of the NOR gate 41-9 when both the input terminals IN1 and IN2 are at the logical "0" voltage. Output a logic "0" voltage. The voltages output from the output terminals NN9 to NN12 of the NOR gates 41-9 to 41-12 are ANDed by the AND gate 42-3, and further output from the output terminals NN13 to NN16 of the NOR gates 41-13 to 41-16. The output voltage is ANDed by the AND gate 42-4. The voltages output from the output terminals NN3 and NN4 of these AND gates 42-3 and 42-4 are ANDed by the AND gate 43-2, and the result is output from the terminal ALL0. Therefore, when all of the input terminals IN1 to IN32 are at the logical "0" voltage, "0" is output to the terminal ALL0.

As described above, the terminal A compressed by the detection circuit
The data of the output terminal OUT composed of LL1 and ALL0 is
The data is output to the data bus DBUS via the tri-state buffers 22-1 to 22-3 in FIG. Since this detection circuit is composed of the multi-level generation circuit 30 and the multi-level logic circuit 40, it has an advantage that data compression can be easily performed with a small number of elements.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, the RAM 1-1 of FIG.
1-3 may be any number other than three, or their memory capacity may be any number of bits other than 2 ^N × 32 bits. Address bus ABU accordingly
S, data bus DBUS, and data compression circuit 20-1
The number of bits, the number of bits, and the like may be changed. Also,
The detection circuits 21-1 to 21-3 in each of the data compression circuits 20-1 to 20-3 in FIG. 1 may be configured using transistors, gate circuits, and the like other than those in FIG. Further, each of the tri-state buffers 22-1 to 22-3 may be configured by another gate circuit such as a tri-state inverter.

[0017]

As described in detail above, according to the present invention, a data compression circuit is provided on the output side of the RAM, and the output side of the data compression circuit is connected to each bit of the data bus. The output data of the RAM is compressed by the data compression circuit to generate data to be output to the data bus, and the output data of each data compression circuit can be output to the data bus at the same time. Therefore, the output data of each RAM output to the data bus can be simultaneously verified, and IC
The function test of a plurality of RAMs built in the CAM can be easily and quickly performed. Further, since the data compression circuit includes the multi-value level generation circuit and the multi-value logic circuit , it is possible to easily perform data compression with a small number of elements.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of a RAM test circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a detection circuit illustrated in FIG. 1;

FIG. 3 is a voltage waveform diagram of the detection circuit shown in FIG.

[Explanation of symbols]

1-1 to 1-3 RAM 10-1 to 10-3 OR gate 20-1 to 20-3 Data compression circuit 21-1 to 21-3 Detection circuit 22-1 to 22-3 Tristate buffer 30 Multi-level level Generation circuits 31-1 to 31-32 NMOS 40 Multi-valued logic circuits 41-1 to 41-8 NAND gates 41-9 to 41-16, 42-1, 42-2 N
OR gate 42-3, 42-4, 43-1, 43-2 A
ND gate ABUS Address bus DBUS data bus INA, INB, INC Write data TEST1, TEST2 Test terminal

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/16 G01R 31/28 H01L 21/66

Claims (1)

(57) [Claims] 1. A plurality of random access memories built in an integrated circuit.
In a random access memory test circuit for performing function verification by providing test data to an access memory and causing each of the random access memories to perform a write operation and a read operation , Multiple data output
To generate fewer multi-valued voltage levels
A multi-level level generating circuit for determining the multi-level voltage level
After detecting with the threshold voltage of
And a multi-valued logic circuit for compressing the data into one data output.
A random access memory test circuit, comprising: a plurality of data compression circuits provided respectively; and an output side of each of the data compression circuits is connected to each bit of a data bus composed of a plurality of bits .