JP3133472B2 - Semiconductor light receiving element and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light-receiving element manufactured using a semi-insulating InP substrate and a method for manufacturing the same, and more particularly to a semiconductor light-receiving element for performing high-speed photoelectric conversion of light in a 1 .mu.m band wavelength region. And a method of manufacturing the same.

[0002]

2. Description of the Related Art As a conventional example of a semiconductor light-receiving element manufactured using a semi-insulating InP substrate, for example, an InGaAs / InP-based light-receiving element disclosed in Document a (Technical Research Report OQE89-20 of the Institute of Electronics, Information and Communication Engineers). was there. FIG. 11 is a sectional view schematically showing the configuration of the semiconductor light receiving element.

[0003] In the semiconductor light receiving element disclosed in the document a,
On a semi-insulating InP substrate 11, an n ⁺ -InP buffer layer 13, an n ^-- InGaAs light absorbing layer 15, and an n ^--In
The P window layers 17 are provided in this order. Further, the n ⁻ -InP window layer 17 is provided with a p-type diffusion region 19 formed by selectively diffusing Zn or Cd and having a lower end reaching the boundary between the window layer 17 and the light absorbing layer 15. Furthermore, in order to reduce the element capacity and enable high-speed operation, these n ⁺ -InP buffer layers 1
3, n ⁻ -InGaAs light absorbing layer 15 and n ⁻ -InP
The window layer 17 is a mesa-shaped structure portion 21 (hereinafter, “mesa portion 21”). And this mesa unit 21
Are covered with an insulating film 23. However, on a predetermined portion of the p-type diffusion region 19, a part of the insulating film 23 is removed, and the p-side electrode 25 is provided there. The p-side electrode 25 is provided with a p-side wiring electrode 25a extending from above the mesa 21 to the substrate surface. Also, n
^- -InP even on a predetermined portion of the window layer 17, an insulating film 2
3 is partially removed, and an n-side electrode 27 is provided there. The n-side electrode 25 is provided with an n-side wiring electrode 27a extending from above the mesa 21 to the substrate surface.

Further, as another conventional example of a semiconductor light-receiving element manufactured using a semi-insulating InP substrate, see, for example, Reference b (Supplementary Proceedings No. 28pF-38th Spring Meeting of 1991 Spring Alliance, 1991). 1) InGaAs /
There was an InP-based light receiving element. FIG. 12 is a sectional view schematically showing the configuration of the semiconductor light receiving element.

[0005] In the semiconductor light-receiving element disclosed in Document b,
On a semi-insulating InP substrate 31, an n ⁺ -InP buffer layer 33, an n ^-- InGaAs light absorbing layer 35, and an n ^--In
P window layers 37 are provided in this order. This n
^- The -InP window layer 37, elements similar to p-type diffusion region 39 described with reference to FIG. 11 is provided. Further, these n ⁺ -InP buffer layers 33 and n ^--In
GaAs light absorbing layer 35 and n ⁻ -InP window layer 37
However, similar to the element described with reference to FIG. 11, a mesa-shaped structure portion 41 (hereinafter, “mesa portion 41”) is provided. However, the plane area of the buffer layer 33 is equal to the light absorption layer 35 and p ⁺ I
The plane area of each nP layer 37 is wider than each plane area. The mesa 41 is covered with an insulating film 43. However, on a predetermined portion of the p-type diffusion region 39, a part of the insulating film 43 is removed, and the p-side electrode 45 is provided there. The p-side electrode 45 is provided with a p-side wiring electrode 45a extending from above the mesa 41 to the substrate surface. Also, on a predetermined portion of the n ⁺ -InP buffer layer 33, a part of the insulating film 43 is removed, and the n-side electrode 47 is provided there. The n-side electrode 47 is provided with an n-side wiring electrode 47a reaching the surface of the substrate. In this device, the carrier transit time is shortened by reducing the layer thickness of the n ^- InGaAs light absorption layer 35 (the thickness is set to 0.3 μm in the literature), thereby shortening the response time. Further, the series resistance of the element is reduced by setting the carrier concentration of the n ⁺ -InP buffer layer 33 to 10 ¹⁷ cm ⁻³ or more, and the element capacity is increased by forming the light receiving portion into a mesa (mesa portion 41). , The circuit constant (CR time constant) is reduced, and the response time is shortened.

Further, as another conventional light receiving element,
In some cases, the light-receiving element described with reference to FIG. 12 is changed to a back-illuminated type so that flip-chip mounting is possible. FIG. 13 is a sectional view schematically showing the structure of the light receiving element. In FIG. 13, the same components as those shown in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted.

In the light receiving element of this example, a mesa section (light receiving section)
Protrusions 51a and 51b, which are approximately the same height as the mesa 41, are provided on the substrate around the base 41. And
A p-side electrode 45 and a p-side electrode 45 are formed on the p ⁺ diffusion region 39 of the mesa portion 41.
The side wiring electrode 45a and the bump 53a are stacked. Also, the n-side wiring electrode 47 protruding from the mesa portion 41
“a” extends to the projection 51a, and the bump 53b is stacked on the wiring electrode 47a on the projection 51a. The bump 53c is also laminated on the other convex portion 51b.

[0008]

However, document a
In the conventional semiconductor light receiving element disclosed in the above, since the height of the mesa section 21 is about 4 to 6 μm, a large step is formed between the substrate surface and the mesa section 21. Therefore, the p-side wiring electrode 25
In each of the a and n-side wiring electrodes 27a, a step is likely to occur between the shoulder of the mesa 21 and the surface of the substrate. Such a disconnection occurs in the light absorbing layer 3 even in the light receiving element disclosed in Document b.
Although 5 is thin, it is particularly likely to occur in the p-side wiring electrode 45a. When the disconnection occurs, the element is released, so that a wiring structure in which the disconnection hardly occurs is desired. In addition, since it is not easy to form the wiring electrodes on the side surfaces of the mesa portion 21 and the mesa portion 41 in the first place, an improvement in that point is desired.

Further, in a device having a pin structure composed of an n ⁺ buffer layer, a light absorbing layer and a p ⁺ layer, such as a light receiving device disclosed in Document a or Document b, reverse bias applied to the pin structure portion When the depletion layer width becomes larger than the thickness of the light absorption layer and increases to the n ⁺ buffer layer near the light absorption layer by increasing the voltage, the rate of increase of the depletion layer width decreases, and therefore the rate of increase of the maximum electric field strength And the maximum electric field intensity rises sharply, which causes a problem that the dark current sharply increases.

In a back illuminated light receiving element as shown in FIG. 13, for example, n ⁺ InP having a low electric field intensity is used.
Since the light absorption in the light absorbing layer 35 near the buffer layer 33 increases, when the light input to the element is large, n ⁺
Since the electric field in the light absorbing layer 35 near the InP buffer layer 33 is modulated, the carrier traveling speed decreases (the so-called space charge effect occurs. This is described in, for example, the document "Optical Communication Device Engineering", Engineering Books (1986)). , P.374). As a result, the response time of the light receiving element increases, so that the cutoff frequency decreases.

The present application has been made in view of such a point, and accordingly, an object of the first invention of the present application is a semiconductor light-receiving element manufactured by using a semi-insulating InP substrate and having a high response speed. An object of the present invention is to provide a semiconductor light receiving element having a structure which can be improved and in which disconnection of a wiring electrode hardly occurs. Another object of the present invention is to provide a method for easily manufacturing the light receiving element of the first invention.

Another object of the third invention of this application is a semiconductor photodetector manufactured using a semi-insulating InP substrate, which can reduce dark current and prevent a cutoff frequency from being lowered by a space charge effect. An object of the present invention is to provide a semiconductor light receiving element having a structure (that is, an improvement in response speed).

[0013]

In order to achieve this object, according to the semiconductor light receiving device of the first invention, a semi-insulating I.D.
An n-type InP layer, an InGaAs light absorbing layer, and an n ⁻ -type InP layer having a p-type diffusion region in part are provided in this order on an nP substrate, and a p-side is formed on a predetermined portion of the p-type diffusion region. An n ^- type InP layer having a p-side wiring electrode on a predetermined region of the n ^- type InP layer separated from the p-type diffusion region via an insulating film; ^- -type In
The P layer portion and the n-type InP semiconductor layer portion are replaced with the remaining n ⁻ type I
To electrically separate from nP layer portion and the n-type InP layer portion, n of the above ^- described above -type InP semiconductor layer surface In
An isolation structure using a groove having a depth reaching the P substrate is provided, and the above-mentioned p-side wiring electrode and the above-mentioned p-side electrode are connected by a space wiring which runs over the above-mentioned groove.

In implementing the first invention, the above-mentioned separating structure is constituted by any one of the following (a) to (c), and the above-mentioned separating structure is the following (b): Alternatively, in the case of (c), the n ⁻ -type InP layer portion in a region surrounded by the groove provided around the p-type diffusion region and an n-side wiring electrode separately provided outside the region are formed on the groove. It is preferable that the connection be made by a space wiring extending through the space.

(A). A groove surrounding the p-side wiring electrode formation region and having a depth from the surface of the n ⁻ -type InP layer to the above-described InP substrate (hereinafter, abbreviated as “p-side wiring electrode portion separating groove”). There is also.).

(B). A groove surrounding the above-described p-type diffusion region (however, a groove surrounding a part of each of the above-described n-type and n ⁻ -type InP layers) and has a depth from the surface of the above-mentioned n ⁻ -type InP layer to the above-mentioned InP substrate. (Hereinafter, may be abbreviated as “light receiving portion separating groove”) and the n under the n-side wiring electrode provided in a predetermined portion of the region outside the region surrounded by the light receiving portion separating groove. The side wiring electrode is made of the above-mentioned n ^- InP.
An insulating film provided to insulate from layers.

(C). A groove for individually taking in the p-side wiring electrode formation region and the p-type diffusion region, and having a depth from the surface of the n ⁻ -type semiconductor layer to the above-described InP substrate (hereinafter referred to as a “separating portion The groove surrounding the p-type diffusion region is provided around the p-type diffusion region so that the surrounding region also includes a part of each of the n-type and n ⁻ -type InP layers.) .

Further, in implementing the first invention, p
The width of each of the side wiring electrode part separating groove, the light receiving part separating groove, and each part separating groove is preferably 10 μm or less, and more preferably about 2 to 3 μm.

Furthermore, implementing this first invention, when n-type InP layer the aforementioned n ⁺ -type InP layer, the n ⁺
N -type InP layer between the above-described InGaAs light absorbing layer ^-
It is preferable to provide a type InP layer.

According to the method of manufacturing a semiconductor light receiving element of the second invention, when manufacturing the semiconductor light receiving element of the first invention, the formation of the space wiring is performed by forming the groove and then forming a positive type in the groove. A step of filling with a resist, a step of forming a common thin film for forming a corresponding wiring electrode and a space wiring on the upper side of the sample in which the groove is filled with the positive type resist, and simultaneously or after patterning the thin film, And removing the mold resist.

According to the third aspect of the present invention, an n ⁺ -type InP layer, an InGaAs light absorbing layer, and an n ⁻ -type InP layer partially having a p-type diffusion region are formed on a semi-insulating InP substrate. In this order, the n ⁺ -type In
An n ⁻ -type InP layer is provided between the P layer and the InGaAs light absorbing layer.

[0022]

According to the first aspect of the present invention, the following operation can be obtained.

In the semiconductor light receiving device of the first invention, the n-type I
A p-type diffusion region is formed in a predetermined portion of a stacked body of an nP layer, an InGaAs light absorbing layer, and an n ⁻ -type InP layer, and a p-side wiring electrode is provided on another predetermined portion via an insulating film. Therefore, the n ⁻ type semiconductor layer below the p-side wiring electrode and n
When the type semiconductor layer portion is connected to the n-side electrode, a capacitance is generated under the p-side wiring electrode, and the capacitance of the entire light receiving element increases accordingly. However, in the semiconductor light receiving element of the first invention, each of the n ^- and n-type InP layers under the p-side wiring electrode is separated by a separation structure using a groove extending from the surface of the n ^-- type InP layer to the semi-insulating InP substrate. Remaining n ^- and n-type InP
Since it is separated from the layer portion, it is possible to prevent a capacitance from being generated below the p-side wiring electrode. This separation structure, for example,
(A) Separation structure by groove for separating p-side wiring electrode part, (b)
This is realized by a structure including the light receiving portion separating groove and the insulating film below the n-side wiring electrode, or (c) a structure including each portion separating groove. In addition, since the separation structure using the grooves is employed, the surface of the light receiving portion and the surface of each wiring electrode formation region have the same height from the substrate surface.

In addition, even if the separation structure using the groove is employed, in the first aspect of the present invention, the space between the electrodes (between the p-side wiring electrode and the p-side electrode, the n-side wiring The electrical connection between the electrode and the n-side electrode) is made not by a wire passing through the groove but by a space wire (air bridge interconnect). Therefore, disconnection in the wiring is less likely to occur than in the case of performing wiring in the trench.

In the structure of the first invention, the n-type In
When the P layer is an n ⁺ -type InP layer, the n ⁺ -type InP layer and I ⁺
In the configuration in which the n ⁻ -type InP layer is provided between the n ^- type light absorbing layer and the n -type light absorbing layer, the depletion layer spreads to a part of the n ⁻ -type InP semiconductor layer by applying a high reverse bias voltage to the element. Of the maximum electric field intensity does not change. Further, the light absorbing layer and the n ⁺ -type InP layers the depletion layer when using the device as a back-illuminated n ^- it is possible to widen up type InP layer The n ^- type InP layer InGaAs light absorbing layer portion in the vicinity The electric field strength can be made higher than when the n ⁻ -type InP layer is not provided.

In the structure of the second aspect of the present invention, the inside of the groove is filled with a positive resist to form a space wiring. In order to obtain a space wiring over the groove, it is necessary to first selectively and satisfactorily fill the inside of the groove, but this groove is not easy because the aspect ratio is relatively high. However, if a positive resist is used, the resist can be easily left in the groove only by selectively exposing the resist portion outside the groove. When the resist in the groove is removed simultaneously with or after the patterning of the wiring, a spatial wiring is obtained. In addition, the groove portion can be almost flattened by a positive resist, and a thin film for wiring formation can be formed thereon and patterned, so that known film forming technology, photolithography technology, etching technology, lift-off technology, electroplating technology, etc. By appropriately combining these, desired wiring electrodes and spatial wiring can be obtained.

Further, according to the semiconductor light receiving element of the third invention, n ^{− is provided} between the n ⁺ -type InP layer and the InGaAs light absorbing layer.
Since the n ^- type InP layer is provided, even if the depletion layer spreads to a part of the n ⁻ -type InP layer by applying a high reverse bias voltage to the element, the increasing rate of the depletion layer width does not change. The rate of increase does not change. When the device is used as a back-illuminated type, the light absorption layer and n ⁺
It is possible to widen the depletion layer to type InP layer The n ^{- -} n type Inp interlayer field strength of the InGaAs optical absorption layer portion of the mold InP layer near n ^- can be increased than the case without the type InP layer.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of each invention of the present application will be described below with reference to the drawings. However, the drawings used in the description merely show the dimensions, shapes, and arrangements of the components so that the present invention can be understood. In each of the drawings, the same components are denoted by the same reference numerals, and detailed description thereof may be omitted.

1. Description of Semiconductor Photodetector of First Invention First, each embodiment of the first invention will be described. In these examples, the n-type InP layer provided on the semi-insulating compound semiconductor substrate is referred to as an n-type InP buffer layer,
An n ⁻ -type InP layer having a p-type diffusion region in part is
It is called P window layer.

1-1. First Embodiment FIG. 1 is a perspective view showing a planar photodiode as a semiconductor light receiving element according to a first embodiment of the first invention, cut away along a substantially center line thereof (a perspective view of one part divided into two parts).
It is. In this perspective view, the region denoted by the symbol I corresponds to the main portion of the light receiving element constituted by the light receiving portion and the wiring electrode, and the region denoted by the symbol II corresponds to the peripheral portion.

The semiconductor light receiving device of the first embodiment has an n-type InP buffer layer 63 on a semi-insulating InP substrate 61.
An n ⁻ -type InGaAs light absorbing layer 65 and an n ⁻ -type InP window layer 67 are provided in this order. Also, this n ^- type I
In the region where the light receiving portion is to be formed in the nP window layer 67, the lower end reaches the boundary between the window layer 67 and the light absorbing layer 65, and the plane shape is substantially circular (FIG. A semi-circular) p-type (p ⁺ -type in this case) diffusion region 69 is provided. Further, a p-side electrode 71 is provided on a predetermined portion of the p ⁺ -type diffusion region 69 (in this embodiment, on a ring-shaped portion along the edge of the p-type diffusion region). In addition, n ^-
An insulating film 73 is provided in one of two predetermined regions of the type InP window layer 67 remote from the p ⁺ type diffusion region 69.
A p-side wiring electrode 75 is provided via a and 73b, and an n-side wiring electrode 77 is provided in the other region via insulating films 73a and 73b. Since the insulating film 73b also serves as an anti-reflection film in the p ⁺ diffusion region 69, it is made of a material suitable therefor, for example, a Si ₃ N ₄ film or a SiO ₂ film. Also,
The insulating film 73b can be made of a suitable material such as a Si ₃ N ₄ film, a SiO ₂ film, or a heat-resistant polyimide.

Further, in the semiconductor light receiving element of the first embodiment, the formation region of the p-side wiring electrode 75 and the p-type diffusion region 69
These are trenches for taking these individually around, and are n ^- type InP
A groove (separation groove) 79 having a depth from the surface of the window layer 67 to the InP substrate 61 is provided. However, a groove part (light receiving part separating groove) surrounding the p-type diffusion region 69 of each part separating groove 79 is provided with an n ⁻ -type InP window layer 67, a light absorbing layer 65, and an n-type InP buffer in the surrounding area. The arrangement is provided so as to include a part of each of the layers 63. Also, the n ⁻ -type InP window layer 67 in the surrounding region
An n-side electrode 81 is provided on a part of the part. And
In the semiconductor light receiving element of the first embodiment, the p-side wiring electrode 7
5 and the p-side electrode 71 are connected by a p-side space wiring 83 crossing the groove 79, and the n-side wiring electrode 77 and the n-side electrode 81 are connected to the n-side space crossing the groove 79. Wiring 85
Connected by The width of each part separating groove 79 is preferably 10 μm or less, and more preferably, 2 to 3 μm.

[0033] In the light receiving element of the first embodiment, n under the p-side interconnect electrode formation region ^- and n-type semiconductor layer portion because it is electrically isolated from other portions by a groove 79, the p-side interconnection electrodes formed It is possible to prevent generation of capacitance below the region. Furthermore, n
Since the side wiring electrode formation region is also defined as the minimum required flat area by the groove 79, the space between the p-side wiring electrode 75 and the n-side wiring electrode 77 and the header when the light-receiving element is mounted on the header. The capacitance can be reduced as compared with the case where the capacitance is not set.

Although FIG. 1 shows an example in which a groove is also provided in the region II, this groove is not essential, and the structure of the region II can be changed according to the design. Further, for example, in the case where the structure is such that the position along the line PP in FIG. 1 is one end of the semiconductor light receiving element, each of the n-type semiconductor layer portions below the p-side wiring electrode 75 In this structure, the p-side wiring electrode 75 is considered to be surrounded by a groove (p ⁺ The same applies to the diffusion region 69.)

1-2. Second Embodiment FIG. 2 is a cutaway perspective view showing a semiconductor light receiving element according to a second embodiment of the first invention as in FIG.

The difference between the light receiving element of the second embodiment and that of the first embodiment lies in the separation structure. In the second embodiment,
A groove surrounding this region around p ⁺ diffusion region 69 (provided that n-type InP buffer layer 63, light absorption layer 65 and n ⁻
A groove also surrounding a part of each of the InP window layers 67. )
In addition, a groove 91 (light receiving portion separating groove) having a depth from the surface of the window layer 67 to the InP substrate 61 is provided. An isolation structure is formed by the groove 91 and insulating films 73a and 73b provided below the n-side wiring electrode 77 provided in a predetermined portion of a region outside the region surrounded by the groove 91.

1-3. Third Embodiment FIG. 3 is a cutaway perspective view showing a semiconductor light receiving element according to a third embodiment of the first invention as in FIG.

The difference between the light receiving element of the third embodiment and that of the first embodiment lies in the separation structure. In the third embodiment,
A groove 93 (p-side electrode wiring separation groove) surrounding the p-side wiring electrode 75 formation region is provided around the formation region, and the groove 93 forms a separation structure. However, this groove 93 is n-type I
The nP buffer layer 63, the light absorption layer 65, and a part of each of the n ⁻ -type InP window layers 67 are also provided so as to surround a part thereof.

1-4. Fourth Embodiment The first invention can also be applied to a semiconductor light receiving element called a balanced twin photodiode in which two light receiving sections are connected. Hereinafter, the example will be described. FIG. 4 (A)
And (B) is a diagram provided for explanation thereof. Particularly, (A) is a perspective view of the light receiving element, and (B) is QQ of (A).
FIG. 3 is a cross-sectional view of the element at a position corresponding to a line.

In the twin photodiode of this embodiment,
As shown in FIGS. 4A and 4B, a laminate 95 including a buffer layer 63, a light absorbing layer 65, and a window layer 67.
A first light receiving portion forming region 96, a first light receiving portion p-side wiring electrode forming region 96 a, a second light receiving portion forming region 97,
An n-side wiring electrode formation region 97a for the second light receiving portion, a connection region 98a for connecting the n-side electrode of the first light receiving portion and the p-side electrode of the second light receiving portion, and a connection region 98a for the connection region 98a Are formed by dividing the wiring electrode forming regions 98b by grooves 99 having a depth from the surface of the window layer 67 to the substrate 61. Then, predetermined electrodes in adjacent areas are connected to each other by a spatial wiring 100 extending over the groove 99.

In the balanced twin photodiode of this embodiment, the region 9 is used for the same reason as in the first embodiment.
6, 96a, 98a, 98b, 97 can be prevented from generating a capacitance under each of them, and the capacitance when mounted on the header can be reduced.

2. Description of Second Invention (Manufacturing Method Invention) Next, an embodiment of the second invention will be described using an example of manufacturing the semiconductor light receiving element of the first embodiment described with reference to FIG. FIGS. 5 to 7 are process diagrams provided for the description, and are process diagrams showing a state of a sample in a main process by a cutaway perspective view at a position similar to FIG.

First, an n-type InP buffer layer 63 is formed on a semi-insulating InP substrate 61 by a suitable crystal growth method such as a metalorganic vapor phase epitaxy method, a halide vapor phase epitaxy method, or a liquid phase epitaxy method. n ⁻ -type InGaAs light absorbing layer 65 and n ⁻
A type InP window layer 67 is sequentially grown. Next, ap ⁺ -type impurity such as Zn or Cd is selectively diffused into ap ⁺ -type diffusion region formation region of the n ⁻ -type InP window layer 67 to form a p ⁺ -type diffusion region 69 (FIG. 5A). . The selective diffusion is performed under such conditions that the lower end of the diffusion region reaches the boundary between the window layer 67 and the light absorbing layer 65.

Next, on the n ^- type InP window layer 67,
A mask 101 is formed by a known photo-etching method so as to cover a region other than a region where a part isolation groove (see FIG. 1) is to be formed (FIG. 5B). As a constituent material of the mask 101, for example, a photoresist, a SiO ₂ film, and a Si ₃ N ₄ film can be used.

Next, the portion of the sample not covered with the mask 101 is removed by a known etching means up to the substrate 61 to form a groove 79 for separating each part (FIG. 5).
(C)).

Next, Si was added to the sample by a known method.
_A 3N ₄ film, a SiO ₂ film, a polyimide film, or the like is formed to form an insulating film 73a. Then, the p ⁺
A portion corresponding to the mold diffusion region 69 and a portion corresponding to the region where the n-side electrode (see FIG. 1) is to be formed are respectively removed by a photoetching technique to form an opening 73x (FIG. 6A).

Next, a Si film is formed on this sample by a known method.
₃ N ₄ film, SiO ₂ film or the like having an insulating property and an insulating film 73b to form a thin film that can be used as an antireflection film of the light-receiving portion
(FIG. 6B).

Next, a portion of the insulating film 73b corresponding to the region where the n-side electrode (see FIG. 1) is to be formed and a portion corresponding to the edge of the p ⁺ -type diffusion region (that is, the portion corresponding to the region where the p-side electrode is to be formed) Are respectively removed. Then, the p-side electrode 71 is also added to the p ⁺ type diffusion region 69 by a known method.
An n-side electrode 81 is formed on each of the n ⁻ -type InP window layers 67 (FIG. 6C).

Next, a positive photoresist as a photoresist is formed on the entire surface of the sample (not shown). At this time, this operation is performed so that the positive photoresist is embedded in the groove 79. Next, the groove 7 of the positive photoresist is used.
The portions other than 9 are exposed, and then this resist is developed. Thereby, the positive photoresist 103 is formed in the groove 79.
Is selectively embedded, and the groove 79 portion of the sample is flattened (FIG. 7A). In this embodiment, a polymethylisopolopecoketone-based positive photoresist is used as the positive photoresist.

Next, a p-side wiring electrode, a space wiring for connecting the p-side electrode 71 and the n-side wiring electrode, and a space wiring for connecting the n-side electrode 81 to the n-side electrode 81 of this sample were prepared. A resist pattern 105 made of a second photoresist that does not dissolve the above-described positive photoresist 103 is formed on portions other than the respective regions to be formed (FIG. 7).
(B)). In this embodiment, a phenol-novolak resin-based positive photoresist is used as the second photoresist.

Next, a suitable metal thin film 107 for forming each wiring electrode and each space wiring is formed on the entire surface of the sample having the resist pattern 105 (FIG. 7C).

Next, by dissolving the resist pattern 105 with a suitable solvent, the portion of the metal thin film 107 on the resist pattern 105 is removed (lift-off).
Thus, the p-side wiring electrode 75 and the n-side wiring electrode 77 can be formed. If the solvent at the time of this lift-off is acetone or dimethylformamide, the positive photoresist 103 filling the groove 79 can be simultaneously dissolved in this step. However, since the area of the metal thin film 107 is larger than the amount of the resist in the groove, the metal thin film on the groove 79 remains. Therefore, the space wiring 83 for the p-side and the space wiring 85 for the n-side are formed on the groove 79, respectively. FIG. 1
The semiconductor light receiving device according to the first embodiment of the first invention shown in FIG.

In the above description, the wiring electrodes 75 and 77 and the space wirings 83 and 85 are formed by the lift-off method. However, these may be formed by other methods. Hereinafter, two examples of a method using a photoetching method and a method using an electroplating technique will be described.

FIGS. 8A to 8C show each wiring electrode 75,
It is a principal part process drawing showing the example which forms 77 and each space wiring 83 and 85 by a photoetching method.

In this method, first, FIGS. 5, 6 and 7
According to the procedure described with reference to FIG.
5, 67, the p-type diffusion region 69,..., The positive photoresist 103 is buried in the groove 79, and then a metal thin film 107 is formed on the entire surface of the sample (FIG. 8).
(A)). Next, a resist pattern 10 using, for example, the above-described second photoresist is formed in a shape covering the respective regions where the respective wiring electrodes 75 and 77 and the respective spatial wirings 83 and 85 are to be formed.
9 is formed on the metal thin film 107 (FIG. 8).
(B)). Thereafter, a portion of the metal thin film 107 that is not covered with the resist pattern 109 is selectively removed, and the metal wiring 107 is patterned. Next, each of the resist pattern 109 and the positive photoresist 103 in the groove 79 is dissolved simultaneously or separately. Thus, the respective wiring electrodes 75 and 77 and the respective spatial wirings 83 and 85 can be formed (FIG. 8C).

FIGS. 9A to 9C show each of the wiring electrodes 75,
It is a principal part process drawing which showed the example which forms 77 and each space wiring 83, 85 using the electroplating method.

In this method, first, FIGS. 5, 6 and 7
According to the procedure described with reference to FIG.
5, 67, the p-type diffusion region 69,..., The positive photoresist 103 is buried in the groove 79, and a current film 111 for forming a current path for electroplating is formed on the entire surface of the sample. For example, a two-layer film of titanium-gold is formed by a vacuum evaporation method. Next, each wiring electrode 75,
A resist pattern 109 using, for example, the above-described second photoresist is formed on the current film 111 so as to cover an area other than the formation area of each of the 77 and the spatial wirings 83 and 85 (FIG. 9A). ). Next, electroplating is performed to selectively cover the portions of the current film 111 that are not covered with the resist pattern 109 with the plating material 11.
5 is formed (FIG. 9B). Next, the resist pattern 109 is removed. Next, the current film portion exposed by this removal is etched. It is preferable to select a plating material so that the etching can be performed using the plating material as a mask. Next, by dissolving the positive photoresist 103 in the groove 79, each of the wiring electrodes 75 and 77 is dissolved.
In addition, the respective wiring spaces 83, 85 can be formed with the respective space wirings 83, 85.

3. Description of the semiconductor light receiving element of the third invention Next, an embodiment of the semiconductor light receiving element of the third invention will be described with reference to an example in which the third invention is applied to the light receiving element described with reference to FIG. FIG. 10 is a cross-sectional view of the element used for the description.

The light receiving element according to the third embodiment of the present invention is obtained by forming an n ⁺ -InP first buffer layer 123 on a semi-insulating InP substrate 121 as an n ^- type semiconductor layer made of a material different from the light absorbing layer. n ⁻ type InP second buffer layer 125, n ⁻
-InGaAs light-absorbing layer 127 and the ⁿ - -InP comprising a window layer 129 in this order, further the ⁿ - lower end to -InP window layer 129 reaches the boundary of the window layer 129 and the light absorbing layer 127 p ⁺ -type diffusion region 131 It has. These first buffer layer 123 and second buffer layer 12
5. The light absorbing layer 127 and the window layer 129 are formed as a mesa-shaped structure portion 133 (hereinafter, “mesa portion 133”). However, the plane area of the first buffer layer 123 is larger than the plane area of each of the second buffer layer 125, the light absorbing layer 127, and the window layer 129. Also, this mesa unit 133
Is covered with an insulating film 135 made of, for example, a SiO ₂ film or a Si ₃ N ₄ film. However, the p-type diffusion region 131
On a predetermined portion, a part of the insulating film 135 is removed, and a p-side electrode 137 is provided there. The p-side electrode 137 is provided with a p-side wiring electrode 137a extending from above the mesa 133 to the surface of the substrate 121. Also, n ⁺ −
Also on a predetermined portion of the InP first buffer layer 123, a part of the insulating film 135 is removed, and an n-side electrode 139 is provided there. The substrate 121 is connected to the n-side electrode 139.
An n-side wiring electrode 139a reaching the surface is provided.

In the device of this embodiment, n ^- InG
The aAs light absorbing layer 127 is thinner than usual, for example, 1 to 2 μm. This is because the response time is reduced by limiting the carrier traveling time. The series resistance of the device is reduced by setting the carrier concentration of the n ⁺ -InP first buffer layer 123 to 10 ¹⁷ cm ^-3 or more. This is because the response time is reduced by limiting the circuit constant. Also,
The n ⁻ -type InP second buffer layer 125 has a carrier concentration of about 10 ¹⁵ to 10 ¹⁶ cm ⁻³ and a layer thickness of 0.3 to 0.8.
It is about μm.

In this device, a sharp increase in dark current in a region where the reverse bias voltage is high can be prevented. Further, when this element is changed to a back reflection type configuration (a configuration having a second buffer layer corresponding to FIG. 13), the space charge effect can be prevented even when the light input is large, and the cutoff frequency is reduced. Can be prevented.

The third invention can of course be applied to other light receiving elements such as the light receiving element of the first invention and the light receiving element described with reference to FIG. In addition, the present invention can be applied to the case where the light receiving portion is not mesa-shaped.

[0063]

Effects of the Invention] According to the semiconductor light receiving device of the first invention, as is apparent from the above description, n ^- -type p-side wiring electrode under the isolation structure from the InP layer surface with grooves extending in the semi-insulating InP substrate Since the n ^- and n-type InP layer portions are separated from the remaining n ^- and n-type InP layer portions, it is possible to prevent the occurrence of capacitance under the p-side wiring electrode. In addition, even if the separation structure using the grooves as described above is adopted, in the first aspect of the present invention, between the electrodes (between the p-side wiring electrode and the p-side electrode or between the n-side wiring electrode and n The electrical connection with the side electrode is made not by a wire passing through the groove but by a space wire. Therefore, disconnection in the wiring is less likely to occur than in the case of performing wiring in the trench. Therefore, it is possible to provide a semiconductor light receiving element having a structure in which the response speed can be improved and the disconnection of the wiring electrode hardly occurs.

Further, according to the manufacturing method of the second invention, the semiconductor light receiving element of the first invention can be easily manufactured.

Further, according to the semiconductor light receiving device of the third invention, n ^{− is provided} between the n ⁺ type InP layer and the InGaAs light absorbing layer.
Since the n ^- type InP layer is provided, even if the depletion layer spreads to a part of the n ⁻ -type InP layer by applying a high reverse bias voltage to the element, the increasing rate of the depletion layer width does not change. The rate of increase does not change. For this reason,
It is possible to prevent a sharp increase in dark current at such a reverse bias voltage. Also, when the device is used as a back illuminated type, n ⁻ between the InGaAs light absorbing layer and the n ⁺ -type InP layer.
Since the depletion layer can be extended to the InP layer,
^- the electric field intensity of the light absorbing layer part of the mold InP layer near the n ^- -type I
It can be made larger than when no nP layer is provided. Therefore, the space charge effect can be prevented, and the cutoff frequency can be prevented from decreasing.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a light receiving element according to a first embodiment of the first invention with a part cut away.

FIG. 2 is a perspective view showing a light receiving element according to a second embodiment of the first invention with a part cut away.

FIG. 3 is a perspective view showing a light receiving element according to a third embodiment of the first invention with a part cut away.

FIG. 4 is a perspective view of a light receiving element according to a fourth embodiment of the first invention.

FIGS. 5A to 5C are process diagrams of the first embodiment of the second invention.

6 (A) to 6 (C) show FIG. 5 of the first embodiment of the second invention.
FIG.

FIGS. 7A to 7C are diagrams of the first embodiment of the second invention, FIG.
FIG.

FIGS. 8A to 8C are main part process charts of a second embodiment of the second invention.

FIGS. 9A to 9C are main part process diagrams of a third embodiment of the second invention.

FIG. 10 is a diagram provided for explanation of an embodiment of the third invention.

FIG. 11 is an explanatory diagram of a conventional technique.

FIG. 12 is an explanatory diagram of another conventional technique.

FIG. 13 is a diagram provided for explanation of another conventional technique.

[Explanation of symbols]

61: semi-insulating InP substrate 63: n-type InP buffer layer 65: n ⁻ -type InGaAs light absorbing layer 67: n ⁻ -type InP window layer 69: p ⁺ -type diffusion region 71: p-side electrode 73a: insulating film 73b: insulating Film (also serving as antireflection film) 75: p-side wiring electrode 77: n-side wiring electrode 79: groove for separating each part 81: n-side electrode 83: p-side spatial wiring 85: n-side spatial wiring 91: light receiving Part separation groove 93: P-side wiring region separation groove 101: Mask 103: Positive resist (first photoresist) 105: Resist pattern of second photoresist 107: Metal thin film 109: Resist pattern 111: Current film 113: resist pattern 115: plating material 121: a semi-insulating InP substrate 123: n ⁺ -type InP first buffer layer 125: n ^- -type InP second buffer Layer 127: n ^- -type InGaAs light-absorbing layer 129: n ^- -type InP window layer 131: p ⁺ -type diffusion region 133: mesa 135: insulating film 137: p-side electrode 137a: p-side wiring electrode 139: n-side electrode 139a : N-side wiring electrode

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-5-304282 (JP, A) JP-A-5-63098 (JP, A) JP-A-63-37639 (JP, A) JP-A-60-1985 37149 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 31/10-31/119 H01L 27/14-27/148

Claims (4)

(57) [Claims] 1. An n-type InP on a semi-insulating InP substrate.
Comprising comprising a type InP layer in this order, the p-side electrode on a predetermined portion of the p-type diffusion region, said n ^{- -} the layer, and the InGaAs light-absorbing layer, part n with p-type diffusion region type InP A p-side wiring electrode provided on a predetermined region of the layer separated from the p-type diffusion region via an insulating film, wherein the n ⁻ -type InP layer portion and the n-type InP semiconductor layer portion below the p-side wiring electrode formation region And a separation structure using a groove having a depth from the surface of the n ⁻ -type InP semiconductor layer to the InP substrate to electrically separate the n ⁻ -type InP layer portion and the n-type InP layer portion from each other. A semiconductor light-receiving element, wherein a p-side wiring electrode and the p-side electrode are connected by a space wiring extending over the groove. 2. The semiconductor light receiving device according to claim 1, wherein the separation structure is formed of one of the following (a) to (c), and the separation structure is as follows: In the case of (b) or (c), an n ⁻ -type InP layer portion in a region surrounded by the trench provided around the p-type diffusion region and an n-side wiring electrode separately provided outside the region are formed. A semiconductor light receiving element connected by a space wiring extending over the groove. (A). A groove surrounding the p-side wiring electrode formation region and having a depth from the surface of the n ⁻ -type InP layer to the InP substrate. (B). A groove surrounding the p-type diffusion region (however, a groove surrounding a part of each of the n-type and n ⁻ -type InP layers).
A groove having a depth from the surface of the n ⁻ -type InP layer to the InP substrate, and an n-side wiring electrode provided below an n-side wiring electrode provided in a predetermined portion outside a region surrounded by the groove. An insulating film provided for insulation from the n ⁻ -type InP layer; (C). A groove for individually taking in the p-side wiring electrode formation region and the p-type diffusion region, and having a depth from the surface of the n ⁻ -type InP layer to the InP substrate (the groove surrounding the p-type diffusion region is A trench in the surrounding region that also includes a portion of each of the n-type and n ⁻ -type InP layers.) 3. The semiconductor light-receiving device according to claim 1, wherein when the n-type InP semiconductor layer is an n ⁺ -type InP layer, n is provided between the n ⁺ -type InP layer and the InGaAs light absorption layer.
^- semiconductor light receiving element characterized in that comprises a type InP layer. 4. When manufacturing the semiconductor light receiving element according to claim 1, the formation of the space wiring includes a step of filling the inside of the groove with a positive resist after the formation of the groove, and a step of filling the groove with the positive resist. Forming a common thin film for forming the corresponding wiring electrode and spatial wiring on the upper side of the sample filled with the above, and a step of removing the positive resist simultaneously with or after patterning the thin film. A method for manufacturing a semiconductor light receiving element, comprising: