JP3133524B2 - Vertical PNP transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an improvement in a vertical PNP transistor.

[0002]

2. Description of the Related Art FIGS. 3 and 4 show a vertical PNP transistor.
It is the sectional view and top view shown. In the figure, (1) is P
Semiconductor substrate, (2) N-type epitaxial layer, (3)
Is N⁺Mold buried layer, (4) is P⁺Mold buried layer, (5)
Is P⁺Mold separation area, (6) is P ⁺Type collector derivation area,
(7) is a P-type emitter region, and (8) is an N-type emitter region.⁺Mold base control
It is a tact area. Epitaxy surrounded by isolation area (5)
The char layer (2) is an island region, and P⁺Type filling
Layer (4) and P⁺Surrounded by mold collector lead-out area (6)
The part thus set is a base region (9). Base area (9)
The other island regions are generally called non-epi regions (10).
Is an electrically isolated area, but V _CCPotential
It is common to apply.

[0003]

[SUMMARY OF THE INVENTION However, from the circuit, the process requirements, or V _CC electrode chip size specific that no pulling turning space requirements, can not be applied to V _CC potential outside epitaxial region (10) There are special uses. In such an example, the outer epi region (10) is in a floating state instead of applying the V _CC potential. When the outer epi region (10) is floating, there is a disadvantage that the parasitic transistor (11) is turned on by a leak current on the surface of the epitaxial layer (2) and the signal waveform is distorted.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and has a collector leading region (25).
Forming an N ⁺ -type contact region (30) extending over both the N ⁺ -type contact region (30) and the N ⁺ -type contact region (30). It is an object of the present invention to provide a vertical PNP transistor in which application of a collector potential to the region (29) makes application of V _CC unnecessary and prevents a parasitic effect.

[0005]

According to the present invention, since the base-emitter of the parasitic transistor is short-circuited by short-circuiting the collector lead-out region (25) and the outer epi region (29), the parasitic transistor is prevented from turning on.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described in detail. 1 and 2 show the vertical PN of the present invention, respectively.
3A and 3B are a cross-sectional view and a plan view showing a P transistor. these
In the figure, (20) indicates a P-type silicon single crystal semiconductor substrate.
Plate, (21) epitaxy on semiconductor substrate (20)
N-type epitaxial layer formed by the
2) N is formed so as to be embedded in the surface of the substrate (20).
⁺Mold embedded layer, (23) is N⁺Mold buried layer (22)
Formed so as to be superimposed on and embedded in⁺Embedding types
Layer, (24) is N⁺Around the mold buried layer (22)
P which penetrates through the axial layer (21) to form an island region⁺Type
(25) is the surface of the epitaxial layer (21)
To P⁺It was connected to the mold buried layer (23) and formed in an annular shape.
P⁺Type collector derived area, (26) is collector derived area
On the surface of the epitaxial layer (21) surrounded by (25)
The formed P-type emitter region, (27) is N ⁺Mold bay
The contact area.

In the island region surrounded by the isolation region (24), a region completely surrounded by the P ⁺ type buried layer (23) and the P ⁺ type collector lead-out region (25) is a base region (28).
And a vertical PNP transistor using the P ⁺ type buried layer (23) as a collector. A region of the island region other than the base region (28), that is, an annular region outside the collector lead-out region (25) and inside the isolation region (24) is called an outer epi region (29). Collector lead-out area (25)
An N ⁺ -type contact region (30) is provided on a surface extending over both the first region and the outer epi region (29), and the contact region (30) overlaps over substantially the entire circumference of the collector lead-out region (25). Then, a concave portion is formed at a portion of the collector electrode which is to be contacted (see FIG. 2).

In FIG. 2, (31), (32), (33)
Indicates contact holes for an emitter electrode, a base electrode, and a collector electrode, respectively. A contact hole (33) of the collector electrode is formed in the concave portion of the contact region (30) so as to extend over both the collector lead-out region (25) and the contact region (30), and the collector electrode makes ohmic contact with both of them (FIG. Not shown). Therefore, the collector lead-out region (25) and the contact region (30) are short-circuited by the collector electrode, and the outer epi region (29) is brought to the collector potential via the contact region (30). Therefore, the base-emitter of the parasitic PNP transistor formed by the collector leading region (25), the outer epi region (29), and the isolation region (24) is short-circuited, and the EB junction exceeds 0.7V. Therefore, the ON operation of the parasitic PNP transistor can be prevented.

The P-type emitter region (26) is an NPN transistor.
In the base diffusion process of the transistor, N ⁺Mold contact area
(30) is obtained by an emitter diffusion process of an NPN transistor.
Is formed. The emitter diffusion is in the collector outlet region (2
5) Since the diffusion depth is sufficiently shallower than that of the contact region (3)
0) does not increase the island size.
No. Also, the pattern shape of the contact region (30) is
It is not limited to the above embodiment, but
The region (25) and the outer epi region (29) can be shorted by an electrode
Any shape is acceptable.

[0010]

As described above, according to the present invention, the ON operation of the parasitic transistor is prevented by short-circuiting the collector lead-out region (25) and the outer epi region (29) with the electrode. This has the advantage that the _Vcc wiring for this can be omitted and the chip size does not need to be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a vertical PNP transistor of the present invention.

FIG. 2 is a plan view showing a vertical PNP transistor of the present invention.

FIG. 3 is a cross-sectional view illustrating a conventional vertical PNP transistor.

FIG. 4 is a plan view showing a conventional vertical PNP transistor.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-47434 (JP, A) JP-A-54-16190 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 29/73

Claims (1)

(57) [Claims] 1. A reverse conductivity type epitaxial layer formed on a semiconductor substrate of one conductivity type, a reverse conductivity type buried layer buried in a surface of the substrate, and overlapping the reverse conductivity type buried layer. A buried layer of one conductivity type buried as described above, an isolation region separating the epitaxial layer into island regions so as to surround the buried layer of the one conductivity type and the opposite conductivity type, and connected to the buried layer of one conductivity type. A collector-derived region of one conductivity type forming a base region, a emitter region of one conductivity type formed on the surface of the base region, and both the collector-derived region and the island region other than the base. A formed reverse conductivity type contact region, and a boundary between the collector lead-out region and the contact region
Is formed in an uneven shape, and is arranged so as to straddle the boundary portion of the uneven shape.
And a collector electrode that makes ohmic contact with both the collector lead-out region and the contact region through the contact hole to bring an island region other than the base to a collector potential. PNP transistor.