JP3134364B2 - Information processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to an information processing system having a central processing unit including a write buffer having a function of changing the order of write data according to an address.

[0002]

2. Description of the Related Art FIG. 4 shows a device configuration in a conventional information processing system. Reference numeral 2 denotes a write buffer for holding a plurality of write addresses and write data in the central processing unit 1, reference numerals 4 and 5 denote address / data buses corresponding to even / odd write addresses, and reference numeral 6 denotes two banks corresponding to even / odd write addresses. It is a main storage device having 7,8. In this configuration, the write command issued in the central processing unit 1 is sent to the write buffer 2 as it is, and the write buffer 2 sends it to the main storage device 6 in the order in which it was received in accordance with the evenness of the address.

[0003]

In the conventional system described above, the address / data bus and the main memory are divided into those for even addresses and those for odd addresses because the write speed of the main memory is that of a write buffer. It was intended to reduce the occurrence of waiting time because the buffer might become full because it is relatively slow. However, for example, when write requests for even addresses occur consecutively, only one address data bus for even addresses is used at that time, and the address data bus and the main memory are used for even addresses. In addition, the meaning of the division for the odd addresses is lost, and the waiting time increases.

[0004]

SUMMARY OF THE INVENTION An information processing system according to the present invention comprises: a write buffer for sequentially holding a plurality of write addresses and write data during a write operation and transmitting the held write address and write data; A current address register that holds the even or odd address of the data, and a virtual write buffer obtained by adding the current address register to the beginning of the write buffer by one stage are stored in the virtual write buffer.
It monitors whether there are consecutive even or odd addresses in the write data that is written, and alternates between even and odd numbers.
Central processing unit and having a write buffer sequence management circuit to switch the order of the write data in the write buffer to be; even address and for said central processing unit via the two address data bus for odd addresses And a main memory of two banks divided by an even number and an odd number of addresses.

[0005]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 and FIG. 2 showing the configuration of an embodiment of the present invention, a write buffer order management circuit 3 is provided in a central processing unit 1 and a current address register 10 is provided at the head of the actual write buffer 2. There is provided a virtual write buffer 9 with one stage added. The current address register 10 holds the even / odd of the address of the data that has recently started writing. The write buffer order management circuit 3 monitors whether the address of the write data in the virtual write buffer is even or odd and not continuous. If there is a continuous row, one of the following operations 1 and 2 is performed.
Here, for simplicity, it is assumed that the continuous columns are even address columns.

Operation 1: Before write data of an odd address is input, that is, a new
If the write buffer 2 becomes full before the data is stored in the buffer, the process waits. When the writing of the current data is completed, the address of the data to be newly written, that is, the address newly held in the current address register 10 becomes the head of the column.

Operation 2: When write data of an odd address comes in , that is, a new write buffer 2
If stored, the data at the odd address is inserted next to the head data at the even address. If the write data of the even address is still continuous (if it is three or more continuous), the write buffer order management circuit 3
Recognizes that the column after this operation is a column of write data of a new even address.

If the continuous column is a write data column having an odd address, the operations of the above operations 1 and 2 are performed in which even and odd numbers are exchanged.

This will be described in detail with reference to FIG. In this example, the write buffer 2 has four stages, and the write data of the even address is represented by 0, and the write data of the odd address is represented by 1. Let us consider a case where three write data of even addresses are successively input to the empty write buffer 2. FIG. 3A shows that the write data of the even address is
State that three consecutively entered, that is, stored
That in the state, since first data is in the process of already writing to even address storage banks 7 of the main memory 6 is performed, the address is held in mosquito rent address register 10. At this time, the write buffer order management circuit 3 starts the current address register 10 of the virtual write buffer 9 and
It is recognized that up to the stage is a column of write data of an even address. Here, it is assumed that write data of an odd address newly enters , that is, the write buffer
2 (FIG. 3B), the above operation 2
, The data of the odd address is inserted next to the head data of the column of the data of the even address, that is, at the 0th stage of the write buffer 2 (FIG. 3 (c)). The third stage is recognized as a new column of even addresses. Since the write data of the odd address is at the head of the write buffer 2, if the address data bus 5 for the odd address is not in use, the odd address storage bank 8 can be immediately accessed. By continuing this operation, the waiting time due to the writing operation can be reduced.

[0011]

As described above, according to the present invention, data of the opposite address is newly stored in the write buffer.
Alternating the data of the data and odd addresses of the even address is inserted in the second column of the write data of the even or odd address continuously this data when the, also the continuous column of data of the even or odd address If the beginning was already in the middle of a write operation ,
That is, the newly stored reverse address is immediately accessible to the address data bus, thereby more effectively using two address data buses and two banks of main memory. The processing capacity of the central processing unit can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a concept of a virtual write buffer in the embodiment.

FIG. 3 is a diagram showing an operation of a virtual write buffer in the embodiment.

FIG. 4 is a configuration diagram of a conventional information processing system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit 2 Write buffer 3 Write buffer order management circuit 4 Address data bus for even addresses 5 Address data bus for odd addresses 6 Main storage device 7 Even address storage bank 8 Odd address storage bank 9 Virtual write buffer 10 Current address register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/30-9/42 G06F 12/00-12/08 G06F 13/16-13/18

Claims (1)

(57) [Claims] 1. A write buffer for sequentially storing a plurality of write addresses and write data during a write operation and sending out the stored write addresses and write data, and a current address register for storing the evenness and oddness of the address of data that has recently started writing. It is regarded as a virtual write buffer obtained by adding the current address register to the head of the write buffer by one stage, and it is monitored whether or not there is an even or odd continuous address of write data stored in the virtual write buffer. Even and odd
A central processing unit having a write buffer order management circuit for changing the order of the write data in the write buffer so that the numbers are alternated ; and the central processing unit via two address / data buses for an even address and an odd address. An information processing system connected to a central processing unit and comprising a main storage device of two banks divided by an even number and an odd number of addresses.