JP3134428B2 - Failure diagnosis method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for diagnosing a fault, and more particularly to a method and an apparatus internally or externally added to a programmable logic controller (hereinafter simply referred to as a PLC) for detecting a fault in a system (including equipment) controlled by the PLC. A method and apparatus suitable for diagnosing.

[0002]

2. Description of the Related Art In order to detect an abnormality in the operation of a system controlled by a PLC at an early stage, an abnormality detection (failure diagnosis) function is included in a PLC program.
Alternatively, it is required to add a failure diagnosis unit to the PLC, and the demand is increasing every day.

To cope with this, the normal operation state of the system controlled by the PLC is observed in advance, and the result is stored. Then, a method has been proposed in which the actual operation of the system is monitored, and this is compared with a normal operating state stored in advance to detect a system abnormality in real time.

As an index indicating a normal operation state, PL
The input and output states of C and the on / off state of the output signal, the order in which the states transition, the time required for the state transition (standard value and allowable width or minimum and maximum values) are considered.

However, if both states of the input signal and the output signal for each operation state are created together as a criterion, an erroneous diagnosis occurs in the following cases.

[0006] For example, it is detected that the rods of three hydraulic (or pneumatic) cylinders have reached their advanced ends.
It is assumed that there are provided limit switches SW1, SW2, and SW3. A condition that all three limit switches SW1 to SW3 are turned on (AN
The program is programmed so that the next operation of the device is started under the (D condition). In such a case, there is no problem if the order in which the three limit switches SW1 to SW3 are turned on is constant. However, if it is not constant due to variations in cylinder operation or other causes, three limit
All order combinations in which the switches SW1 to SW3 are turned on must be monitored. If the operation state of the input signal is limited switch SW1, SW3, SW
If only the state transition of turning on in the order of 2 is registered as a criterion, if these limit switches are turned on in the order of SW3, SW2, and SW1, it is erroneously detected that there is an abnormality.

As described above, the monitoring of the state transition of the input signal of the PLC involves the risk of erroneous diagnosis. Therefore, there is a problem that the state transition of the input signal must be removed from the monitoring target, and only the state transition of the output signal of the PLC must be limited to the monitoring target.

However, actual system failures can be caused by a failure of the input signal of the PLC, such as a failure of an input sensor, a break of a signal line, or a case where a limit switch or the like cannot detect the failure due to insufficient operation of a device. Many are based on abnormalities.

For this reason, when only the state transition of the output signal of the PLC is monitored, when an abnormality occurs, it becomes complicated or difficult to identify the abnormal part where the abnormality has occurred. That is, when an abnormality is detected, it is necessary to perform a task of locating an abnormal portion while sequentially checking the state of the input / output signal at that time and the PLC program list.

In the actual PLC control, as shown in a ladder diagram shown in FIG. 11, the input signal is relayed through a number of auxiliary relays to control the output. Therefore, related descriptions scattered in a program list are stored. We have to go through them one by one.
In FIG. 11, when an abnormality is detected at the output 1, as indicated by an arrow, the auxiliary relays B and A become abnormal (N
G) While specifying that there is (other contacts are normal: OK
), An operation to reach the limit switch SW which is the cause of the failure is required.

For this reason, it takes a long time to repair a failure and to start up the system after an abnormality is detected.

[0012]

SUMMARY OF THE INVENTION The present invention provides a failure diagnosis method and apparatus which can always detect an abnormality correctly without causing an erroneous diagnosis, and can quickly identify an abnormal part when an abnormality is detected.

In the fault diagnosis method according to the present invention, a programmable logic controller having an input / output table for storing states of input / output signals and controlling a system according to a predetermined program is used. The control operation of the system according to the program is normally performed by the controller, and the state of the input / output signal stored in the input / output table is read out at every predetermined sampling period. Then, the reference data for detecting an abnormal point is created using the state of the input signal when the state of the input signal changes as an expected input pattern, and the created reference data for detecting an abnormal point is stored in advance. Further, in the read state data, abnormality determination reference data is created using the state of the output signal when the state of the output signal changes as an output reference pattern, and the created abnormality determination reference data is stored in advance. Then, during the operation of the programmable logic controller, the output pattern of the programmable logic controller is compared with the output reference pattern of the abnormality determination reference data. If the output pattern does not match the output reference pattern, it is determined that there is an abnormality. An abnormal location is identified by comparing the input pattern of the programmable logic controller when it is determined that there is an abnormality with the expected input pattern of the abnormal location detection reference data.

The fault diagnosis apparatus according to the present invention has an input / output table for storing states of input / output signals, and a programmable logic controller for controlling the system in accordance with a predetermined program. The control operation is normally performed, and the state of the input / output signal stored in the input / output table is read out at a predetermined sampling period. Means for preparing and storing in advance the abnormal point detection reference data using the state of the output signal as the expected input pattern and the abnormality determination reference data using the state of the output signal when the state of the output signal changes as the output reference pattern. While the programmable logic controller is operating, Means for comparing the output pattern of the ramable logic controller with the output reference pattern of the abnormality determination reference data; means for determining that there is an abnormality when the output pattern does not match the output reference pattern; Means for identifying an abnormal point by comparing the input pattern of the programmable logic controller when the judgment is made with the expected input pattern of the abnormal point detection reference data.

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

According to the present invention, a monitoring target for abnormality detection (failure diagnosis) is limited to a signal output by a programmable logic controller (PLC) to control a controlled system. This is from the controlled system
It is not intended to exclude the signal input to C from being monitored, but it means that monitoring only the output signal is sufficient for the purpose of abnormality detection.

According to the present invention, since the output signal of the PLC is to be monitored, the pattern of the actual output signal during the operation of the PLC may be checked against the output reference pattern, so that the load on the processing device (especially the CPU) is reduced. Can be reduced.

Further, according to the present invention, when an abnormality is detected by monitoring the output pattern, the abnormal point detection reference data including the expected input pattern relating to the input signal is referred to for the first time.

In principle, the present invention is based on the premise that one output reference pattern corresponds to one expected input pattern. In the abnormal point detection reference data, an expected input pattern is registered corresponding to each output reference pattern. Therefore, if the occurrence of an abnormality is detected by comparing the actual output pattern with the output reference pattern, the part where the abnormality has occurred should be identified by comparing the actual input pattern at that time with the expected input pattern. Can be. As described above, abnormalities are often caused by failure of the input sensor, disconnection of the signal line, detection failure by the sensor due to insufficient operation of the device, etc., and these causes are reflected in the state of the input signal. You. By comparing the actual input pattern with the expected input pattern, it is possible to quickly identify the location where the abnormality has occurred.

Since the location where the abnormality has occurred is quickly and automatically extracted and output (displayed), it is possible to reduce the time required for maintenance and recovery work.

However, the present invention does not exclude that a plurality of expected input patterns correspond to one reference pattern. An OR signal of two or more input signals may generate an output signal to initiate or control some operation. Since such conditions are often known in advance when the control program is created, a plurality of expected input patterns corresponding to one output reference pattern should be registered in advance in the abnormal point detection reference data. I just need.

Since the reference data for detecting an abnormal point need only be referred to when an abnormality is detected, it may take some time to access the data. On the other hand, the reference data for abnormality determination is a real data during operation of the PLC.
Need to refer by time.

Therefore, it is possible to store the reference data for abnormality determination in the internal memory and store the reference data for abnormality detection in an external memory such as a memory of a support tool or a memory card. by this,
It is possible to reduce the storage capacity of the memory to be referred to during execution of the operation of the PLC.

The present invention further proposes a method for creating the above-described reference data for detecting an abnormal point.

A programmable logic controller having an input / output table for storing states of input / output signals and controlling the system in accordance with a predetermined program is used, and the system is controlled by the programmable logic controller according to the program. Control operation is normally performed, and the state of the input / output signal stored in the input / output table is read out at every predetermined sampling period, and the input state when the state of the output signal changes in the read state data is read out. An abnormal point detection reference data is created by using a signal state as an expected input pattern.

[0031]

[0032]

According to the present invention, it is possible to create the abnormal point detection reference data while reducing the burden on the operator.

[0034]

[Explanation of the embodiment]

 (1) Configuration Example of Failure Diagnosis Apparatus FIG. 1 shows a schematic configuration of a failure diagnosis apparatus.

This fault diagnosis device is integrally formed with a main body of a programmable logic controller (PLC). That is, a failure diagnosis function is added to the PLC body. Of course, it goes without saying that the failure diagnosis device can be configured as a separate unit from the PLC body.

The PLC 10 having the failure diagnosis function is composed of the CPU 11,
ROM 12, RAM 13, 14, timer 15, I / O (input / output)
Unit (interface) 16 and operation unit I / F
(Interface) consists of 17.

The ROM 12 stores a ladder control system program and a failure diagnosis program.

The RAM 13 has an area for storing a user program (ladder program) created by the user for controlling the controlled system, and an area for storing reference data for abnormality determination. The RAM 14 is used for work (work), and is used to store an I / O table that holds the actual states of input / output signals of the PLC and sampled input / output signals used in the failure diagnosis processing.

The CPU 11 controls the controlled system in accordance with the system program stored in the ROM 12 and the user program stored in the RAM 13, and stores the controlled system in the RAM 13 according to the failure diagnosis program stored in the ROM 12. The failure diagnosis process is performed using the abnormality determination reference data.

The timer 15 is for measuring the time required for transition of the output pattern in the failure diagnosis.

The I / O unit 16 stores PLCI / O data
It transmits and receives input and output signals to and from the controlled system via the bus.

The PLC 10 is connected to the console 20 via the operation unit I / F 17. The console 20 includes a computer main body (a so-called personal computer or the like), an input device such as a keyboard, an output device such as a display device or a printer, and a storage device including a hard disk and a floppy disk. This storage device stores the reference data for detecting an abnormal point. When the CPU 11 of the PLC 10 detects an abnormality, the CPU 11 performs a process of referring to the abnormal point detection reference data to specify the abnormal point. However, this reference data for detecting an abnormal point is used together with the reference data for abnormality determination in RA.
It may be stored in M13.

The input device of the console 20 is used for inputting an operation input such as setting of a user program to be set in the PLC 10 and inputting a command for causing the PLC 10 to create the above-described reference data. The output device (display device or printer) of the console 20 is used for outputting information such as notification of occurrence of an abnormality, notification of a found failure location, and the like.

When the failure diagnosis device is configured as a unit separate from the PLC, the failure diagnosis device includes a CPU for executing a failure diagnosis process, a ROM storing a failure diagnosis program,
It may be constituted by a timer, a RAM for storing the reference data for abnormality determination, and a RAM or another storage device for storing the reference data for abnormality detection. This fault diagnosis device will fetch the actual output pattern by accessing the PLC I / O table at regular intervals.

(2) Configuration of Controlled System and Example of Control FIG. 2 shows an example of the controlled system.

The work W is transported by the transport conveyor 91. The transport conveyor 91 is driven by a first motor (M1) 72. In the course of the conveyor 91, the detection of the presence of the work W and the detection of burrs on the work W are automatically performed. For this purpose, a first work detector 55 and a burr detector 56 are provided. When it is detected that the work W has burrs or that there is a burr larger than a predetermined amount, the work W is removed from the conveyor 91 by the defective removal pneumatic cylinder 73. During the operation of the cylinder 73, the rotation of the motor 72 is stopped, and the conveyor 91 is stopped.

The work W conveyed to the end by the conveyor 91 is moved to a carrier 92. A stay detector 57 for detecting the work W transported to near the end of the conveyor 91 is provided. When the state in which the stay detector 57 detects the work W has continued for a certain period of time or more, the abnormal lamp 71 of the operation panel 90 is turned on.

A second work detector 58 is provided for detecting the work W transferred from the transfer conveyor 91 onto the transfer table 92. When the work W is detected by the work detector 58, the input pneumatic cylinder 75 is driven, and the work W is pushed out onto the transfer table 92 toward the processing table 93 by the rod of the input cylinder 75. The work W transferred to the processing table 93 is detected by the third work detector 61.

When the work W is moved onto the worktable 93, a jig 77 for fixing the work W is driven in a direction to tighten the work W. A second motor (M2) 78 is driven to rotate, and a drill 79 fixed to the rotating shaft of the motor 78
The work W is lowered with 78, and a hole is formed in the work W. After the drilling operation, the drill 79 moves up with the motor 78, and the rotation of the motor 78 stops. The workpiece on which the holes are formed is finally discharged from the processing table 93 by the discharge pneumatic cylinder 81.

The operation panel 90 is provided with an operation switch 50, a stop switch 51, a release switch 52, a running lamp 70 and an abnormal lamp 71. When the operation switch 50 is turned on, the above-described series of steps starting from the activation of the motor 72 is started, and the in-operation lamp 70 is turned on.
When the stop switch 51 is turned on, the operation of the above steps is stopped, and the running lamp 70 is turned off. As described above, when the detection signal of the stay detector 57 continues for a predetermined time or more, the abnormal lamp 71 is turned on, and the operating lamp 70 is turned off. When the release switch 52 is turned on in this state, the abnormal lamp 71 is turned off.

The defective discharge cylinder 73 has a defective front end detector for detecting that the rod has advanced (advanced) and has reached its advanced end, and a defective front end detector for detecting that the rod has retracted and reached its retracted end. A rear end detector (both not shown) is provided. Similarly, the charging cylinder 75 has a charging front end detector and a charging rear end detector, and the discharging cylinder 81 has a discharging front end detector and a discharging rear end detector (both not shown).
Are provided respectively. Further, the upper end detector of the drill detects that the drill 79 (and the motor 78 to which it is attached) is raised and reaches its rising end, and the lower end detector of the drill which detects that the drill 79 is lowered and reaches its falling end. (Both not shown) are provided.

The signals input from the controlled system to the PLC 10 are as follows. (000) to (01
5) is the number of the input signal. The abbreviations are shown in parentheses at the end.

(000) ON / OFF signal of operation switch 50 (operation SW) (001) ON / OFF signal of stop switch 51 (stop S
W) (002) ON / OFF signal of release switch 52 (release S
W) (003) Detection signal of defective front end detector (Front front end) (004) Detection signal of defective rear end detector (Defective rear end) (005) Work detection signal of first work detector 55 (Detection 1) (006) Burr detection signal of burr detector 56 (burr detection) (007) Detection signal of stay detector 57 (stay detection) (008) Work detection signal of second work detector 58 (detection 2) (009) Detection signal of input front end detector (front end of input) (010) Detection signal of input rear end detector (rear end of input) (011) Work detection signal of third work detector 61 (detection 3) (012) Upper end of drill Detector detection signal (Drill upper end) (013) Drill lower end detector detection signal (Drill lower end) (014) Detection signal of discharge front end detector (Ejection front end) (015) Detection signal of discharge rear end detector (Ejection) Rear end)

The signals output from the PLC 10 to the controlled system include the following. (100) to (1
12) is the number of the output signal. The abbreviations in parentheses are used.

(100) ON / OFF control signal of operating lamp 70 (operating L) (101) ON / OFF control signal of abnormal lamp 71 (abnormal L) (102) Rotation drive control signal of first motor 72 (M1 rotation) (103) Forward drive control signal of defective exclusion cylinder 73 (defective forward) (104) Reverse drive control signal of defective exclusion cylinder 73 (defective reverse) (105) Forward drive control signal of input cylinder 75 (input forward) (106) Retraction drive control signal of the input cylinder 75 (input retraction) (107) Tightening drive control signal of the fixing jig 77 (jig tightening) (108) Rotation drive control signal of the second motor 78 (M2 rotation) (109) Drill 79 up drive control signal (drill up) (110) Drill 79 down drive control signal (drill down) (111) Forward drive control signal of discharge cylinder 81 (discharge forward) (112) Reverse drive control signal of the discharge cylinder 81 (ejection retracted)

FIG. 3 shows a part of a program (user program) set in the PLC 10 for controlling the above-mentioned controlled system. This program is expressed using contacts that are turned on and off by input signals, relays that generate output signals, contacts that are turned on and off by the relays, and internal auxiliary relays and their contacts.

The meanings of the internal auxiliary relay and its contacts shown in FIG. 3 are as follows. During the setting, it indicates the start of the entire drilling operation, and is turned on until the drilling operation and the discharge of the work are completed. The completion of the setting indicates that the setting of the work on the processing table is completed. Completion of processing indicates that the discharge of the work from the processing table has been completed. The loading memory indicates that the workpiece has been loaded into the processing table, and is turned on until processing and discharging are completed.

FIG. 4 shows the whole drilling operation (transfer of the workpiece W from the transfer table 92 to the processing table 93 by the input cylinder 75, a jig 77).
3 shows the operation of fixing the work W, the drilling of the work W by the motor 78 and the drill 79, and the discharge of the drilled work from the processing table 93 by the discharge cylinder 81). P
An input signal to the LC 10 and an output signal from the PLC 10 are shown. Further, a state in which the state of the output signal (output pattern) changes with the transition of time is shown. Numbers [1] to [7] are assigned to each state of the transitioning output signal (the state of the signal at the position where the broken line is drawn). Each of these states is hereinafter referred to as a state.

With the rising edge of the input signal "detection 2" as a trigger, the state shifts from state [7] to state [1] to be described later (the relationship between the input signal and output signal serving as a trigger is indicated by a chain line and an arrow). The transition of this state is executed by the program at the address 0039 shown in FIG. When the second work detector 58 detects the work W, the rod of the input cylinder 75 advances, and pushes the work W in the direction of the processing table 93.

Next, when the input front end detector detects that the rod of the input cylinder 75 has reached its forward end (input signal “input front end” is on), the state transits from state [1] to state [2]. Then, the rod of the input cylinder 75 stops the forward movement and starts the backward movement, the jig 77 starts fixing the work sent to the processing table 93, and the motor 78 is further driven to rotate. This is the address 00005 shown in FIG.
And so on.

When the input rear end detector detects that the rod of the input cylinder 75 has reached the retreat end (input signal “input rear end” is off), the state transits from state [2] to state [3]. The retraction operation of the charging cylinder 75 stops,
Drill 79 begins to descend. Thus, a hole is formed in the work W by the drill 79.

When the drill lower end detector detects that the drill 79 has reached the lower end (input signal “drill lower end” is ON), the state transits from state [3] to state [4], and the lowering of the drill 79 is performed. Stop and drill 79 begins to ascend.

When it is detected by the drill upper end detector that the drill 79 has reached the rising end (input signal “drill upper end” is on), the state transits from state [4] to state [5], and the jig 77 is moved to the work. And the rotation of the motor 78 stops.
The lifting of the drill 79 stops, and the rod of the discharge cylinder 81 starts to move forward. As the rod of the discharge cylinder 81 advances,
The drilled workpiece W is discharged from the processing table 93.

When the discharge front end detector detects that the rod of the discharge cylinder 81 has reached the forward end (input signal “discharge front end” is ON), the state shifts from state [5] to state [6], and the discharge cylinder 81 81 stops moving forward and starts retreating.

When the discharge rear end detector detects that the rod of the discharge cylinder 81 has reached the rearward end (input signal “discharge rear end” is on), the state transits from state [6] to state [7]. Thus, one drilling step is completed.

(3) Failure Diagnosis Processing In the controlled system shown in FIG. 2, the control of defective product removal by the defective cylinder 73 based on the detection of burrs and the above-described drilling control have little relevance to each other. . Therefore, the fault diagnosis of the rejection operation and the fault diagnosis of the drilling operation can be performed separately and independently. Hereinafter, the description will be limited to the failure diagnosis of the drilling operation.
Thereby, the essence of the present invention can be completely understood, and those skilled in the art can implement the present invention.

FIG. 5 shows a part of the reference data for abnormality determination for abnormality detection. The abnormality determination reference data is provided for each state, and includes output pattern data of the state, an average transition time from the previous state, and a permissible range of the transition time.

The output pattern data is a collection of data representing the state of all output signals to be monitored. The state of each output signal is represented by one bit. In this embodiment, the on state is 1 and the off state is 0.

FIG. 6 shows the above-mentioned seven states [1]-
The output pattern data of [7] is extracted from the abnormality determination reference data and summarized, and shows the states of the eight types of output signals shown in FIG. The correspondence can be easily understood by comparing the timing chart shown in FIG. 4 with the table of FIG.

Such output pattern data is obtained by actually operating the controlled system under the control of the PLC 10 and extracting the state of the output signal when the system operates normally when it changes. Can be created. Most commonly, the I / O provided in the RAM 14 of the PLC 10
The O table can be created by sampling the O table at a constant period and processing it. The details will be described in the description of the creation of the abnormal point detection reference data.

The average transition time from the previous state is the average time required to transition from the previous state to the state. This can be determined by repeatedly operating the controlled system under the control of the PLC 10 and calculating the average transition time when the system operates normally. Of course, when the time is known in advance, such as the set time of the timer, or when it can be theoretically easily obtained, the user may input.

The allowable variation time of the transition time represents the allowable range of deviation of the actual transition time from the average transition time, and will generally be input by the user. Of course, this proportionality constant may be determined uniformly, with all allowable widths being values proportional to the average transition time.

As the data relating to the transition time, in addition to the above-described combination of the average value and the allowable width, for example, a combination of the reference value, the lower allowable width, and the upper allowable width, and the combination of the maximum value and the minimum value may be used. it can.

The reference data for detecting an abnormal point is constituted by data representing an expected state (input expected pattern) of an input signal corresponding to the reference data for abnormality determination in each state described above. That is, the abnormal point detection reference data includes an expected input pattern set in advance for each state.

The abnormal point detection reference data is used to specify a part or a part that causes the detected abnormality when an abnormality is detected in the abnormality detection processing using the above-described abnormality determination reference data. . Therefore, in principle, all input signals which directly or indirectly affect the output signal to be monitored are selected. However, it is also possible to intentionally remove an input signal relating to a part that does not cause a problem even if it leaks from the abnormal part specifying process. It is not necessary to select an input signal that is unrelated to the output signal being monitored. For example, since there is no relationship between the drilling process and the defective work elimination process shown in FIG. 2, the input signal related to the work exclusion process is included in the reference data for abnormal location detection in association with the abnormality determination reference data for the drilling process. It need not be included.

In some cases, there may be a plurality of expected input patterns corresponding to one output reference pattern. In this case, the operation proceeds to the next state depending on the OR condition of a plurality of input signals. In such a case, a plurality of expected input patterns are registered in advance in association with the one-state abnormality determination reference data.

FIG. 7 shows an example of abnormal point detection reference data, which is composed of expected input patterns corresponding to each state shown in FIG. Also in this input expected pattern, the expected state of each input signal is represented by 1 bit, and ON is represented by 1 and OFF is represented by 0. The timing chart of the input signal shown in FIG.
By comparing the tables, the correspondence between them can be easily understood.

The reference data for detecting an abnormal part including such an expected input pattern is obtained by outputting the output signal when the controlled system is operating normally under the control of the PLC 10 while the controlled system is operating normally. It can be created by reading the state of the input signal when the state changes, and storing the read state of the input signal corresponding to the abnormality determination reference data relating to the state transition of the output signal.

In the control of the controlled system by the PLC 10 in particular, since an I / O table is provided in the RAM 14 of the PLC 10, the I / O table is used.
The output reference pattern shown in FIG. 6 and the expected input pattern shown in FIG. 7 can be created as follows.

The controlled system is operated under the control of the PLC 10. The data of the I / O table in the RAM 14, which stores the state of the input / output signals when the controlled system is operating normally, is read at regular sampling intervals.
It is checked whether the state of the output signal has changed among the states of the read input and output signals. When there is a change in the state of the output signal, the state of the output signal after the change is stored as an output reference pattern corresponding to the state number, and a part of the abnormality determination reference data is created. Further, the state of the input signal immediately after the change of the state of the output signal is stored as an expected input pattern in association with the above-mentioned state number, thereby creating abnormal point detection reference data.

As described above, what is always referred to in the abnormality detection processing is the abnormality determination reference data. Therefore, it is preferable to store the abnormality determination reference data in the RAM 13 which can be quickly accessed by the CPU 11. On the other hand, the abnormal point detection reference data is referred to for the first time when an abnormality is detected.
It does not necessarily require high speed, and can be stored in a storage device (hard disk, floppy disk, etc.) of the console 20. Of course, it goes without saying that the abnormal point detection reference data may be stored in the RAM 13.

FIG. 8 shows an algorithm of a failure diagnosis process executed by the CPU 11 of the PLC 10.

When a failure diagnosis function is added as a part of the functions of the PLC 10, the CPU 11 follows the PLC proper processing, that is, a user program partially shown in FIG. 3, in addition to the failure diagnosis processing. Execute the control process of the controlled system. The CPU 11 repeats a series of processing at a fixed cycle (cycle), and executes control processing of the controlled system in the first half of each cycle and failure diagnosis processing in the second half. Therefore, the failure diagnosis processing shown in FIG. 8 is repeated at a constant cycle.

The failure diagnosis processing shown in FIG. 8 is composed of an abnormality detection processing and an abnormal point identification processing. The abnormality detection processing is performed with reference to the abnormality determination reference data. The abnormality determination reference data is related only to the state of the output signal as described above. As described above, even if only the state of the output signal is monitored, it is possible to sufficiently detect the occurrence of the abnormality. The abnormality detection process must be performed in real time.
By monitoring only the output signal state in the abnormality detection processing, the processing can be speeded up.
The burden on PU11 is reduced. In the abnormality detection processing of this embodiment shown in FIG. 8, the order of state transition and the transition time are checked. When an abnormality is detected in the abnormality detection process, the process first proceeds to the process of specifying an abnormal portion with reference to the abnormal portion detection reference data.

The state (output pattern) of the output signal is read (sampled) from the I / O table of the RAM 14.
(Step 101). Since the output pattern sampled last time is stored in the predetermined area of the RAM 14, the previous sample pattern is compared with the current sample pattern (step 102).

The timer 15 is started when a transition is made from the previous state to the current state, and measures the time from the point of the transition to the current state.

If it is determined in step 102 that the previous sample pattern is the same as the current sample pattern, it is determined whether the current sample pattern is within the time range allowed to transition from the current state to the next state. It is checked (step 106).

That is, the current state is set to state [i]. The next state is state [i + 1]. The timer 15 counts the time from the time when the previous state [i-1] transits to the current state [i]. The time allowed to transition from the current state [i] to the next state [i + 1] is determined by the “average transition time from the previous state” and the “permissible range of transition time” in the reference data of the next state [i + 1]. Desired. It is determined in step 106 whether the time measured by the timer 15 is within the range of the allowable transition time obtained from the reference data of the next state [i + 1].

If the elapsed time is within the allowable range, the current sample pattern is stored in the above-mentioned area of the RAM 14 and the process returns to the step 101 (step 107).

If the elapsed time measured by the timer 15 exceeds the allowable transition time, it means that the transition to the next state has not been made even after the time allowed for the state transition has elapsed. It is determined that an abnormality has occurred, and the display device of the console 20 indicates that an abnormality has been detected and an output signal indicating that the abnormality has occurred (step 108), and proceeds to the process of detecting an abnormal portion starting from step 109. . An output signal in which an abnormality has occurred can be identified as a non-coincidence point in comparison between the current sample pattern and the output pattern of the next state [i + 1].

In step 102, if the previous sample pattern is different from the current sample pattern,
It is determined that the state of the output signal, that is, the state has transitioned. In this case, the time measured by the timer 15 is read as the actual transition time from the state [i] to the state [i + 1] (step 103). Also, the current sample pattern is compared with the output pattern included in the reference data of the state [i + 1] after the transition (step 104).
).

If the current sample pattern matches the reference output pattern (step 105), the flow advances to the next step 106 for checking the transition time. This sample
If the pattern and the reference output pattern do not match, it is determined that an error has occurred, an error is detected, and an output signal indicating that the error has occurred is displayed on the display device (step 108). Proceed to. In the comparison between the current sample pattern and the reference output pattern, a mismatched portion corresponds to an abnormal output signal.

In checking the transition time when transitioning from state [i] to state [i + 1], the timer
The actual transition time obtained from 15 is the state [i + 1]
Is determined to be within the range of the allowable transition time obtained from the data relating to the “average transition time from the previous state” and the “permissible variation of the transition time” stored as the reference data. If the actual transition time is within the transition allowable time,
The current sample pattern is stored in the RAM 14 (step 107), and the process returns to step 101. If the actual transition time is outside the transition allowable time, a message indicating that an abnormality has occurred and an abnormal output signal are displayed on the display device of the console 20 (step 108), and the process proceeds to the abnormal point specifying process after step 109.

The time required for the transition is measured by the timer 15
It is needless to say that the processing can be performed using a predetermined area of the RAM 14 without using the above.

In the process of specifying an abnormal part, first, the state (input pattern) of the input signal at the time when the abnormality is detected is read from the I / O table, and this sample input pattern is temporarily stored in the RAM 104 ( Steps
109).

Subsequently, state [i + 1] (if the transition from the current state to the next state does not occur even after the allowable transition time elapses), the state corresponds to the next state, and the current state changes to the next state. If the transition is made but the time required for the transition exceeds the allowable time, it corresponds to the next state: that is, in any case, if the current state is [i], the next state [i + 1]).
Is read and compared with the temporarily stored sample input pattern (step 110).
).

If there is a state of the input signal that does not match in the comparison between the expected input pattern and the sample input pattern, the input signal is displayed on the display device of the console 20 as an abnormal point (step 111).

The processing of steps 108 to 111 is performed on the console 20
May be executed by the CPU in the server. In this case, the CPU 11 of the PLC 10 will notify the CPU of the console 20 of data relating to the abnormality detection (abnormal output signal or state number).

As an example, it is assumed that the bit of the output signal “input advance” in state [1] has not become 1 even after the transition allowable time has elapsed.

According to the timing chart shown in FIG. 4, the output signal "input advance" is turned on by the input signal "detection 2" as a trigger. However, looking at the ladder program (address 0309) shown in FIG. 3, the output signal “input advance” indicates that not only the input signal “detection 2” is turned on but also the input signal “input rear end” is turned on. Is also turned on as a condition. Further, in order for the output signal “input forward” to be turned on, the input signal “detection 3”, “input front end”, the output signal “input reverse” and “set complete” must be on.

FIG. 9 shows an expected input pattern in state [1] and a sample input pattern (abnormal pattern) sampled when an abnormality is detected. By comparing these patterns, it is specified that the input signal “rear end”, that is, the input rear detector of the input cylinder 75 is abnormal.

If the expected input patterns include not only those directly related to the output signal but also the input signals indirectly related through an auxiliary relay such as set completion, the expected input pattern and the sample input By collating with the pattern, it is possible to immediately identify the part where the failure has occurred without performing the operation of checking the program list.

FIG. 10 shows a console when an abnormality is detected.
20 shows display examples displayed on 20 display devices. When an abnormality is detected, first, the occurrence of an abnormality such as "output:" input forward "does not turn on" in the upper stage and an abnormal output signal are displayed (step 108). Subsequently, abnormal point identification processing is performed, and the input signal and guidance for inspection found in this processing are displayed as follows: "The" rear end "does not match the standard. Check the sensor / wiring of the above signal." Is performed (step 111).

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a failure diagnosis device.

FIG. 2 is a configuration diagram illustrating an example of a controlled system.

FIG. 3 is a ladder diagram showing a part of a user program.

FIG. 4 is a timing chart showing the control operation of the controlled system;
It is a chart.

FIG. 5 shows an example of abnormality determination reference data.

FIG. 6 shows an example of an output reference pattern.

FIG. 7 shows an example of abnormal point detection reference data (expected input pattern).

FIG. 8 is a flowchart showing a failure diagnosis processing procedure.

FIG. 9 shows how an expected input pattern is compared with a sample input pattern (abnormal pattern).

FIG. 10 shows a display example when an abnormality occurs.

FIG. 11 is a ladder diagram for explaining a problem of a conventional failure diagnosis.

[Explanation of symbols]

10 PLC (Programmable Logic Controller) 11 CPU 12 ROM 13 RAM 14 RAM 15 Timer 20 Console

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Irie 10 Odron, Hanazono Todocho, Ukyo-ku, Kyoto-shi (56) References JP-A-62-49518 (JP, A) (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G05B 23/02 302 G05B 19/05

Claims (3)

(57) [Claims] 1. A programmable logic controller having an input / output table for storing states of input / output signals and controlling a system according to a predetermined program, wherein the programmable logic controller follows the program. When the control operation of the above system is performed normally, the state of the input / output signal stored in the input / output table is read out at a predetermined sampling period, and when the state of the output signal changes in the read state data, A fault diagnosis method that creates reference data for abnormal location detection using the state of the input signal as an expected input pattern. 2. The method according to claim 1, wherein the reference data for detecting an abnormal point is prepared and stored in advance, and the state of the output signal when the state of the output signal changes in the read state data is determined. Abnormality determination reference data is created and stored in advance as an output reference pattern. During the operation of the programmable logic controller, the output pattern of the programmable logic controller is used as the output reference pattern of the abnormality determination reference data. When the output pattern and the output reference pattern do not match, it is determined that there is an abnormality. When the abnormality is determined, the input pattern of the programmable logic controller is referred to as the abnormal point detection reference data. Identify abnormal locations by comparing with expected input patterns , Failure diagnosis method. 3. A programmable logic controller, which has an input / output table for storing states of input / output signals and controls the system in accordance with a predetermined program, performs a normal control operation of the system according to the program. In addition, the state of the input / output signal stored in the input / output table is read every predetermined sampling period, and the read state data indicates the state of the input signal when the state of the output signal changes in the expected input pattern. Means for preliminarily creating and storing anomaly determination reference data as an abnormal point detection reference data, and an abnormality determination reference data using an output signal state when an output signal state changes as an output reference pattern. During operation, the programmable logic controller Means for comparing the output pattern of the controller with the output reference pattern of the reference data for abnormality determination; means for determining that there is an abnormality when the output pattern does not match the output reference pattern; and determining that there is an abnormality. Means for identifying an abnormal location by comparing the input pattern of the programmable logic controller at the time with the expected input pattern of the abnormal location detection reference data.