JP3134655B2 - High resolution analog / digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter (hereinafter abbreviated as "AD converter"), and more particularly to a high-resolution analog-to-digital converter of a feedback pulse width modulation system. .

[0002]

2. Description of the Related Art A feedback-type pulse width modulation (hereinafter simply referred to as PWM) type AD converter has been conventionally known. FIG.
FIG. 1 shows an example of a principle configuration diagram of a PWM type AD converter.
In the figure, the measured input voltage E _X is led to an input terminal of the operational amplifier 1 through the input resistor R _1. The operational amplifier 1 has a capacitor C ₁ in the feedback path is connected. Further, the switch SW ₁ and the resistor R
_A negative reference voltage −E _S or a positive reference voltage + via _S
E _S is selectively applied, and the clock voltage (± E _C ) from the square wave clock voltage generator 3 is applied via the resistor R _C. The clock voltage generator 3 divides the frequency of the reference clock generated by the normal clock generator 5 and generates a clock voltage such that the duty ratio is 50 and the average DC voltage in one cycle becomes zero. Incidentally, the operational amplifier 1, capacitors C _1, resistors R _1, R _S, the portion consisting of R _C is in the integrator.

[0003] The comparator 2 compares the output of the integrator with a zero level, so the integrator output is the reference voltage + E _S when the positive is, when the negative -E _S is negatively fed back to the integrator Switch S
The W ₁ is adapted to drive. Switch SW ₁ is +
E _S side or -E _S side in contact with that period will vary with the magnitude of the input voltage, an equilibrium state where the average value is canceled exactly the input voltage E _X over one period. The clock voltage ± E _C activates the system,
A repetition period T is determined.

[0004] Now, as shown in FIG. 5, T ₁ a time period in which the switch SW ₁ is in contact with the reference voltage + E _S side, the period in contact with -E _S side and T _2, also resistors R ₁ and R _S if equal, when the system is in _{equilibrium, E X · T = E S} (T 2 -T 1) ∴E X = E S · (T 2 -T 1) / T ...... (1) However, T ₁ + T ₂ = T holds. Since E _S and T are already values, it is possible to know the input voltage E _X by taking the (T ₂ -T _1).

The gate control circuit 4 opens the gate for the period T ₂ (or T ₁ ) based on the output of the comparator 2 and passes the reference clock CLK from the clock generator 5. Counting unit 6
Then, the passing clock is counted, _EX is obtained based on the above equation (1), and EX is digitally displayed on the display 7.

[0006] AD converter of such PWM system, depends only on the accuracy and reference voltage ± E _S resistor R _1, R _S, affected by amplification of the clock voltage ± E _C and operational amplifier In addition, since the pulse width modulation is highly accurate and highly stabilized by the negative feedback, the pulse width modulation is excellent in that it is not affected by the dead band voltage of the comparator.

However, since such a PWM type AD converter is of a feedback type, it generally has a slow response and requires several cycles of the clock voltage E _C until it is stabilized against a step input.

The response of the system to a step input will be described below. In the integrator output waveform shown in (3) of the same B, each time interval t ₁ , t ₂ , t ₃ , t ₄ ,. . . The inclination k ₁ of the waveform at each _{time, k 2, k 3, k} 4, and. . . And the following relationship is established.

(Equation 1) Also,

(Equation 2)

[0009] Each inclination is as follows. _{k 1 = (E C -E S} -E X) / CR k 2 = (- E C -E S -E X) / CR k 3 = (- E C + E S -E X) / CR k 4 = ( _{E C + E S -E X)} / CR ...... (4)

Further, if one cycle is formed by k ₁ , k ₂ , k ₃ , and k ₄ , the following relationship is established at the same time. k ₁ = k ₅ = k ₉ = ... = k _4n-3 = k _{4n + 1} k ₂ = k ₆ = k ₁₀ = ... = k _4n-2 = k _{4n + 2} k ₃ = k ₇ = k ₁₁ = ... = k _4n-1 k ₄ = k ₈ = k ₁₂ = ... = k _4n …… (5)

If the dead band voltage of the comparator is zero and the above equation is satisfied,

(Equation 3) and,

(Equation 4) Is obtained. And

(Equation 5) , T _4n−1 , t _4n , t _{4n + 1} , and t _{4n + 2} are respectively obtained.

However, a point to be noted as the pulse width modulation operation is that the period (t) of the pulse which is more positive than the length of each time axis.
_{4n + 1} + _{t4n + 2} ) and a negative pulse period ( _t4n-1 + _t4n ).
Each pulse period is as follows.

(Equation 6) Also,

(Equation 7)

In the above equation, (k ₁ k ₃ ) / (k ₂ k ₄ ) is 1
If it is smaller, eventually when n increases,

(Equation 8) Becomes

The response to the step voltage is as follows. (K ₁ k ₃ ) / (k ₂ k ₄ ) needs to be minimized in order to quickly converge to a steady pulse width when a step voltage is applied. Here, when the E _X = mE _S,

(Equation 9) Is obtained.

[0015] Using m as a parameter, (k ₁ k ₃ ) / (k ₂ k ₄ ) and E
FIG. 6 shows the relationship of _S / E _C. (k ₁ k ₃ ) / (k ₂
k ₄ ) is positive, so (k ₁ k ₃ ) regardless of the value of m
In order for / (k ₂ k ₄ ) to be positive, it is necessary that E _S / E _C ≦ 0.5. However, when E _S / E _C = 0.5, although the system is responsive, the system becomes unstable, so that E _S / E _C <
It is set to 0.5. For example, E _S / E _C = 0.45
When, to become zero voltage when turning off the E _X to its residual voltage becomes smaller than 0.01% _{E X, {(k 1 k} 3) / (k 2 k 4)} n = (0 .14) It is necessary to satisfy ⁿ ≦ 10 ⁻⁴ . Therefore, n ≧ 5, and a time longer than 5 cycles of the clock voltage is required. In _{n = 5, {(k 1} k 3) / (k 2 k 4)} n is E _S / E _C becomes ^10-4 or less, when calculated as m = 0 in the above (14), E _S / E _C ≧ 0.4305. In short, when n = 5, 0.5> E _S / E _C
If ≧ 0.4305, the pulse width time can be measured with an accuracy of 0.01% or more for the step input, and the first four digits of the measured value are values whose accuracy is guaranteed. FIG. 7 conceptually shows a response characteristic to the above-described step input.

[0016]

However, since the counting section 6 counts the pulse width time with the reference clock CLK, a quantization error cannot be avoided, and a 1 or 2 digit quantization error is involved. was there. Also,
There has been a problem that the accuracy cannot be further improved without changing the measurement conditions, that is, the ratio of E _S to E _C and the value of n. An object of the present invention has been made in view of such a point. AD conversion is divided into an upper digit and a lower digit, and is obtained.
It is intended to realize an M-type AD converter.

[0017]

In order to achieve the above object, according to the present invention, a feedback pulse for integrating a square wave clock voltage, positive and negative reference voltages, and an input voltage to obtain a digital value corresponding to the input voltage. A width modulation type analog-to-digital converter, which counts an integration time of the reference voltage with a reference clock, and obtains an upper digit count value at i digits which is one digit larger than the digit number whose accuracy is guaranteed; A section averaging circuit for section averaging the reference voltage switched to the section in synchronization with the square-wave clock voltage signal, and a digital conversion of a difference between the input voltage and the section averaging circuit to obtain a j-digit lower digit count value. A voltage measuring unit, and a controller that combines the measured value of the upper digit and the measured value of the lower digit, discards the least significant digit of the upper digit, adds the measured value of the lower digit thereto, and synthesizes the measured value of the (i−1 + j) digit. , Characterized by comprising a display for digitally displaying the output of this controller.

[0018]

The input voltage EX is _expressed by the upper digit (i digit) and the lower digit (j
Digit), and combine them later. The upper digits are obtained by the same PWM method as in the past. However, the number of digits (i digits)
Is the number of digits one digit larger than the number of digits whose accuracy is guaranteed. Lower digit (j digits) is pulse width modulated reference voltage signal difference direct current value and the input voltage E _X by the section average (E _X -
An E _X ^'), obtained by the minute voltage measuring unit. The measured values of the upper digit and the lower digit obtained in this way are combined in the controller. At the time of synthesis, the least significant digit of the upper digit is rounded down (to i−1 digit), and the measured value of the lower digit (j digit) is added thereto to obtain a combined value of i−1 + j digits. By truncating the least significant digit of the upper digit, it is possible to eliminate the quantization error mixed in the measurement of the upper digit, and to use only the value of the significant digit whose accuracy is guaranteed. The minimum resolution is determined by the lower digit. In this way, a high-precision, high-resolution AD with no quantization error without lowering the response speed
A converter can be realized.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
FIG. 1 is a principle configuration diagram showing one embodiment of a high-resolution AD converter according to the present invention. The same parts as those in FIG. 4 are denoted by the same reference numerals, and the description of those parts will be omitted.

In the figure, 6a is a counting section, 10 is a section averaging circuit, 20 is a differential amplifier, 30 is a minute voltage AD converter, and 40 is a controller. The counting unit 6a counts the reference clock CLK that has passed through the gate control circuit 4 in the same manner as the conventional counting unit 6 shown in FIG. 4, but here counts five digits, which is one digit larger than the conventional case. . The accuracy is assured for the upper four digits as described in the conventional example, but errors are mixed in the least significant digit. Note that the quantization error is also included in the least significant digit.

The section averaging circuit 10 calculates the section average of the voltage waveform (pulse width modulated reference voltage waveform) appearing at the common connection point of the switch SW ₁ and the resistor R _S. FIG. 2 shows an example of the section averaging circuit.

In FIG. 2, reference numeral 101 denotes an integrator, which is an operational amplifier 10 to which negative feedback is applied via a capacitor C _2.
The 2 via an input resistor R ₂ input signals E _i (here,
The pulse width modulated reference voltage waveform is provided.
A sample and hold circuit 103 samples and holds the output of the integrator 101 each time a sampling pulse P arrives. The sample hold voltage is negatively fed back via a resistor R ₃ to the input terminal of the integrator 101.

According to such an interval averaging circuit, the output of the integrator is sampled and held, and the output is fed back to the integrator again. Integrate the difference between the value and the instantaneous value of the input signal in the current section. Therefore, there is an advantage that there is no unnecessary pulsation as compared with a section averaging circuit in which integration, hold and reset are repeated for each section. The sample and hold circuit 103 obtains a DC voltage signal obtained by averaging the input signal for each section. Here, the sampling pulse P to be used is a pulse synchronized with the clock voltage ± E _C, the pulse P is generated based on the clock voltage ± E _C in the controller 40.

The differential amplifier 20 multiplies the difference between the input voltage and the output voltage of the section average circuit by n times and outputs the result. Here, it is assumed that n = 10 for convenience. The micro voltage AD converter 30 digitizes the output of the differential amplifier 20. For the micro voltage measurement, any type of PWM type or double integral type AD converter can be used for measuring the micro voltage. You can use it. Note that the differential amplifier 20 and the small voltage A
The part including the D converter 30 is referred to as a minute voltage measuring unit here.

The controller 40 combines the upper digit value obtained by the counting section 6a with the lower digit value obtained by the minute voltage A / D converter 30 to digitally display the result on the display 7; It has a generation function and a function of managing the number of cycles from the start of measurement when the values of the counting unit 6a and the minute voltage measuring means are combined.

The operation in such a configuration will be described below. Hereinafter, the measurement conditions are the same as those in the related art, that is, E _S / E _C is around 0.5 and the clock voltage 5
An example will be described in which the counting unit 6a can measure the pulse width time with an accuracy of 0.01% when the number of cycles has elapsed. The counting unit 6a measures the PWM pulse width with five digits (i = 5), which is one more than the predetermined number of digits (four digits) at which the accuracy of 0.01% is guaranteed. The controller 40 reads the measured value of the measuring part 6a when the n = 5 from the input voltage E _X measurement start (5 cycle) (this is referred to as upper digit measure). The measured value at this time is, for example, as shown in FIG.
It is assumed that the value is 3.2537 (V). In this case, the top 4
The digit number “3.253” is accurate, but the least significant digit “7” is not guaranteed to be accurate. This also includes a quantization error.

On the other hand, in the section averaging circuit 10, the switch SW
Modulated signals ± E _S appearing in the _first common contact (a square-wave signal of FIG. 4 (2)) is sampled and held. The output E _OUT at this _{time, E S · T 1 / R} 3 -E S · T 2 / R 3 = -CE OUT ∴E OUT = E S (T 2 -T 1) / (C · R 3) ... … (15) If the time constant C · R ₃ is equal to T, equation (1) and (1
5) is equal, so that the output E _OUT is equal to the value E _X ^′ of the solid line in FIG. E _X ^', as is clear from FIG. 5, always less than the input voltage E _X is the number of cycles around the clock voltage. Differential amplifier 20, the input voltage E _X
Difference between the output E _OUT (= E _X ^') of the interval average circuit 10 and (E _X
-E _X ^') to amplify 10 times.

The AD converter 30 for small voltage digitizes outputs, i.e. the ^{_{(E X -E X ') ×}} 10 of the differential amplifier 20. For example, it is assumed that digital conversion is performed with four digits, and the value at this time (referred to as a lower digit measurement value) is 6,448.
Assume that This four-digit value corresponds to (E _X -E _X ^'), as shown in FIG. 3, the most significant digit is coordinated to the least significant digit of the measurement value of the counter 6a. The controller 40 cuts off the least significant digit of the upper digit measurement value measured by the counting unit 6a, extracts only the upper four digits, adds the lower digit measurement value obtained by the minute voltage measurement unit to the four digits, and adds the eight digits. This is passed to the display 7 as a measured value.

However, in the section averaging circuit 10, the counting section 6a
Since the output appears at a timing delayed by one cycle with respect to the measured value, the controller 40 uses the output of the minute voltage measuring unit when n = 6 (the sixth cycle of the clock voltage) as the lower digit measured value.

As described above, by truncating the least significant digit of the measured value of the upper digit, the quantization error is prevented from being mixed, and the number of digits can be increased by synthesizing the upper digit and the lower digit. A high-resolution AD converter can be easily realized.

It should be noted that the present invention is not limited to the embodiments, and that structural modifications can be made as appropriate without departing from the spirit of the present invention. For example, in the embodiment, the measurement by the counting unit 6a is set to five digits, but the present invention is not limited to this.
The value of n may be increased, and the measurement by the counting unit 6a may be performed with six digits (only the first five digits are used during synthesis). Further, n may be smaller than 5. Generally, the counting unit 6a measures i digits, and the minute voltage measuring unit measures j digits. It is sufficient that the least significant digit of the i digit is deleted at the time of synthesis and the j digit of the lower digit is added thereto. However, E _S / E _C and n need to be set so that desired accuracy is ensured in the upper digit measurement value.

In the differential amplifier, the signal to be supplied to the minute voltage AD converter is set to 10 times amplification in order to make the signal have an appropriate magnitude. However, the magnification is not fixed but can be changed as appropriate. However, it is desirable to set 10 ^k (k = 0, 1, 2,...) In order to simplify the combination of the upper digit and the lower digit by the controller.

[0033]

According to the present invention as described in the foregoing, individually determined by dividing the input voltage E _X to the upper and lower digits, lower digits measurements the least significant digit of the ascending digit measured value after the most By combining by overwriting with the upper digit, it is possible to easily realize a high-precision, high-resolution AD converter without lowering the response speed while preventing the mixing of quantization errors in the upper digit measurement value. The effect is large in practical use.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram showing an embodiment of a high-resolution AD converter according to the present invention.

FIG. 2 is a configuration diagram illustrating an example of a section averaging circuit.

FIG. 3 is an explanatory diagram showing a state of combining upper digits and lower digits.

FIG. 4 is a diagram illustrating an example of a principle configuration diagram of a conventional PWM type AD converter.

FIG. 5 is an operation waveform diagram in PWM AD conversion.

FIG. 6 is a graph showing a relationship between (k ₁ k ₃ ) / (k ₂ k ₄ ) and E _S / E _C.

FIG. 7 is a diagram for explaining response characteristics.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Operational amplifier 2 Comparator 3 Clock voltage generator 4 Gate control circuit 5 Clock generator 6a Counter 7 Display 10 Section averaging circuit 20 Differential amplifier 30 Micro voltage AD converter 40 Controller

Claims (2)

(57) [Claims] 1. A square wave clock voltage (± E _C) positive and negative reference voltage (-E _S, + E _S) and integrates the input voltage (E _X), a digital value corresponding to the input voltage (E _X) A feedback pulse-width modulation type analog-to-digital converter which obtains the integration time of the reference voltage using a reference clock and obtains a higher-order digit count value at i digits which is one digit larger than the number of digits whose accuracy is guaranteed. And a section averaging circuit (1a) for averaging the section of the reference voltage, which is alternately switched, in synchronization with the square wave clock voltage signal.
0), the difference between the input voltage (E _X) and interval average circuit (10) to digital converter, a minute voltage measuring portion for obtaining a lower digit count value of j digits, the upper digit measured value and the lower digit measurement value When combining the (4), the controller (4) that cuts off the least significant digit of the upper digit and adds the measured value of the lower digit to the (i−1 + j) digit measured value
0) and a display for digitally displaying the output of the controller (40). 2. The method according to claim 1, wherein said E _S / E _C is smaller than 0.5 and 0.4.
3 and sets the above range, the a 5-digit number of digits i of the measuring part (6a), wherein the controller (40) is at 5 cycles elapse of the clock voltage from the measurement starting point of the input voltage (E _X) 2. The high resolution analog-to-digital converter according to claim 1, wherein the count value of said measuring section (6a) is adopted as a higher-order digit count value.