JP3134830B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device realizing miniaturization and high speed.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices have been subjected to submicron processing for high integration and high speed processing, miniaturization, and reduction of parasitic capacitance.

For this reason, in the current photolithography method, it is difficult to realize processing of a submicron size or less due to a pattern shift, and a fine pattern is formed by a self-alignment (self-alignment) technique.

A conventional method for manufacturing a semiconductor device will be described with reference to FIG. First, as shown in FIG. 6A, an n-type buried collector layer 32 is formed on a P-type semiconductor substrate 31,
An n-type epitaxial layer 33 is formed thereon. Further, the main surfaces of the emitter and base regions are protected by a nitride film 34, and an oxide film 35 is formed therearound.

[0005] Next, as shown in FIG.
The nitride film 34 is changed to an oxide film 36 during the formation, and the periphery thereof is etched by photolithography. Further, a polycrystalline silicon 37 is formed, n-type ion implantation is performed, and a heat treatment is performed so as to reach the buried collector layer 32. Then, an extraction collector region 38 is formed. Further, the polycrystalline silicon on the main surface of the oxide film 36 is removed by photolithography.

[0006] Next, as shown in FIG.
Is removed, the oxide film 42 is vapor-phase grown on the entire surface, the external base region 39 is selectively opened, and after growing the polycrystalline silicon 40, P ⁺ type ion implantation is performed. Form. Further, the base region is selectively opened in the oxide film 42, and the base region 41 is formed by P-type ion implantation.

[0007] Next, as shown in FIG.
Is grown, the emitter region is opened, and the emitter region 44 is formed by ion implantation of n ⁺ type. Then base 4
5. Opening the collector 46 completes each base region and collector region.

Further, a method of manufacturing a semiconductor device by a self-alignment technique is disclosed in Japanese Patent Application Laid-Open Nos. 8-293504 and
-310520.

[0009]

However, the conventional example shown in FIG. 6 has a problem that the parasitic capacitance of the external base region, the intrinsic base region, and the emitter region increases.

The reason is that the mask alignment accuracy of the current exposure apparatus is about ± 0.2 μm, so that the buried collector region and the external base region and the margin between the external base region and the emitter region need to be 0.4 μm. Is increased.

Further, the manufacturing methods disclosed in Japanese Patent Application Laid-Open Nos. 8-293504 and 6-310520 have a problem that the collector region becomes large, which leads to an increase in parasitic capacitance and transistor size.

The reason for this is that the collector lead-out region is located on the outer periphery of the LOCOS and the trench. Usually, the base lead electrode and the collector lead electrode are arranged above the locos and trenches in order to reduce the parasitic capacitance, and the locos and trench widths are increased to several μm or more, and the buried collector region is enlarged accordingly.

An object of the present invention is to provide a method of manufacturing a semiconductor device which realizes miniaturization, high speed, and high integration of elements by a self-alignment technique.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a method of manufacturing a semiconductor device of one conductivity type.
Forming buried collector region of opposite conductivity type on semiconductor substrate
Forming an epitaxial layer of the opposite conductivity type on the substrate
And the first oxidation grown on the main surface of the epitaxial layer.
Selective removal of film, collector drawer, external base, true
Do not surround the area where the base and emitter will be formed.
The method of manufacturing a semiconductor device having that insulating film, wherein
A first nitride film is grown on the main surface of the epitaxial layer, and
The oxide film is etched back on the side wall of the first oxide film.
A step of leaving a serial first nitride layer, said epitaxial layer main
One conductivity type polycrystalline silicon is grown on the surface and etched back
The one conductivity type polycrystal on the side wall of the first nitride film
A step of leaving silicon, and on the main surface of the epitaxial layer,
Grow a second nitride film and etch back
Leaving the second nitride film on the sidewalls of the polycrystalline silicon of the mold type, and ion-implanting from the main surface of the epitaxial layer.
From the predetermined depth of this epitaxial layer,
Forming a reverse conductivity type diffusion region reaching the collector region, and forming a reverse conductivity type polycrystalline silicon on the main surface of the epitaxial layer.
Grow a silicon and etch back the second nitride film
Leaving the opposite conductivity type polycrystalline silicon on the side walls of ;
Forming a third nitride film and a second acid on the main surface of the epitaxial layer;
A nitride film is grown and the first to third nitrides are etched back.
Oxide film, the first oxide film, the one conductivity type and the opposite conductivity type
Step of flattening polycrystalline silicon and heat treatment
Diffusing impurities from each polycrystalline silicon, the reverse conductivity type
Conductor withdrawal and conduction of reverse conductivity type connected to diffusion region
Forming an external base of the electric type, and the first oxide film
Is removed, and heat treatment after ion implantation is performed with the external base.
Forming an intrinsic base of one conductivity type to be connected, the
Process to form emitter by ion implantation in intrinsic base
It has a process .

In addition, the collector drawer is provided with the embedded collector.
That directly reach the collector region .

Also, the collector drawer and the external base
Are formed simultaneously by heat treatment .

In addition, a second conductive type second conductive layer is provided on the intrinsic base main surface.
Grown polycrystalline silicon, etched back and heat treated
It forms the emitter more .

An insulating film is grown on the main surface of the semiconductor device.
Aperture windows that selectively act as emitter, base and collector
To form an emitter electrode, a base electrode, and a collector electrode.
It forms the poles .

[0019]

According to the self-alignment of the present invention, the dimensions of the emitter / base / collector region are determined by the thickness of the insulator or polycrystalline silicon. Miniaturization can be realized.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1A is a plan view showing a semiconductor device according to Embodiment 1 of the present invention, and FIG.
FIG. 2 is a sectional view taken along line XX ′ of FIG.

As shown in FIG. 1 (b), a region which becomes a semiconductor device after being separated from other elements by the LOCOS 6 has N
^- N-type diffused -type polysilicon 10 collector lead 1
N-type diffusion layer 9 previously diffused by N-type ion implantation
Electrically connects the buried collector 2 with the buried collector 2.

Next, the external base 13 is formed by diffusion of the P-type polysilicon 7 insulated from the N-type polysilicon 10 by the thickness of the Si ₃ N ₄ film 8. Further, P-type ions are implanted from an emitter opening window separated by the thickness of the Si ₃ N ₄ film 5 to form an intrinsic base 14 connected to an external base 13 by thermal diffusion.
The respective regions are completed by performing N-type ion implantation to be 5.

At this time, in the emitter / base / collector region, it is possible to eliminate a mask misalignment caused by an exposure machine in each region by a self-alignment technique. Since the size of each region is determined by the thickness of the polysilicon, it can be controlled within several tens of square meters.

Next, a specific example of Embodiment 1 of the present invention will be described in detail as Example 1 with reference to the drawings. FIG.
FIG. 3G is a structural cross-sectional view showing Example 1 of the present invention in the order of steps. First, as shown in FIG. 2A, an N-type buried collector 2 is formed in a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 having a thickness of about 1 μm is grown. Thereafter, the SiO ₂ film 4 is coated on the main surface of the epitaxial
Grow 000 $. The thickness at this time is finally adjusted by the design value of the parasitic capacitance of the emitter, base and collector electrodes. Further, the oxide film 4 is formed by photolithography so as to have a width of about several hundreds to about 1000 so as to selectively have a final emitter width.

Next, as shown in FIG. 2 (b), a Si ₃ N ₄ film 5 (nitride film) is grown on the entire
Is selectively removed by photolithography, and LOCOS 6 is formed by thermal oxidation.

[0028] Next, as shown in FIG. 2 (c), Si ₃ N ₄ film 5 are etched back leaving the side wall of the SiO ₂ film 4, the polysilicon 7 doped with boron to 1000Å growth, Si ₃ N by etching back _{4 The} film is left on the side wall of the film 5. Similarly, a Si ₃ N ₄ film 8 is grown at 1000 ° and is left on the side wall of the boron-doped polysilicon 7 by etch back. afterwards,
N-type ion implantation is performed, and an epitaxial layer depth of 0.5
The connection to the buried collector 2 is made from about μm.

[0029] Next, as shown in FIG. 2 (d), the polysilicon 10 doped with phosphorus was 1000Å grown, is formed on the sidewall of the Si ₃ N ₄ film 8 by etching back, 2000 Å or more so as to cover each etchback territory Of the Si ₃ N ₄ film 11 and the SiO ₂ film 19 (silicon oxide film)
Grow over Å.

Next, as shown in FIG. 3E, an etch-back is performed so that each etch-back area becomes flat. Thereafter, heat treatment is applied to form an N-type collector lead 12 and a P-type external base 13 directly below the polysilicons 10 and 7, respectively. At this time, boron-doped polysilicon 7 is 1 × 10 ²⁰
cm ^-3 , phosphorus-doped polysilicon 10 is 1 × 10 ²¹ cm
^Keep the concentration at about ^-3 .

Next, as shown in FIG. 3F, the SiO ₂ film 4 is removed, P-type ion implantation is performed at about 1 × 10 ¹⁶ cm ^-3 , and heat treatment is performed so as to connect to the external base 13. An intrinsic base 14 is formed, and N-type ion implantation is performed at 1 × 10
^{The process} is performed at about ²¹ cm ⁻³ to form the emitter 15.

Next, as shown in FIG. 3 (g), a SiO ₂ film 16 is grown and each contact region (emitter, base,
The collector is selectively opened, and an emitter electrode and a collector electrode are formed to complete each region.

(Embodiment 2) Next, Embodiment 2 of the present invention
Will be described with reference to FIG. 4A is a front view, and FIG. 4B is a cross-sectional view taken along line XX ′ of FIG. 4A.

The second embodiment of the present invention is characterized in that the N-type epitaxial layer 3 is thinned to about 0.5 μm to reduce the collector resistance in order to realize an operation at a higher frequency than the first embodiment. Things. In this case, since the epitaxial layer 3 is sufficiently thin, the buried collector 2 is connected only by diffusion of the N-type polysilicon 10, and the N-type diffusion layer 9 is unnecessary. If the emitter 15 is directly ion-implanted from the main surface of the intrinsic base 14, a channel is formed in the depth direction and it is difficult to make the emitter junction shallower. It is possible to form a shallow emitter 15.

Further, a specific example of Embodiment 2 of the present invention will be described as Example 2. FIGS. 5A to 5C are cross-sectional views illustrating a second embodiment of the present invention in the order of steps. FIG. 5 (a)
As shown in FIG. 7, when the epitaxial layer 3 is sufficiently thin, 0.5 μm, the N-type collector lead 12 is connected to the buried collector 2 only by diffusion of the phosphorus-doped polysilicon 10, so that the N-type diffusion layer 9 by ion implantation is unnecessary. Becomes

Next, as shown in FIG. 5B, the SiO ₂ film 4 is removed, and ion implantation for forming the intrinsic base 14 is performed.
An N-type doped polysilicon 18 (phosphorus or arsenic) is grown at a concentration of about 2 × 10 ²¹ cm ^−3, etched back, and heat-treated to form the emitter 15.

Next, as shown in FIG. 5C, an SiO ₂ film 10 is grown, each contact (emitter / base / collector) area is selectively opened, and an electrode is formed. (Emitter, base, and collector) is completed.

[0038]

As described above, according to the present invention, it is possible to prevent misalignment of a mask by an exposure apparatus.
The dimensional correction due to the displacement becomes unnecessary, and the element can be reduced accordingly.

The reason is that the emitter, base and collector are formed by a self-alignment technique.

Further, since the dimensional method of each region (emitter / base / collector) and the distance between the regions can be controlled in units of several tens of square meters, it is possible to realize a significant reduction in the size of the device.

The reason is that each region (emitter, base,
This is because the distance between the collector and each region is determined by the thickness of the insulator or the polycrystalline silicon.

[Brief description of the drawings]

FIG. 1A is a plan view showing a first embodiment of the present invention,
FIG. 2B is a sectional view taken along line XX ′ of FIG.

FIG. 2 is a cross-sectional view showing Embodiment 1 of the present invention in the order of manufacturing steps.

FIG. 3 is a sectional view showing Embodiment 1 of the present invention in the order of manufacturing steps.

FIG. 4A is a plan view showing a second embodiment of the present invention,
FIG. 4B is a cross-sectional view taken along line XX ′ of FIG.

FIG. 5 is a sectional view showing Example 2 of the present invention in the order of manufacturing steps.

FIG. 6 is a sectional view showing a conventional example in the order of manufacturing steps.

[Explanation of symbols]

1 P-type substrate 2 buried collector 3 epitaxial layer 4,6,16,19 SiO ₂ film _{5 · 8 · 11 Si 3 N} 4 film 7 boron-doped poly silicon 10 phosphorous doped poly silicon 9 N-type diffusion layer 12 N-type collector lead-out 13 P-type external base 14 P-type intrinsic base 15 Emitter 16 Emitter electrode 17 Collector electrode 18 N-type polysilicon

Claims (5)

(57) [Claims] A semiconductor device of the opposite conductivity type is embedded on a semiconductor substrate of one conductivity type.
Formed on the substrate, and a reverse conductivity type
Form a epitaxial layer, and on the main surface of the epitaxial layer
Selectively remove the grown first oxide film,
To form an external base, intrinsic base, and emitter.
In a method of manufacturing a semiconductor device having an insulating film surrounding a constant region, a first nitride film is grown on the main surface of the epitaxial layer, and
The nitride film is etched back by etching the side wall of the first oxide film.
Leaving the first nitride film on the surface of the substrate, and forming one conductivity type polycrystalline silicon on the main surface of the epitaxial layer.
Is grown and etched back to form sidewalls of the first nitride film.
Leaving the one conductivity type polycrystalline silicon on, and growing a second nitride film on the epitaxial layer main surface,
The side of the one conductivity type polycrystalline silicon is etched back.
Leaving the second nitride film on the wall; and performing ion implantation from the main surface of the epitaxial layer.
From the predetermined depth of the epitaxial layer,
Forming a reverse conductivity type diffusion region reaching the region, and forming a reverse conductivity type polycrystalline silicon on the main surface of the epitaxial layer.
Is grown and etched back to form sidewalls of the second nitride film.
Leaving a polycrystalline silicon of the opposite conductivity type on the main surface and a third nitride film and a second acid on the main surface of the epitaxial layer.
A nitride film is grown and the first to third nitrides are etched back.
Oxide film, the first oxide film, the one conductivity type and the opposite conductivity type
A step of planarizing the polycrystalline silicon, and diffusing impurities from the polycrystalline silicon by heat treatment
And a reverse conductivity type collector connected to the reverse conductivity type diffusion region.
A step of forming an external base of one conductivity type and removing the first oxide film, and performing a heat treatment after ion implantation.
Form an intrinsic base of one conductivity type connected to the external base
To form a step, the emitter by ion implantation into the intrinsic in the base to
The method of manufacturing a semiconductor device characterized by having a that step. 2. The method according to claim 1, wherein said collector drawer is connected to said embedded collector.
The method of manufacturing a semiconductor device according to claim 1, characterized in that you are directly reaching data area. 3. The collector drawer and the external base,
2. The method according to claim 1, wherein the heat treatment is performed simultaneously by heat treatment.
3. A method for manufacturing a semiconductor device according to item 2. 4. An opposite conductivity type second surface on the intrinsic base main surface.
Polycrystalline silicon is grown, etched back and heat treated
Claim 1 or 2, characterized in that to form the Ri emitter
13. The method for manufacturing a semiconductor device according to item 5. 5. An insulating film is grown on the main surface of the semiconductor device,
An aperture window that can be selectively used as an emitter, base and collector
And the emitter electrode, base electrode, and collector electrode
The process of claim 3 or the semiconductor device according to 4, characterized in that the formation.