JP3134898B2 - Semiconductor storage device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure of a MIS type gain cell in which the cell itself has an amplifying function and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a gain cell in which a cell of a semiconductor memory device itself has an amplifying action, there is one disclosed in "Nikkei Electronics", October 7, 1985, P255-P274. A polycrystalline silicon transistor is connected to a polycrystalline silicon floating gate of an EPROM. FIG. 8 shows the basic structure of this type of cell, and FIG. 9 shows its electrical equivalent circuit.

A gain cell has two transistors 1, 2
And one capacitor C1. _{One of} the transistors (transistor 1) is formed as a polycrystalline silicon transistor on an oxide film in order to reduce the area of the cell. This transistor 1 is connected to the gate electrode (signal charge storage region) of the other sensing transistor 2 and is used for writing data from the write bit line 4.

As bit lines and word lines, a read bit line 5, a write word line 6, and a read word line 7 are provided in addition to the write bit line 4. The detailed operation of the gain cell will be described with reference to FIG. In this example, each of the transistors 1 and 2 is formed of an n-channel MOSFET. In consideration of the threshold voltage of the polycrystalline transistor 1 serving as a writing transistor, the drive voltage of the write word line 6 is
Is higher than the voltage.

[0005] The degree of capacitive coupling depends on the above-mentioned capacitor C _1.
And the capacitance ratio of the gate oxide film capacitance C ₂ of the sense transistor 2. FIG. 10 shows a case where the capacity ratio is 3: 2. FIG. 10A shows the conditions of the applied voltage when "1" is written. 5V to the read word line 7,
When 7V is applied to the write word line 6 and 5V to the write bit line 4, the signal charge accumulation region (the sense transistor 2
Potential of the gate electrode) becomes 5V.

When the word lines 6, 7 and the bit line 4 all fall to 0 V during standby, the potential of the signal charge storage region becomes 2
V (FIG. 10B). If the threshold value of the sensing transistor 2 is set to 2 V or more, no current flows during standby. FIG. 10 (c) shows an application condition when "0" is written.
Is shown in When 5V is applied to the read word line 7, 7V to the write word line 6, and 0V to the write bit line 4, the potential of the signal charge storage region becomes 0V.

During standby, the word lines 7 and 6 and the bit lines 4
Are all reduced to 0 V, the potential of the signal charge storage region becomes-
The voltage drops to 3V (FIG. 10D). If the threshold voltage of the write transistor (polycrystalline silicon transistor 1) is 3 V or less, this transistor 1 is turned on, and a small amount of signal charge is lost. For this reason, at the time of reading, the potential of the signal charge storage region is slightly higher than 0 V, but if the potential is lower than the threshold voltage of the sense transistor 2, the sense transistor 2 remains off and no current flows.

In the case of reading, 5 V is applied to the read word line 7 while the write bit line 4 and the write word line 6 are kept at 0 V. At this time, in the "1" state, the sensing transistor 2 is turned on, and in the "0" state, the sensing transistor 2 is turned off.
Or “0”).

However, in the gain cell having such a structure, the two transistors 1 and 2 are arranged in a plane, and the word line and the bit line also need to be used for reading and writing. Was unsuitable for doing so.

In order to solve such a problem, the present inventors have proposed a new configuration of a gain cell as disclosed in Japanese Patent Laid-Open Publication No. Hei.
No. 255269. The gain cell disclosed in this publication is one in which a read word line and a write word line are shared, and a polycrystalline transistor is formed on a sense transistor so as to surround the word line. Are more suitable for miniaturization. However, the gain cell having such a configuration also has a technical problem described below.

[0011]

That is, since the gain cells disclosed in the above-mentioned documents and the publications use polycrystalline transistors, the driving current is small, the leakage current is large, and the writing time is long. There is a problem that the charge retention time is short. In addition, there is a problem that a manufacturing process is complicated to form a polycrystalline transistor.

SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and an object of the present invention is to eliminate the use of polycrystalline transistors, thereby shortening the time for writing and erasing. It is an object of the present invention to provide a semiconductor device capable of improving a charge retention time and a method for manufacturing the same.

[0013]

In order to achieve the above object, the present invention provides a semiconductor device comprising a gain cell having a MIS structure, comprising a source formed on a silicon semiconductor substrate and a pair of pn junctions, Two channel regions having different threshold values are formed adjacent to each other on a semiconductor substrate, and one of the channel regions having a larger absolute value of the threshold value is used as a write channel region, and one of the pn junctions is connected to the write channel region. And the other of the pn junctions is positioned in the read channel region, with the smaller of the absolute values of the threshold values being the read channel region.

In the method of manufacturing a semiconductor device, a step of forming an element isolation film and an insulating film obtained by reducing the thickness of the element isolation film on a silicon semiconductor substrate, and forming two channel regions having different threshold values adjacent to each other; An upper surface and an end surface are covered with a first insulating film on the element isolation film and the insulating film to form a first read / write common word line located in a larger absolute value of a threshold value in the channel region. Forming a pn junction in a portion where the threshold value is large through a through hole formed in the first read / write common word line; and forming a pn junction portion in the channel region having a smaller absolute value of the threshold value. Forming a signal charge storage region in which one end side is located and the other end side is extended on the first insulating film, and which is connected to the insulating film via the through hole at the extension; A step of forming a second insulating film covering the upper surface and the end surface of the signal charge storage region, and provided on the second insulating film and connected to the first read / write common word line via a through hole. The second read,
Forming a write common word line; and forming a source and a drain on the silicon semiconductor substrate.

In the method of manufacturing a semiconductor device, before forming the first read / write common word line, a charge film covering a part of the element isolation film and the insulating film is formed. Two channel regions having different threshold values can be formed adjacent to each other.

[0016]

According to the semiconductor memory device and the method of manufacturing the same described above, a gain cell can be formed without using a polycrystalline transistor, as will be apparent from the description of an electric equivalent circuit described later.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 1 and 2 show one embodiment of a semiconductor memory device according to the present invention. In the semiconductor memory device shown in FIG. 1, an active region 12 is formed by forming a field oxide film 11 (element isolation film) on a silicon semiconductor substrate 10, and a source 13 formed in the active region 12 and a first pn. It has a junction (drain) 14 and a second pn junction 15.

In this embodiment, a thin portion (insulating film 16) of the element isolation film formed in the active region 12 functions as a gate film of the transistor. In this embodiment, for example, the insulating film 1 is formed on the silicon semiconductor substrate 10.
For example, by partially changing the thickness of the film 6 and the impurity concentration thereunder, two channel regions having different threshold values are formed, and one of these channel regions having the larger absolute value of the threshold value is defined as the write channel region 17. , The one with the smaller absolute value of the threshold value is defined as the read channel region 18.

The source 13 has an inverted L-shape in plan view over the write channel region 17 and the read channel region 18, and is connected to the write bit line 19 via a contact 20. I have. The drain 14
Are formed in a substantially rectangular shape at a predetermined interval from the source 13 in the read channel region 18, and are connected to the read bit line 21 via the contact 22.
The pn junction 15 is formed at a predetermined distance from the source 13 so as to be located in the write channel region 17.

On the other hand, a first read / write common word line 23 is provided on the write channel region 17 of the insulating film 16. A signal charge storage region 24 is provided on the read channel region 18 of the insulating film 16 in contact therewith, and the signal charge storage region 24 is formed of a first insulating film 25.
And extends over the first read / write common word line 23 with the interposition of. Further, the signal charge storage region 24
Is a contact 26 penetrating the first read / write common word line 23 in the write channel region 17.
Is connected to the pn junction 15.

The contact 26 and the first read / write common word line 23 are separated by a first insulating film 25 as shown by a broken line in FIG. Also,
On the upper surface side of the signal charge storage region 24, a second insulating film 27
Is formed, and a second read / write common word line 28 is formed above the insulating film 27. This second read / write common word line 28 is
9 is connected to the first read / write common word line 23. The portion indicated by reference numeral 30 shown in FIG. 2 is an interlayer insulating film.

In the gain cell having the above structure, the sense transistor 32 of the electrical equivalent circuit shown in FIG. 3 is formed by the source 13 and the drain (first pn junction) 14 and The write transistor 31 is formed at the portion with the second pn junction 15. The capacitor C ₁ is formed at a portion sandwiched between the signal charge storage region 24 and the second read / write common word line 28, and the capacitor C ₂ is formed between the charge storage region 24 and the silicon semiconductor substrate 10. Formed in the part where it is located. Further, the signal charge accumulation region 24 is provided between the gate and the capacitor C ₁ of the drain and the sensing transistor 32 of the write transistor 31.

Table 1 shows an example of the applied voltage conditions at the time of "1" writing and "0" writing and reading of the gain cell of the present invention for the n-channel MOSFET type.

[0024]

[Table 1]

FIGS. 4 and 5 show an example of the operation of the gain cell under the application conditions in Table 1 using an equivalent circuit.
In the case of the p-channel MOSFET type, the operation can be performed in the same manner as the n-channel MOSFET type by reversing the signs of the threshold voltage and the applied voltage condition of the writing transistor 31 and the sensing transistor 32.

Next, as an example of the operation, the capacitor C ₁
The capacitance ratio of the capacitor C ₂ is an insulating film capacitance of the sense transistor 32 is 1: 2, the threshold voltage of the write transistor 31 and the sense transistor 32 is 8V, respectively, for the case of 0.7V will be described.

First, writing, standby, and reading of "1" will be described with reference to FIG. FIG. 5A shows the potential state of each part in the "1" write state, in which 12 V is applied to the read / write common word lines 23 and 28, and the write bit line 1 is applied.
When 5 V is applied to 9 and 5 V is applied to the read bit line 21, the writing transistor 31 is turned on, and the potential of the signal charge storage region 24 becomes 4 V.

At this time, the sense transistor 32 is off, and no current flows through the read bit line 21. FIG. 4B shows the potential state during standby. When the read and write common word lines 23 and 28 are set to 0V,
The signal charge storage region 24 also becomes 0 V, the sense transistor 32 does not turn on, and no current flows through the read bit line 21.

FIG. 4C shows the state of the potential at the time of reading. When 5 V is applied to the read / write common word lines 23 and 28 and the write bit line 19, the signal charge storage region 24 becomes 1.7 V. become. Since the threshold voltage of the sense transistor 32 is 0.7 V, the sense transistor 32 is turned on, and the voltage obtained by subtracting the threshold voltage of the sense transistor 32 from the voltage of the signal charge accumulation region 24, that is, 1 V is the read bit line 21. Is output to

Next, writing, waiting, and reading of "0" will be described with reference to FIG. FIG. 7A shows the potential state of each part in the "0" write state, where 12 V is applied to the read / write common word lines 23 and 28, and the write bit line 1 is applied.
When 0V is applied to 9 and 0V is applied to the read bit line 21, the writing transistor 31 is turned on, and the potential of the signal charge storage region 24 becomes 0V.

FIG. 5B shows a potential state during standby. When the read / write common word lines 23 and 28 are set to 0 V, a potential of -4 V appears in the signal charge storage region 24. At this potential, the sense transistor 32 is off, and no current flows through the read bit line 21.

FIG. 5C shows the state of the potential at the time of reading. When 5 V is applied to the read / write common word lines 23 and 28 and the write bit line 19, the signal charge storage region 24 becomes -2. 3V, and the sense transistor 32
Remains off. Also, common word line 2
The potential difference between 3, 28 and the signal charge storage region 24 is 7.3 V
Since the threshold voltage of the writing transistor 31 is lower than 8 V, the writing transistor 31 is not turned on, and the potential of the signal charge accumulation region 24 is held.

Therefore, only when reading is performed after the writing of "1", the sensing transistor 32 is turned on, a positive potential appears on the read bit line 21, and "1" and "0" are determined by this potential state. "Can be determined.

The above-described gain cell is manufactured by the steps shown in FIG. In the manufacturing method shown in the figure, the element isolation film not only functions as an element isolation but also functions as a gate insulating film of a transistor and also functions to change a threshold value of a channel region.

In the manufacturing process, first, as shown in FIG. 6A, a 30 to 300 nm element isolation film, for example, a field oxide film 11 for LOCOS isolation, is formed on a silicon semiconductor substrate 10.
And an insulating film 16 of 10 to 30 nm is formed. Then, 100
After depositing a polysilicon film of about 400 nm by LPCVD or the like, phosphorus is diffused in a POCl ₃ atmosphere, or an n-type dopant such as phosphorus or arsenic is implanted by ion implantation to form an n-type polysilicon film. Polysilicon is formed, and an insulating film of 100 to 400 nm is deposited thereon by CVD or the like (FIG. 6B).

Next, these films are patterned,
A first read / write common word line 23 and a first insulating film 25 are formed, and a through hole for a contact 26 for connecting the signal charge storage region 24 and the second pn junction 15 to the common word line 23 is formed. Form a hole. And after this,
A sidewall insulating film 25a is formed on the inner surface of the through hole by depositing a CVD insulating film and anisotropic etching (FIG. 6C).

Next, a portion other than the portion of the through hole for the contact 26 is covered with a resist, an n-type dopant is implanted through the hole by ion implantation to form a second pn junction 15, and then the resist is removed. Then, the same processing as the formation of the polysilicon film shown in FIG. 2B is performed, a polysilicon film of 100 to 400 nm containing an n-type dopant is deposited, and then the patterning is performed to form the signal charge storage region 24. . Thereafter, the signal charge storage region 24 has a thickness of 10 to 30 nm.
Is formed, and a through hole 29 is formed in a part of the insulating film 25 (FIG. 6D).

Next, a polysilicon film containing an n-type dopant is deposited and patterned to form a second read / write common word line 28 (FIG. 6).
(E)). Thereafter, an n-type dopant is ion-implanted, and a heat treatment for activating the dopant is performed to form the source 13 and the drain 14. Then, the interlayer insulating film 3
The gain cell is completed by forming 0, write bit line 19, and read bit line 21.

In this manufacturing method, the lower portion of the insulating film 16 becomes the read channel region 18 and the field oxide film 11
Is a writing channel region 17. The threshold voltage of the writing transistor 31 is controlled to an optimum value by changing the thickness of the field oxide film 11 or the concentration of the substrate 10 below the oxide film.

FIG. 7 shows another embodiment of the manufacturing method of the present invention.

In this embodiment, the charged film 40 is formed between the first read / write common word line 23 and the insulating film 16 and charges are retained in the charged film 40 so that the lower portion of the charged film 40 is formed. Control the threshold voltage of the channel region. In the manufacturing method shown in the figure, first, as shown in (a), a field oxide film 11 and an insulating film 16 are formed on a silicon semiconductor substrate 10 as in the above embodiment.

Next, a charged film 40 and an insulating film 41 of 5 to 30 nm are deposited. As the charging film 40 in this case,
Although a polysilicon or nitride film is used, when a Si nitride film is used, the insulating film 41 may not be provided. In the subsequent manufacturing steps, the same processing as in (b) to (f) shown in FIG. 6 is performed, and as a result, a gain cell having the structure shown in FIG. 7 (d) is obtained.

In the gain cell obtained by this manufacturing method,
The lower portion of the charging film 40 is the writing channel region 17,
The lower part of the signal charge storage region 24 is the read channel region 1
It becomes 8. In this case, it is of course possible to make the lower part of the charging film 40 the read channel region 18 and the other part the write channel region 17. In this embodiment, the threshold voltage of the writing transistor 31 is determined by the charge amount of the charging film 40.

The condition of the applied voltage for injecting carriers into the charging film 40 to hold the charge is as follows.
In the case of the FET type, the write / read common word line 23,
28, the read bit line 21 and the write bit line 19 are opened, and -10 V is applied to the substrate 10. In this case, Vt of the writing transistor 31 is 8
V and Vt of the sense transistor 32 are set to 0.7V.

Also for the p-channel MOSFET type, the write transistor 31 and the sense transistor 3
If the signs of the threshold voltage and the applied voltage of 2 are reversed, carriers can be injected into the charged film 40 similarly to the n-channel MOSFET.

Therefore, under this applied voltage condition, the potential difference between the write / read common word line 23 and the substrate 10 is 22 V
Then, electrons are injected into the signal charge storage region 24 from the substrate 10 side. At that time, the charge is captured by the charging film 40,
The threshold voltage of the writing transistor 31 fluctuates, and the optimal threshold voltage is selected by changing the charge amount of the charging film 40.

[0047]

As described above in detail in the embodiments,
According to the semiconductor memory device and the method of manufacturing the same according to the present invention, since a gain cell can be obtained without using a polycrystalline transistor, writing and erasing times can be reduced, and the charge retention time can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is an electrical equivalent circuit of the semiconductor memory device of FIGS.

FIG. 4 is an operation explanatory diagram of the semiconductor memory device of FIGS. 1 and 2;

FIG. 5 is an operation explanatory diagram of the semiconductor memory device of FIGS. 1 and 2;

FIG. 6 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention in the order of steps.

FIG. 7 is a sectional view illustrating a second embodiment of the method of manufacturing the semiconductor memory device according to the present invention in the order of steps.

FIG. 8 is a plan view and a sectional view of a basic structure of a conventional gain cell.

FIG. 9 is an electrical equivalent circuit of a conventional gain cell.

FIG. 10 is a diagram illustrating the operation of a conventional gain cell.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 silicon semiconductor substrate 13 source 14 drain (first pn junction) 15 second pn junction 17 write channel region 18 read channel region 24 signal charge storage region 31 write transistor 32 sense transistor 32

Continuation of front page (72) Inventor Tomoki Shigenobu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-5-226667 (JP, A) JP-A-3-3 58388 (JP, A) JP-A-1-255269 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A semiconductor device comprising a gain cell having a MIS structure, comprising: a source formed on a silicon semiconductor substrate; and a pair of pn junctions, wherein two channel regions having different thresholds are adjacent to the semiconductor substrate. Forming one of the pn junctions in the channel region for writing, with the larger absolute value of the threshold value being a channel region for writing, and setting the absolute value of the threshold value of the channel region in the channel region. A semiconductor memory device, wherein the smaller one is a read channel region, and the other of the pn junctions is located in the read channel region. 2. A method for manufacturing a semiconductor device comprising a gain cell having a MIS structure, comprising: forming an element isolation film and an insulating film on a silicon semiconductor substrate; and forming two channel regions having different threshold values adjacent to each other; Forming a first read / write common word line having an upper surface and an end surface covered with a first insulating film on the element isolation film and the insulating film, and located in the channel region having a larger absolute value of a threshold value; Forming a pn junction at a portion where the threshold value is large through a through hole formed in the first read / write common word line; Forming a signal charge storage region located at the other end and extending on the first insulating film and connected to the insulating film via the through hole at the extension. Forming a second insulating film covering the upper surface and the end surface of the signal charge storage region; provided on the second insulating film and connected to the first read / write common word line via a through hole; Second
Forming a common word line for reading and writing of the semiconductor memory device; and forming a source and a drain on the silicon semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: forming a charged film covering a part of the element isolation film and the insulating film before forming the first read / write common word line. A method for manufacturing a semiconductor memory device.