JP3136045B2 - Memory cell transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor suitable for forming a nonvolatile memory cell.

[0002]

2. Description of the Related Art Conventionally, nonvolatile memory cell transistors having various structures have been proposed.
EE TRANSACTIONS ON ULTRASONICS, FERROELECTRICS, AND
FREQUENCY CONTROL VOL.38, NO.6, p663-671 NOVEMBER
1991, Reference 2: JP-A-52-42381).

FIG. 6 is a sectional view schematically showing the structure of a memory cell transistor disclosed in Document 1. The memory cell transistor shown in FIG. 1 is a MOSFET, and includes a channel, source and drain regions 12, 14 and 16 provided on a substrate 10, and a gate insulating film 18 and a gate electrode 20 provided sequentially on the channel region 12. Have. The gate insulating film 18 is made of a ferroelectric.

In this memory cell transistor,
Polarization P _r of the gate insulating film 18 by positive or negative, the threshold voltage V _th is changed by ± P _r / C _OX, thus storing information by utilizing this. Here, if the thickness and the dielectric constant of the gate insulating film 18 are expressed as d and ε _OX , respectively, it can be written as C _OX = ε _OX / d.

When BaMgF ₄ is used as the gate insulating film 18, ε _OX ≒ 10ε ₀ (ε ₀ is a dielectric constant of vacuum), and the anti-electric field E _C ≒ 160 K generated between both ends of the gate insulating film 18.
V / cm, polarization P _r ≒ 1 μC / cm ² , and the film thickness d =
If _{250nm, P r / C OX =} 25V by the threshold voltage V _th is changed. Also, E _C · to invert the polarization P _r
A voltage of d れ ば 4 V may be applied.

FIG. 7 is a sectional view schematically showing the structure of the memory cell transistor disclosed in Reference 2. The memory cell transistor shown in FIG. 1 is a MOSFET, and includes a channel, source and drain regions 12, 14 and 16 provided on a substrate 10, a first gate insulating film 22 provided sequentially on the channel region 12, and a floating gate. Electrode 24,
It has a second gate insulating film 26 and a control gate electrode 28. The first gate insulating film 22 is made of a paraelectric, and the second gate insulating film 26 is made of a ferroelectric.

Here, the floating gate electrode 24 and the substrate 10
C ₁ a capacitance between the capacitance C _2, the residual polarization of the P _r of the second gate insulating film 22, the induced charges on the substrate 10 Q _S between the floating gate electrode 24 and the control gate electrode 28 Then, the gate voltage V _g of the memory cell transistor can be expressed by the following equation (2).

[0008] reversing the polarization P _r of _{V g = Q S / {(} C 1 · C 2) / (C 1 + C 2)} + P r / C 1 ...... (2) Thus the second gate insulating film 26 As a result, the threshold voltage V _th changes by 2 · P _r / C ₁ , and information can be stored by using this.

[0009]

In [0006] However the conventional memory cell transistor described above, when changing the threshold voltage V _th for writing or erasing information, double gate electrode the charge of at least the polarization P _r 20 , 28 or withdrawn from the gate electrodes 20, 28. More specifically, the polarization P _r of the ferroelectric used for the gate insulating film 18, 26 is usually 1~10μC / cm ^2, this value is induced when the channel region 12 becomes conductive charge Is about 10 to 100 times the value of about 0.1 μC / cm ² . Therefore, in order to change the threshold voltage V _th , it is necessary to supply a large amount of charge to the gate electrodes 20 and 28 or to remove the charge from the gate electrodes 20 and 28, which is a factor that hinders high-speed writing and erasing of information. I was

In the above-mentioned conventional memory cell transistor, the threshold voltage _Vth is limited to a value determined by design conditions such as dimensions and materials. Therefore, the threshold voltage _Vth is set to a value other than the value determined by these design conditions. V _th could not be variably controlled.

A first object of the present invention is to solve the above-mentioned conventional problems and to provide a memory cell transistor capable of writing and / or erasing information at a higher speed.

A second object of the present invention is to solve the above-mentioned conventional problems and to provide a memory cell transistor capable of expanding the range in which the value of the threshold voltage _Vth can be variably controlled.

[0013]

To achieve the first object, a memory cell transistor according to a first aspect of the present invention comprises a channel, source and drain regions provided on a substrate, and a first gate insulating film on the channel region. A floating gate electrode provided on the floating gate electrode, a control gate electrode provided on the floating gate electrode via a second gate insulating film, the second gate insulating film, the floating gate electrode, and the control gate electrode. a memory cell transistors comprising each comprise a barrier layer between the, the opposing area S ₁ of the channel region facing portion and a ferroelectric polarization region including the second gate insulating film of the floating gate electrode, the floating characterized by comprising narrower than the channel region facing area S ₀ of the gate electrode.

In order to further achieve the second object, a memory cell transistor according to a second aspect of the present invention is provided with a channel, source and drain regions provided on a substrate, and a first gate insulating film provided on the channel region. A floating gate electrode, and a control gate electrode provided on the floating gate electrode with a second gate insulating film interposed therebetween and having first and second electrode members to which voltages having different polarities are applied. A memory cell transistor, wherein a ferroelectric polarization region included in a second gate insulating film is provided in regions corresponding to the first and second electrode members, respectively.

[0015]

According to the first aspect of the present invention, the facing area S ₁ between the portion of the floating gate electrode facing the channel region and the ferroelectric polarization region included in the second gate insulating film is reduced by the area of the portion of the floating gate electrode facing the channel region. Make it narrower than S ₀ . For this reason, the amount of charge supplied to the control gate electrode for inverting the polarization of the second gate insulating film or the amount of charge extracted from the control gate electrode can be reduced as compared with the conventional case.

According to the second invention, the control gate electrode is constituted by the first and second electrode members to which voltages having different polarities are applied. Moreover, ferroelectric polarization regions included in the second gate insulating film are provided in regions corresponding to the first and second electrode members, respectively. Therefore, the polarization P _r1 in the region corresponding to the first electrode member and the polarization P _r2 in the region corresponding to the second electrode member can be individually controlled via the first and second electrode members.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. The drawings are only schematically shown to the extent that the invention can be understood, and thus the invention is not limited to the illustrated examples.

FIGS. 1 and 2 are a sectional view and a plan view schematically showing the structure of the memory cell transistor of the first embodiment. FIG. 2 shows a plan view in which the floating gate electrode 42, the second gate insulating film 44, and the control gate electrode 46 are partially cut away and viewed from the normal direction H of the substrate surface 32a. FIG. 1 is a sectional view taken along the line II of FIG. The first embodiment will be described as an embodiment of the first invention.

The memory cell transistor 30 of this embodiment
A channel, source and drain regions 34, 36 and 38 provided on the substrate 32, a floating gate electrode 42 provided on the channel region 34 via the first gate insulating film 40, And a control gate electrode 46 provided via a second gate insulating film 44. Further, the second gate insulating film 44 and the floating gate electrode 4
A barrier layer 54 is provided between the control gate electrode 2 and the control gate electrode 46. When the ferroelectric substance 50 included in the second gate insulating film 44 is in direct contact with the floating gate electrode 42 and the control gate electrode 46, the ferroelectric substance 50, the floating gate electrode 42 and the control gate electrode 46 It is also conceivable that a chemical reaction occurs between the two, and as a result, the ferroelectric substance 50 deteriorates. The barrier layer 54 is for preventing this chemical reaction. Therefore, it is sufficient that the barrier layer 54 is provided at least between the ferroelectric 50 and the floating gate electrode 42 and the control gate electrode 46. Ferroelectric 50 and floating gate electrode 42
Preferably, the barrier layer 54 is formed of a material that does not easily cause a chemical reaction with the control gate electrode 46, for example, SiO ₂ . When the barrier layer 54 is formed of a dielectric, the barrier layer 54 also functions as a second gate insulating film. Further, the area S ₁ between the channel region facing portion 42 a of the floating gate electrode 42 and the ferroelectric polarization region 48 included in the second gate insulating film 44 is reduced by the area S ₀ of the channel region facing portion 42 a of the floating gate electrode 42. Narrower than that.

The second gate insulating film 44 includes at least a ferroelectric substance 50 and, when viewed from the arrangement direction of the floating gate electrode 42 and the control gate electrode 46, the floating gate electrode 4
2. The region of the ferroelectric 50 where all three of the ferroelectric 50 and the control gate electrode 46 overlap is the polarization region 48. Therefore, by changing the shape and relative positional relationship of the floating gate electrode 42, the ferroelectric substance 50 or the control gate electrode 46,
By changing the shape of these three overlapping regions, the area of the polarization region 48 changes, so that the facing area S ₁
Can be changed.

The floating gate electrode 42 and the channel region 3
4 is the area S ₀ of the channel region facing portion 42 a of the floating gate electrode 42. The channel region 34 is a surface layer portion of the substrate between the source region 36 and the drain region 38, and is a region where a channel (passage of carriers) is induced.

In this embodiment, the memory cell transistor 30 is an n-channel MOSFET (Metal-Oxide-Semicond
uctor Field Effect Transistor) and p-Si
An n-type impurity is selectively introduced into the substrate 32 by ion implantation, impurity diffusion, or the like, thereby forming the p-Si channel region 34, the n ⁺ -Si source region 36, and the n ⁺ -Si drain region 38 into one substrate. It is formed on the surface 32a side. The source region 36 and the drain region 38 are
And is adjacent to the channel region 34.

Then, the first gate insulating film 40, the floating gate electrode 42, the second gate insulating film 44, and the control gate electrode 46 are overlapped in a plan view (when viewed from the normal direction H of the substrate surface 32a). They are sequentially provided on the channel region 34 so as to match. The planar shapes of the gate insulating films 40 and 44 and the gate electrodes 42 and 46 are the same shape, for example, a stripe shape elongated in the channel width direction P.

The floating gate electrode 42 is made of n ⁺ -poly Si or Pt. The floating gate electrode 42 is connected to the channel adjacent end 36 of the source region 36 in the channel length direction Q.
a and the drain region 38 so as to extend so as to overlap with the channel adjacent end 38a. The first gate insulating film 40 is made of a paraelectric material such as SiO ₂ , and has a floating gate electrode 42, a channel region 34, and a channel adjacent end 36.
The first gate insulating film 40 is interposed between the first gate insulating film 40 and the first gate insulating film 36b.

The second gate insulating film 44 comprises a ferroelectric substance 50 and a paraelectric substance 52. Both the ferroelectric substance 50 and the paraelectric substance 52 are interposed between the floating gate electrode 42 and the control gate electrode 46. Let it. Here, the ferroelectric substance 50 is P
The ZT and paraelectric 52 are made of SiO _2, and each of the dielectrics 50 and 52 has a striped shape elongated in the channel width direction P. The ferroelectric substance 50 is disposed substantially at the center in the channel length direction Q, and the paraelectric substance 52 is provided in contact with the left and right sides of the ferroelectric substance 50 in the channel length direction Q, respectively.

The control gate electrode 46 is made of n ⁺ -poly Si or Pt.
2, the whole of the second gate insulating film 44, that is, the whole of the ferroelectric 50 and the paraelectric 52 is sandwiched.

FIG. 3 is a plan view for explaining the areas S ₀ and S ₁ of the first embodiment. In the figure, the channel, source and drain regions 34, 36 and 38, the channel region facing portion 42a of the floating gate electrode 42, the ferroelectric polarization region 48 and the ferroelectric 5
0 in a plane view (normal direction H of the substrate surface 32a).
From the point of view).

In this embodiment, the planar shape of the channel facing portion 42a of the floating gate electrode 42 is equal to the planar shape of the channel region 34. Therefore, the area S of the channel facing portion 42a is equal to S.
₀ is equal to the area of the channel region 34 when viewed in plan. This area S ₀ is the area of the part shown by hatching in FIG.

Further, since the entire ferroelectric substance 50 is sandwiched between the floating gate electrode 42 and the control gate electrode 46, the ferroelectric substance 50 is viewed from the arrangement direction of the floating gate electrode 42 and the control gate electrode 46, here, the normal direction H. The whole body 50 overlaps the floating gate electrode 42 and the control gate electrode 46. Therefore, the entire ferroelectric 50 becomes the polarization region 48. The polarization region 48 and the channel region facing portion 42 of the floating gate electrode 42
facing area S ₁ and a is the area of the portion indicated by hatching in the left oblique upward in FIG.

Here, by reducing the area of the ferroelectric 50 itself included in the second gate insulating film 44, for example, in the channel length direction Q, the width of the ferroelectric 50 is reduced to the width of the channel region facing portion 42a (or Is smaller than the channel length) so that the facing area S ₁ <the area S ₀ .

Therefore, in this embodiment, the floating gate electrode 4
The opposing area between the ferroelectric 50 itself is second channel region facing portion 42a and a second gate insulating film 44 includes, it is an opposing area S _1.

The gate voltage V _g of the memory cell transistor 28 of this embodiment constructed as described above can be expressed by the following equation (2).

V _g = Q _S / {(C ₁ · C ₂ ) / (C ₁ + C ₂ )} + (S ₁ / S ₀ ) · P _r / C ₁ (2) Q _s is the charge induced in the channel region 34, C ₁ is the capacitance between the channel region facing portion 42 a of the floating gate electrode 42 and the channel region 34, and C ₂ is the capacitance between the channel region facing portion 42 a of the floating gate electrode 42 and the control. capacitance between the gate electrode 46, P _r represents the polarization in the per unit area of polarized region 48.

The memory cell transistor 28 of this embodiment
The variation [Delta] V _T of the threshold voltage V _th in, expressed as based on the equation (2), the following equation (3).

ΔV _T = (S ₁ / S ₀ ) · (2 · P _r / C ₁ ) (3) Here, the substrate 32 is a p-Si substrate and forms the second gate insulating film 44. PZT film and Si film in which the ferroelectric material 50 and the paraelectric material
If made of O ₂ film, P _r = about 20 [mu] C / cm ^2,
C ₁ = 3.4 × 10 ⁻⁷ F / cm ² At this time
P _r / C ₁ = 118V.

The variable width [Delta] V _T of the threshold voltage V _th desired practical in conventional flash memory is, for example, 5V, thus the area ratio S ₁ / S ₀ 5 / 118-1 / 20 and the area to S ₁ And S ₀ , the threshold voltage variable width ΔV _T of the memory cell transistor 28 of this embodiment is designed.
Can be set to 5 V, for example.

[0037] By narrowing the opposing area S ₁ thus can be reduced to a practical value to the desired threshold voltage variable width [Delta] V _T. By narrowing the opposing area S ₁ addition,
Since the amount of charge supplied or extracted for inverting the polarization of the polarization region 48 can be reduced, information can be written and erased at a higher speed than in the prior art.

The capacitance C ₁ is the same as that of the second gate insulating film 44.
Since changes according to the film thickness d ₁ of the ferroelectric 50 constituting the, possible to control the variable width V _cr by strong thickness d ₁ of the dielectric 50 _(see FIG. 1). Further, the threshold voltage V _{th is set} to a variable width ΔV _T
Voltage to be applied across the ferroelectric 50 in order to only change (inversion voltage) V _cr is V _cr = 2 · E given by _C · d _1, thus the film thickness d ₁ of the magnitude of the reverse voltage V _cr Can be controlled by

Further, in this embodiment, since the second gate insulating film 44 is composed of the ferroelectric substance 50 and the paraelectric substance 52, the capacitance C ₂ of the equation (2) can be expressed as the following equation (4).

C ₂ = ε ₁ · S ₁ / d ₁ + ε ₂ · S ₂ / d ₂ (4) Here, ε ₁ is the dielectric constant of the ferroelectric 50 constituting the second gate insulating film 44. And the thickness, ε ₂ and d ₂ are the dielectric constant and the thickness of the paraelectric 52 constituting the second gate insulating film 44 (see FIG. 1 for the thickness d ₂ ), and S ₂ is The area of the floating gate electrode 42 facing the channel region facing portion 42a is shown. Note that S ₁ + S ₂ = S ₀ .

As described above, in order to make the threshold voltage variable width ΔV _T a practical value, it is necessary to set S ₁ / S ₀ << 1. In this case, equation (4) is approximately 5) It can be rewritten as in the equation.

[0042] From _{C 2 = ε 2 · S 2} / d 2 ...... (5) Therefore Equation (2) and (5), the gate voltage V _g required to obtain a channel charge Q _S a certain amount, Thickness d ₂
It can be understood that it can be controlled by Thus the gate voltage V _g to be applied in order to obtain a channel charge Q _S required for reading the information size (hereinafter, the read gate voltage V _g represents the voltage V _R), can be controlled by the film thickness d ₂ .

As described above, in this embodiment, the ferroelectric 5
The threshold voltage variable width ΔV _T or the inversion voltage V _cr is controlled by the film thickness d ₁ of 0, and the reading voltage V _R can be controlled by the film thickness d ₂ of the paraelectric material 52 almost independently of this. It is. Therefore, in addition to d ₁ = d ₂ , d ₁ > d ₂ or d ₁
It can be ₁ <d _2.

FIG. 4 is a sectional view schematically showing the structure of the second embodiment. This embodiment will be described as an embodiment of the first invention. Hereinafter, points different from the first embodiment will be described, and detailed description of the same points as the first embodiment will be omitted.

In this embodiment, the second gate insulating film 44
A barrier layer 54 is provided between the floating gate electrode 42 and the control gate electrode 46. If the ferroelectric 50 included in the second gate insulating film 44 and the gate electrodes 42 and 46 are in direct contact, a chemical reaction occurs between the ferroelectric 50 and the gate electrodes 42 and 46, As a result, the ferroelectric substance 50 may deteriorate. The barrier layer 54 is for preventing this chemical reaction. Therefore, it is sufficient that the barrier layer 54 is provided at least between the ferroelectric 50 and the gate electrodes 42 and 46. The barrier layer 54 is preferably formed of a material that does not easily cause a chemical reaction with the ferroelectric 50 and / or the gate electrodes 42 and 46, for example, SiO ₂ . When the barrier layer 54 is formed of a dielectric,
The barrier layer 54 also functions as a second gate insulating film.

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

[0058]

[0059]

[0060]

[0061]

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070]

[0071]

[0072]

[0073]

[0074]

FIGS. 4 and 5 are a sectional view and a plan view schematically showing the structure of the second embodiment. FIG. 5 is a plan view showing the floating gate electrode 42, the second gate insulating film 44, and the control gate electrode 46 partially cut away and viewed from the normal direction H of the substrate surface 32a. FIG. 4 is a sectional view taken along line XIII-XIII in FIG. This embodiment will be described as an embodiment of the second invention.

The memory cell transistor 30 of this embodiment
A channel, source and drain regions 34, 36 and 38 provided on the substrate 32, a floating gate electrode 42 provided on the channel region 34 via the first gate insulating film 40, A control gate electrode 46 provided via a second gate insulating film 44,
The control gate electrode 46 is divided into a first electrode member a1, a2, a3 and a second electrode member b to which voltages having different polarities are applied.
1 and b2, and the ferroelectric polarization region 48 included in the second gate insulating film is divided into the first electrode members a1 and a
2, a3 and the second electrode members b1, b2, respectively.

The second gate insulating film 44 includes at least a ferroelectric substance 50, and is formed of the floating gate electrode 42, the ferroelectric substance 50 and the control gate electrode 46 when viewed from the arrangement direction of the floating gate electrode 42 and the control gate electrode 46. The portion of the ferroelectric 50 in the region where all three overlap is the polarization region 48.

In this embodiment, the memory cell transistor 30 is an n-channel MOSFET (Metal-Oxide-Semicond
uctor Field Effect Transistor) and p-Si
An n-type impurity is selectively introduced into the substrate 32 by ion implantation, impurity diffusion, or the like, thereby forming the p-Si channel region 34, the n ⁺ -Si source region 36, and the n ⁺ -Si drain region 38 into one substrate. It is formed on the surface 32a side. The source region 36 and the drain region 38 are
And is adjacent to the channel region 34.

Then, the first gate insulating film 40, the floating gate electrode 42, the second gate insulating film 44, and the control gate electrode 46 are stacked in a plan view (as viewed from the normal direction H of the substrate surface 32a). They are sequentially provided on the channel region 34 so as to match. The planar shapes of the first gate insulating film 40, the floating gate electrode 42, and the second gate insulating film 44 have the same shape, for example, a stripe shape elongated in the channel width direction P.

The floating gate electrode 42 is made of n ⁺ -poly Si or Pt. The floating gate electrode 42 is connected to the channel adjacent end 36 of the source region 36 in the channel length direction Q.
a and the drain region 38 so as to extend so as to overlap with the channel adjacent end 38a. The first gate insulating film 40 is made of a paraelectric material such as SiO ₂ , and has a floating gate electrode 42, a channel region 34, and a channel adjacent end 36.
The first gate insulating film 40 is interposed between the first gate insulating film 40 and the first gate insulating film 36b.

The second gate insulating film 44 is made of only the ferroelectric material 50, and includes the floating gate electrode 42 and the control gate electrode 46.
The ferroelectric substance 50 is interposed between the respective electrode members a1 to a3 and b1 to b2. Accordingly, when viewed from the arrangement direction of the floating gate electrode 42 and the control gate electrode 46, here, the normal direction H, a polarization region 48 is formed in each of the ferroelectric bodies 50 in a region overlapping with each of the electrode members a1 to a3 and b1 to b2. Is done. The ferroelectric 50 is PZT.

Each of the electrode members a1 to a of the control gate electrode 46
3, b1 and b2 are each made of n ⁺ -poly Si or Pt, and each of the electrode members a1 to a3 and b1 to b2 is
The stripe shape is elongated in the channel width direction P.
The electrode members a1 to a3 and b1 to b2 are arranged in parallel at a predetermined interval in the channel length direction Q.
In this case, the first electrode members a1 to a
3 and the second electrodes b1 and b2 are alternately arranged. Note that the first and second electrode members need not necessarily be arranged alternately.

In the memory cell transistor 30 of this embodiment having the above-described structure, the first electrode member a1
A3 to apply a positive voltage to the second electrode members b1 to b2, or apply a negative voltage to the first electrode members a1 to a3 and a positive voltage to the second electrode members b1 to b2. Apply. Then, the magnitude of the voltage applied to each electrode member is adjusted to any suitable magnitude. The threshold voltage variable width V _cr of the memory cell transistor 30 is different from the polarization Pr 1 of the polarization region 48 corresponding to the first electrode members a1 to a3 and the polarization P _r1 of the polarization region 48 corresponding to the second electrode members b1 to b2, respectively. It changes according to the sum with the polarization _Pr2 . Therefore, each electrode member a1
To a3, by any suitably changing the magnitude of the polarity or voltage of the voltage applied to b1 and b2, the threshold voltage variation width [Delta] V _T can variably controlled, as a result, the threshold voltage V _th of the memory cell transistor 30 Can be variably controlled.

This embodiment is an embodiment of the second invention. However, if the number of the first and second electrode members constituting the control gate electrode 96 is reduced, the embodiment of the first invention will be described. Can also be expected.

For example, the control gate electrode 96 is composed of only the first electrode member a2 and the second electrode members b1 to b2 as the electrode members, and floats with the polarization region 48 corresponding to each of these electrode members a2, b1 and b2. The sum of the areas S ₁₁ , S ₁₂ and S ₁₃ of the gate electrode 42 facing the channel region facing portion 42a may be smaller than the area S ₀ of the channel region facing portion 42a. At this time, the facing areas S ₁₁ , S ₁₂ and S ₁₃
Are the areas of the portions indicated by hatching in FIG. In this case, similarly to the first embodiment, by setting S ₁ <S ₀ , the threshold voltage variable width ΔV _T
Can be reduced to a value practically desired. Further, by reducing S ₁ , it is possible to expect an operation and effect that information can be written and erased at a higher speed than before.
However, since the second gate insulating film 44 is formed only of the ferroelectric material 50, the threshold voltage variable width ΔV _T or the inversion voltage V _cr and the read voltage V _R cannot be independently controlled. This is different from the first embodiment.

The present invention is not limited only to the above-described embodiment, and accordingly, the shape, the number of the components, the location, the forming material, the dimensions, and the like of each component can be arbitrarily and suitably changed.

For example, in the second embodiment, as in the first embodiment, the second gate insulating film 44 and the floating gate electrode 42
And the control gate electrode 46, respectively.
4 may be provided.

The ferroelectric substance 50 may be interposed at least between the channel facing region 42a of the floating gate electrode 42 and the control gate electrode 46. Therefore, the ferroelectric substance 50 may be placed on the floating gate electrode 42 or the control gate electrode 46. Or may be provided only in a region corresponding to the channel facing region 42 a of the floating gate electrode 42.

In the above embodiment, the n-channel FE
Although the example of T has been described, a p-channel FET may be configured in each of the above-described embodiments by setting the conductivity type to the opposite conductivity type.

[0090]

As is apparent from the above description, the amount of charge supplied to the control gate electrode or the amount of charge extracted from the control gate electrode for inverting the polarization of the second gate insulating film can be reduced. Therefore, it is possible to provide a memory cell transistor capable of writing and erasing information at a higher speed than before.

According to the memory cell transistor of the second invention, the polarizations P _r1 and P _r2 of the regions corresponding to the respective electrode members are individually determined via the first and second electrode members constituting the control gate electrode. Can be controlled. Since the threshold voltage of the memory cell transistor changes according to the sum of these polarizations _Pr1 and _Pr2 , the threshold voltage of the memory transistor can be variably controlled via the first and second electrode members.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a configuration of a first embodiment.

FIG. 2 is a plan view schematically showing the configuration of the first embodiment.

FIG. 3 is a diagram for explaining areas S ₀ and S ₁ in the first embodiment.

FIG. 4 is a sectional view schematically showing a configuration of a second embodiment.

FIG. 5 is a plan view schematically showing a configuration of a second embodiment.

FIG. 6 is a cross-sectional view schematically showing a configuration of a conventional memory cell transistor.

FIG. 7 is a cross-sectional view schematically showing a configuration of a conventional memory cell transistor.

[Explanation of symbols]

 30: Memory cell transistor 32: Substrate 34: Channel region 36: Source region 38: Drain region 40: First gate insulating film 42: Floating gate electrode 42a: Channel region facing portion 44: Second gate insulating film 46: Control Gate electrode 48: Ferroelectric polarization region 50: Ferroelectric 52: Paraelectric 54: Barrier layer

Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/10 451 H01L 27/115 H01L 29 / 78 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] 1. A channel, source and drain regions provided on a substrate, a floating gate electrode provided on the channel region via a first gate insulating film, and a second gate provided on the floating gate electrode. A memory cell transistor comprising: a control gate electrode provided via an insulating film; and a barrier layer between the second gate insulating film, the floating gate electrode, and the control gate electrode. The facing area S between the channel region facing portion of the floating gate electrode and the ferroelectric polarization region included in the second gate insulating film
_1, the memory cell transistors, characterized by comprising narrower than the channel region facing area S ₀ of the floating gate electrode. 2. The memory cell transistor according to claim 1, wherein said barrier layer is made of an insulating film material. 3. The memory cell transistor according to claim 1, wherein said barrier layer is made of a dielectric material. 4. A channel, source and drain regions provided on a substrate, a floating gate electrode provided on the channel region via a first gate insulating film, and a second gate provided on the floating gate electrode. A control gate electrode provided with an insulating film and applied with voltages having different polarities from each other; and a control gate electrode including a second electrode member, wherein the second gate insulating film is A memory cell transistor, wherein ferroelectric polarization regions are provided in regions corresponding to the first and second electrode members, respectively. 5. The memory cell transistor according to claim 4, wherein said first electrode members and said second electrode members are alternately arranged. 6. The memory cell transistor according to claim 4, wherein a barrier layer is provided between said second gate insulating film, said floating gate electrode and said control gate electrode. . 7. The memory cell transistor according to claim 6, wherein said barrier layer is made of an insulating film material. 8. The memory cell transistor according to claim 6, wherein said barrier layer is made of a dielectric material.