JP3136674B2 - Effect adding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effect adding device,
More specifically, the present invention relates to an effect adding device including an analog effect adding circuit and a digital effect adding circuit.

[0002]

2. Description of the Related Art In a device for handling sounds such as an electronic stringed musical instrument (for example, a guitar), an electronic musical instrument such as an electronic organ and a synthesizer, and a musical sound output device for processing and outputting a sound generated by another sound source. An important issue is how to produce rich musical tones. As a means for producing such a rich sound, conventionally, an effect adding process of including many harmonic components in an electric signal of a sound generated by a sound source or the like has been performed. Conventionally, analog-type devices have been generally used as such effect adding devices, but recently, digital-type devices have become widespread with the development of electronic technology. This digital type effect adding apparatus generally uses a DSP (Digital Signal Processor),
By rewriting the microprogram in P, various effects (for example, reverb, delay, chorus, etc.) can be provided. Thus one DS
Since various effects can be given by P, digital effect adding devices have been rapidly used recently.

On the other hand, the analog type is used, for example, as a distortion circuit. In the distortion circuit, a diode is connected in both directions, and an excessive voltage input at a level higher than the threshold voltage is supplied to the diode connected in both directions, thereby distorting the input signal using the nonlinear characteristics of the diode. . In this analog type effect adding device, the input signal is distorted using the nonlinear characteristics of the analog element such as a diode used, so the output waveform varies slightly depending on the type and material of the analog element used. , The output sounds each have a distinctive tone. As described above, in the analog type effect adding device, the output sound largely depends on the non-linear characteristic of the analog element to be used, and even if it is attempted to simulate the digital type, the delicate non-linear characteristic curve is accurately expressed. There is a limit to this, and even now that the digital type has become widespread, the analog type effect adding circuit is strongly preferred. In the effect adding device,
It is rare to add only a single effect. For example, a plurality of effects such as delay, distortion, and chorus are often applied simultaneously. In such a case, in a digital effect adding device, particularly a device using a DSP, a plurality of effects can be easily added by serially executing a program list of each effect to be added as a DSP processing program. , Excellent usability.

However, recently, when a plurality of effects are added in order to generate a higher quality sound, a specific effect is realized by an analog type, and other effects are realized by a digital type. Is being done. As such a conventional effect adding device, there is a so-called multi-effect adding device in which a DSP for adding a digital effect and an analog effect adding circuit for adding an analog effect are physically connected in serial.

[0005]

However, in such a conventional effect adding device, particularly in a device capable of adding both analog and digital effects, an analog effect adding circuit and a digital The physical effect connection circuit is physically serially connected, so if multiple effects are to be added sequentially to obtain an output, the physical connection sequence between the analog effect addition circuit and the digital effect addition circuit In the relationship between the addition of the analog effect and the addition of the digital effect, there is a problem that the order of adding the effect cannot be easily changed. For example, a distortion process is performed by an analog effect adding circuit, another effect is added by a DSP, and the order of adding the effect added in the order of reverb → chorus → echo → distortion is changed to chorus → echo → distortion → reverb. To change it, prepare two DSPs, connect them serially in the order of DSP → analog effect adding circuit → DSP, perform chorus and echo effect adding processing with the first DSP, and then perform distortion processing with the analog effect adding circuit. Finally, it is necessary to perform reverb effect adding processing by the DSP. As described above, in the conventional effect adding device, when a plurality of effects are added by using an analog type and a digital type, the analog type effect adding circuit and the digital type effect adding circuit are physically serially connected. Therefore, when a plurality of effects are added, if the order of the effects is to be changed, it is necessary to change the order of the physical connection, and the order of the effects cannot be easily changed. There was a problem that the usability of the device was poor. Therefore, the present invention provides a simple and easy-to-change effect addition order when performing a plurality of effect additions without changing the physical connection between the digital effect addition circuit and the analog effect addition circuit. The purpose is to make it easy to do.

[0006]

According to the first aspect of the present invention,
To achieve the above purpose, input using analog elements
Analog effect adding means for performing an effect adding process on an audio signal, an area for storing an input audio signal, and the analog effect
Input memo having an area for storing the output signal of the adding means
Digital means and at least two types of effect adding processing
Digital effect adding means that can be applied by processing
And an area for storing a final output signal and the analog effect
An output memory means having an area for storing an input signal to the adding means, and an input stored in the input memory means
A sound signal and an output signal of the analog effect adding means, respectively.
About at least 2 of the digital effect adding means.
If you select which type of effect processing to apply
In addition, one of the at least two types of effect processing is performed.
Each output signal obtained is sent to the final output signal of the output memory means.
Area for storing the signal and input to the analog effect adding means.
Select which area to store the force signal in
It includes a signal selecting means for the. The analog effect adding means is, for example, a distortion circuit.

[0007]

According to the first and second aspects of the present invention,
In the effect adding circuit of the electronic stringed instrument, the input sound signal is
Record in the area for storing the input sound signal in the input memory means.
Remembered. In addition, an analog element is used for the input memory means.
Analog effect that applies effect processing to the input audio signal by using
It has an area for storing the output signal of the adding means. This
Each of the signals stored in each area of the
The digital effect adding means
Also becomes one of the input signals of the two types of effect addition processing?
Selected. And at least two types of effect processing
The two signals subjected to any of
Storing the final output signal of the output memory means by means of a stage
Stores the area and the input signal to the analog effect adding means
Supplied to any of the areas. As a result, signal selection
The input audio signal stored in the input memory
Signal and the analog effect added signal
How to supply for the Tal effect addition process, and
Each of the at least two types of digital effect addition processing is performed.
To store the final output signal of the output memory means.
The input signals to the rear and the analog effect adding means are stored.
By changing which of the areas to supply,
The connection order of the digital effect adding unit and the analog effect adding unit can be changed as appropriate without changing the physical connection relationship, and the processing order of the digital effect adding unit and the analog effect adding unit can be changed as appropriate. . As a result, the order of adding effects when a plurality of effects are added can be easily changed, and intended effects can be easily added.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described based on embodiments. 1 to 24 are diagrams showing an embodiment of the effect adding device of the present invention. FIG. 1 is a schematic configuration diagram of an electronic stringed instrument 1 to which the effect adding device of the present invention is applied. The electronic stringed instrument 1 includes a pickup 2, an operational amplifier 3, an electronic circuit unit 4, a tone control unit 5, a volume 6, and an output terminal. 7 and the like.

In the electronic stringed musical instrument 1, string pickup is detected by the pickup 2, and the string vibration detected by the pickup 2 is amplified by the operational amplifier 3 and input to the electronic circuit section 4 as an analog input sound signal. The electronic circuit unit 4 performs an effect adding process on the input acoustic signal of the string vibration, as described later, and outputs the resulting signal to the tone control unit 5 as an output signal. The output signal is tone-controlled by the tone control unit 5, the level of the output signal is adjusted by the volume 6, and then output via the output terminal 7.

The tone control unit 5 includes a capacitor 8
And a variable resistor 9. Tone control is performed by adjusting the variable resistor 9.

As shown in FIG. 2, the electronic circuit section 4 has an A / A
It includes D converters 11 and 12, a DSP (Digital Signal Processor) 13, D / A converters 14 and 15, a microcomputer 16, a distortion circuit 17, a console 18, and the like.

The DSP 13 has two input terminals Ei and Ai.
And two output terminals Wo and Ao, and as will be described later, effect processing is performed on the input signal by digital processing, or the final output signal is used as it is. DSP1
3, an input audio signal WIN from the A / D converter 11 is input to the input terminal Ei, and A / D is input to the input terminal Ai.
A signal from the D converter 12 is input. The DSP 13
The output signal is used as the final output signal via the output terminal Eo.
The signal is output to the D / A converter 15 via the output terminal Ao to the / A converter 14 or as an analog effect addition processing signal.

The D / A converter 15 converts the digital signal from the DSP 13 into an analog signal and outputs the analog signal to the distortion circuit 17 as an analog signal.

The distortion circuit (analog effect adding means) 17 includes a buffer 21, an amplifier circuit 22, a clip circuit 23, and an amplifier circuit 24, as shown in FIG.

An input signal input from the D / A converter 15 is input to an amplifier circuit 22 via a buffer 21, and the amplification factor of the buffer 21 is controlled by a signal (voltage V) input from the microcomputer 16. Is done. A clip position in a clip circuit 23 described later is adjusted by the amplification factor of the buffer 21.

The amplifying circuit 22 includes an operational amplifier OP1 and a resistor R1, amplifies an input signal from the buffer 21, and outputs the amplified signal to the clipping circuit 23.

The clipping circuit 23 is composed of two diodes D1 and D2 connected in parallel in two directions. The clipping circuit 23 clips the plus and minus levels of the signal input from the amplifying circuit 22 to the amplifying circuit 24. Output. That is, the plus level of the signal from the amplifier circuit 22 is clipped at the threshold level of the diode D2,
The negative level is clipped at the threshold level of the diode D1. The clipping circuit 23 clips the signal from the amplifying circuit 22 by the diodes D1 and D2 in this manner, distorts the waveform of the input signal, and outputs a signal having a distorted waveform to the amplifying circuit 24.

The amplifier circuit 24 is composed of resistors R2 and R3 and an operational amplifier OP2. The amplifier circuit 24 amplifies the distorted waveform signal from the clip circuit 23, and
Output to the D converter 12.

Referring again to FIG. 2, the A / D converter 12
The analog signal input from the distortion circuit 17 is converted into a digital signal, and converted into a digital signal by the DSP 13.
To the input terminal Ai.

On the other hand, a string vibration signal (analog input sound signal) detected by the pickup 2 is input to the A / D converter 11 via the operational amplifier 3, and the A / D converter 1
1 converts the analog input audio signal into a digital signal and outputs it to the DSP 13 as a digital input audio signal WIN.

The D / A converter 14 converts the final output signal from the DSP 12 into an analog signal, and outputs the analog output signal to the tone control unit 5 shown in FIG.

The microcomputer 16 has a CPU (Ce
ntral Processing Unit), ROM (Read Only Memory)
And a RAM (Random Access Memory), etc., and controls each unit of the electronic circuit unit 4 to execute processing as an effect adding device. That is, the microcomputer 15 stores a program as an effect circuit, other necessary data, coefficients, and the like in its ROM, and uses the RAM as a work area. Microcomputer 16
Transfers the program in the ROM to the DSP 13 and
It causes the SP 13 to perform an effect adding process or outputs the clip position adjustment signal (clip voltage: V) to the distortion circuit 17 to control the distortion process by the distortion circuit 17.

The console 18 includes various switches and volumes used when the electronic stringed musical instrument 1 is operated, and particularly includes a volume for adjusting the distortion level of the distortion circuit 17 and a mode selection switch to be described later.

The DSP 13 performs a plurality of types of effect adding processing, such as reverb, chorus, and delay. Which of these effect adding processes is to be performed and in which order these effect adding processes are to be performed are set by a microprogram, data and coefficients transferred from the microcomputer 16.

For example, when performing the chorus and delay processing in order, the DSP 13 forms a chorus processing section 30 and a delay processing section 40 as shown as pseudo processing blocks in FIG.

The chorus processing unit 30 includes a multiplier 31, an adder 32, a sign detection unit 33, and an ALU (Arithmetic and Log
ic unit) 34, an adder 35, a delay unit 36, and an adder 3
7, and the delay processing unit 40 includes a delay unit 41 and an adder 42.

The chorus processing unit 30 has a multiplier 31
Adder 32, sign detector 33, ALU 34, and adder 3
5, a delay unit 36 sequentially delays the input signal WINP based on the formed triangle wave, adds the delayed input signal WINP and the non-delayed input signal WINP, and outputs a chorus output as a chorus output. Output to That is, the multiplier 31 of the chorus processing unit 30 includes:
The sawtooth rate WLF1 and the sawtooth rate PRAT are input, and the multiplier 31 outputs the sawtooth rate WLF1 and the sawtooth rate PRAT.
And outputs the result to the adder 32. The sawtooth rate W CC0 is input to the adder 32, and the adder 32 subtracts the result of the multiplication by the multiplier 31 from the sawtooth rate W CC0 and outputs the result to the code detection unit 33. The sign detection unit 33 detects the sign of the subtraction result of the adder 32, and instructs the operation method in the ALU 34 based on the detection result. ALU34,
If the detection result by the sign detection unit 33 is positive, a constant WZRO, which is zero (0), is added to the previous calculation result and output.
If the detection result of the sign detection unit 33 is negative, the constant WZRO
Is subtracted from the previous calculation result and output. This ALU3
The calculation result of No. 4 is output to the adder 32 as the sawtooth wave rate WCC0, and also output to the adder 35, where "00" is added by the adder 35 and output to the delay unit 36 as a triangular wave.

On the other hand, the input signal WINP is input to the delay section 36. The delay section 36 delays the input signal WINP by a predetermined delay time T00 and delays the input signal WINP by a time based on a triangular wave. Then, it is output to the adder 37 as a chorus delay output WCC2. The input signal WINP is input to the adder 37.
The input signal WINP delayed by the delay unit 36 and the input signal WINP not delayed are added and output to the delay processing unit 40 as a chorus output WCC3.

The delay processing section 40 includes the chorus processing section 3
The chorus output WCC3 of 0 is output after being delayed by a predetermined time. That is, the chorus output W of the chorus processing unit 30
The CC3 is input to the delay unit 41 and the adder 42. The delay unit 41 delays the chorus output WCC3 by a predetermined time and outputs the result to the adder 42 as a delay delay output WDD0.
The adder 42 adds the chorus output WCC3 and the delay delay output WDD0, and outputs the addition result as a delay output WDD1.

When performing reverb as effect adding processing, the DSP 13 performs an all-pass filter 50, a comb filter α60, and a pseudo-circuit as shown in FIG.
A comb filter β70, a comb filter γ80, and a mixing processing unit 90 are formed.

The all-pass filter 50 includes an adder 51,
The input signal WINR and the output of the multiplier 53 are input to the adder 51. The adder 51 adds the input signal WINR and the result of the multiplication by the multiplier 53 to form a delay unit 55 and a multiplier 54.
Output to The delay unit 55 delays the addition result of the adder 51 for a predetermined time and outputs the result to the adder 52 and the multiplier 53,
The multiplier 53 is also supplied with an all-pass filter coefficient PALK. The multiplier 53 multiplies the output of the delay unit 55 by the all-pass filter coefficient PALK, and outputs the multiplication result to the adder 51. The all-pass filter coefficient PALL is input to the multiplier 54. The multiplier 54 multiplies the output of the adder 51 by the all-pass filter coefficient PALL and outputs the result to the adder 52. The adder 52 performs an addition process on the output of the delay unit 55 and the output of the multiplier 54, and outputs the addition result as an all-pass filter output WALM for each of the comb filters 60 and 7.
0 and 80 are output.

The comb filter α60 includes a multiplier 61, adders 62 and 63, and a delay unit 64. The output of the all-pass filter WALM is input to the adder 62. The output of the multiplier 61 is further input to the adder 62, and the adder 62 multiplies the output of the all-pass filter WALM by the output of the multiplier 61 to perform delay processing on the delay unit 64.
And to the adder 63. The delay unit 64 includes the adder 62
Is output to the multiplier 61 after being delayed for a predetermined time, and the addition result of the adder 62 is output to the adder 63 after being delayed for a predetermined time. The comb-shaped filtering coefficient PCOM is also input to the multiplier 61.
Represents a comb-shaped filtering coefficient P
COM is multiplied and output to the adder 62. Adder 63
Adds the output of the delay unit 64 to the addition result of the adder 62, and outputs the addition result to the mixing processing unit 90 as the comb filter α output WRV0.

The comb filter β70 is composed of a multiplier 71, adders 72 and 73, and a delay unit 74. The comb filter β70 performs processing in the same manner as the comb filter α60, and outputs the processing result as a comb filter β output WRV1 to the mixing processing unit 90. Output to

Further, the comb filter γ80 is
1. Composed of adders 82 and 83 and a delay unit 84, performs the same processing as that of the comb filter α60, and outputs the processing result to the mixing processing unit 90 as a comb filter γ output WRV2.

The mixing section 90 includes two adders 91 and 9
2 is comprised. The adder 91 has a comb filter α
The comb filter α output WRV0 from the comb filter 60 and the comb filter β output WRV1 from the comb filter β70 are input, and the adder 91 adds the comb filter α output WRV0 and the comb filter β output WRV1 to obtain an addition result. Output to the adder 92. The adder 92 further receives the comb filter γ output WRV2 from the comb filter γ80. The adder 92 adds the comb filter γ output WRV2 to the addition result of the adder 91, and reverbates the addition result. Output as output WRV3.

FIG. 6 is a specific circuit configuration diagram of the DSP 13. The DSP 13 includes a program memory 101, a control circuit 102, an input register (PI1) 103, an input register (PI2) 104, a coefficient memory (P) 105, a work memory (W) 106, and an output register (OR0) 10.
7, output register (OR1) 108, delay processing unit 20
0, a multiplication unit 300, an addition / subtraction unit 400, and the like.
Each part of the DSP 13 is connected by an internal bus 109.

The program memory 101 stores a program as an effect adding device.
The data is written from the microcomputer 16 shown in FIG. An address counter (not shown) is connected to the program memory 101.
Supplies the program contents to the control circuit 102 sequentially according to the address designation of the address counter.

The control circuit 102 includes the program memory 10
The effect adding process is executed by controlling each unit of the DSP 13 in accordance with the program in 1. The detailed processing contents will be described later. Further, the control circuit 102 receives a code flag F (AR) from an addition / subtraction unit 400 described later, and controls the processing of the addition / subtraction unit 400 and the multiplication unit 300 based on the code flag F (AR). I do.

The input register (PI0) 103 receives an input audio signal WIN from the A / D converter 11 via the input terminal Ei, and the input register (PI0) 103 temporarily stores the input audio signal WIN. After that, the internal bus 109
Is transferred to the work memory (W) 106 via the.

The input register (PI1) 104 receives a signal from the A / D converter 12 via an input terminal Ai. The input register (PI1) 104 temporarily stores the input signal, The data is transferred to the work memory (W) 106 via the link 109.

The coefficient memory (P) 105 is a register for storing various coefficients required for effect addition processing by the DSP 13. These various coefficients are stored in the ROM of the microcomputer 16 in FIG.
The microcomputer 16 reads out the coefficients from the ROM and writes them into the coefficient memory (P) 105. As coefficients set in the coefficient memory (P) 105, as shown in FIG. 7 as a memory map of the coefficient memory (P) 105,
The sawtooth rate PRAT is stored at the address 0 and the address 1
, The all-pass filter coefficient PALL is set at the address 2, and the comb-shaped filtering coefficient PCOM is set at the address 3.

The work memory (W) 106 includes an input register (PI0) 103 and an input register (PI1) 104
This is a work memory for temporarily storing an input audio signal WIN, an input signal, and data of a calculation result in a multiplication unit 300 and an addition / subtraction unit 400, which will be described later, and the like. As the data stored in the work memory (W) 106, for example, as shown in the memory map of the work memory (W) 106 in FIG.
INP, input signal WINR at address 1, sawtooth rate WLF1 at address 2, sawtooth rate WCC0 at address 3, constant WZRO at address 4, chorus delay output WCC2 at address 5, The chorus output WCC3 is at address 6, the delay delay output WDD0 is at address 7, the delay output WD1 is at address 8, the all-pass filter output WALM is at address 9, the comb filter α output WRV0 is at address 10, and The address 11 has the comb filter β output WRV1 and the address 12 has the comb filter output γWRV2 and the address 13
Stores the reverb output WRV3.

Therefore, the work memory (W) 10
6, an input memory having a plurality of storage areas for storing an input audio signal and an output signal of the analog effect adding means in a predetermined area; and an input memory having a plurality of storage areas for storing an output signal of the digital effect adding means in a predetermined area. Function as an output memory to be stored in the memory.

The delay processing section 200 includes a delay offset memory 201, a register (LF) 202, and a register (TR).
203, a gate 204, 205, an adder 206, a register (ER) 207, a register (EA) 208, a register (E0) 209, a register (E1) 210, and a delay memory 211.
, Various offset values, for example, T00 and the like are written from the microcomputer 16. The various offset values written in the delay offset memory 201 are set in the register (TR) 203, and the register (TR) 20
3 is output to the adder 206 via the gate 205. The set value of the register (LF) 202 is input to the gate 205, and the gate 205
R) 203 and the value of the register (LF) 202 are selectively output to the adder 206. In this register (LF) 202, a value from an addition / subtraction unit 400 described later is set.
The value from the gate 204 is further input to the adder 206, the count value SC of the counter from the control circuit 102 is input to the gate 204, and the adder 20
6 is input via a register (ER) 207. The gate 204 selectively outputs the two inputs to the adder 20.
6 is output.

The adder 206 comprises a gate 204 and a gate 2
05, and outputs the addition result to a register (ER) 207 and a register (EA) 208. The addition result set in the register (EA) 208 is output to the delay memory 211 and the delay memory 21
1 is used as the address. Various data of the DSP 13 is input to the delay memory 211 via the register (E0) 209, and the delay memory 211 reads various data input via the register (E0) 209 based on the address designation. Thus, the data is delayed and output to the register (E1) 210. The data set in the register (E1) 210 is output to each section of the DSP 13 via the bus 109, and is used for various effect adding processes, especially for chorus processing and delay processing.

The multiplication unit 300 includes gates 301 and 302,
Register (M0) 303, (M1) 304, gate 30
5, a multiplier 306 and a register (MR) 307. The gates 301 and 302 include the coefficient memory (P) 105, the work memory (W) 106, the input register (PI0) 103, and the input register (PI1). ) 104
The output from is input.

The gates 301 and 302 are connected to the control circuit 1
02 controls its operation, and determines which data is input to the register (M0) 303 and the register (M1) 304.
Is output or not. Register (M0) 303
Temporarily stores data input through the gate 301, outputs the data to the multiplier 306, and feeds back the data to the gate 301. The register (M1) 304 temporarily stores data input through the gate 302, outputs the data to the multiplier 306 through the gate 305, and feeds back the data to the gate 302. In the gate 305,
The data from the addition / subtraction unit 400 described later is also input, and the gate 305 operates under the control of the control circuit 102 to select the data from the register (M1) 304 and the addition / subtraction unit 400 and output the data to the multiplier 306. I do. Multiplier 30
6 is a register (M0) 303 and a register (M1) 3
The multiplication processing is performed on the data input from the block 04, and the calculation result is output to the register (MR) 307. Register (M
R) 307 temporarily stores the multiplication result of the multiplier 306, and then outputs the result to the gate 302 and the addition / subtraction unit 400.

The addition / subtraction unit 400 includes gates 401 and 40
2. Register (A0) 403, Register (A1) 40
4, gates 405 and 406, adder / subtractor 407, register (AR) 408, clipper 409, and register (S
R) 410 and the like, and the gates 401 and 402 have the coefficient memory (P) 105 and the work memory (W)
The output from the input register (PI0) 103 and the input register (PI1) 104 is input.

The gates 401 and 402 are connected to the control circuit 1
02 controls the operation of the register (A0) 403 and the register (A1) 404.
Is output or not. Register (A0) 403
Temporarily stores data input through the gate 401, outputs the data to the gate 405, and feeds back the data to the gate 401. The register (A1) 404 temporarily stores data input through the gate 402, outputs the data to the gate 406, and feeds back the data to the gate 402. The data from the register (MR) 307 of the multiplication unit 300 is also input to the gate 405.
The gate 405 operates under the control of the control circuit 102,
The data from the register (A0) 403 and the multiplier 300 are selected and output to the adder / subtractor 407. In the gate 406, in addition to the data from the register (A1) 404, the data of the operation result of the adder / subtractor 407 is stored in the register (AR) 40.
The gate 406 operates under the control of the control circuit 102 to select the input data and output it to the adder / subtractor 407.

The adder / subtractor 407 performs an addition process or a subtraction process on the input data, and stores the operation result in a register (A
R) 408. The register (AR) 408 outputs the operation result of the adder / subtractor 407 to the clipper 409 and the gate 4
06 and the register (LF) 202 of the delay processing unit 200, and the maximum bit of the operation result is output to the control circuit 102 as a code flag F (AR) indicating code information. The clipper 409 is for preventing data overflow, and the data that has passed through the clipper 409 is supplied to a register (SR) 410. The output of the register (SR) 410 is output to the gate 305 of the multiplying unit 300, and is also supplied to the work memory (W) 106 via the internal bus 109 as a calculation result of processing for a certain sound.

The operation results of the multiplication unit 300 and the addition / subtraction unit 400 are output from the addition / subtraction unit 400 to the work memory (W) 106 via the bus 109. ) 106 to the output register (OR0) 107 or the output register (OR1) 108. Whether the output data is output to the output register (OR0) 107 or the output register (OR1) 108 is controlled by the control circuit 102. Therefore, the control circuit 102 specifies the read area of the input memory (work memory (W) 106), selects the signal to be processed by the digital effect adding means (DSP13), and outputs the output signal of the digital effect adding means. A write area for the memory (work memory (W) 106) is specified, and the output signal of the digital effect adding means is used as a signal to be processed by the analog effect adding means (distortion circuit 17) or a final output signal. Function as signal selection means for determining

The output register (OR0) 107 outputs the input data to the D / A converter 14 shown in FIG. 2 as the final output signal via the output terminal Eo, and the output register (OR1) 108 receives the input data. Output data to output terminal Ao
Is output to the D / A converter 15 shown in FIG. 2 as data for a distortion process (for an analog effect adding process).

Next, the operation will be described. Electronic stringed instrument 1
, The string vibration detected by the pickup 2 is amplified by the operational amplifier 3 and input to the electronic circuit unit 4, and the electronic circuit unit 4 performs an effect adding process (effect process). Electronic stringed instrument 1
The signal is subjected to effect addition processing by the electronic circuit section 4, tone-controlled by the tone control section 5, and then output to a tone generator or the like (not shown) via the output terminal 7.

The effect adding process by the electronic circuit section 4 is as follows.
As shown in FIG. 2, the processing is performed by the DSP 13 and the distortion circuit 17. At this time, the DSP 13 can execute a plurality of types of effect addition processing in the set order, and executes the distortion processing by the distortion circuit 17 during the plurality of types of effect addition processing or first or last. I do. How to set the order of adding effects and the order of distortion processing by the DSP 13 can be set by the mode selection switch of the console 18 shown in FIG. Further, the clip position of the distortion processing by the distortion circuit 17 can be set by the volume of the console 18.

That is, as shown in FIG. 9, when the power of the electronic stringed musical instrument 1 is turned on, the electronic circuit section 4 first performs an initialization process (step S1), and
It is checked whether or not the adjustment of the volume No. 8 has been performed (step S2). When the adjustment of the volume is performed, a clip voltage corresponding to the adjusted volume value is output to the distortion circuit 17 (step S).
3) Then, the setting state of the mode switch of the console 18 is checked (step S4). Step S2
If the set value of the volume has not changed, the flow directly proceeds to step S4 to check the state of the mode selection switch.

Now, the electronic stringed musical instrument 1 has a mode 1 and a mode 2, and the mode 1 is, as shown in FIG.
In this mode, effect addition processing is performed in the order of reverb → distortion → chorus → delay.
As shown in FIG. 11, in this mode, the effect adding process is performed in the order of chorus → delay → distortion → reverb.

In step S4, it is checked whether or not the setting of the mode selection switch has changed. If the setting has not changed, it is determined that the mode has not been selected, and the process returns to step S2 to perform the same processing. Step S4
Then, when the mode selection switch is switched to the mode 1, the processing of a program list variable routine A, which will be described later, is executed (step S5), the corresponding microprogram and coefficient are transferred to the DSP 13, and the processing shifts to the processing by the DSP 13 (step S5). Step S7). Further, when the mode selection switch is switched to mode 2 in step S4, the processing of a program list variable routine B, which will be described later, is executed (step S6), and the corresponding microprogram and coefficient are transferred to the DSP 13, and the processing by the DSP 13 is performed. The process proceeds (step S7). Thus, the pre-processing of the effect adding process by the DSP 13 and the pre-processing of the effect adding process by the distortion circuit 17 are completed.

Next, the program list variable routine A will be described. Program list variable routine A
When the mode selection switch is set to the mode 1 in step S4 of FIG. 9, the process proceeds to step DI of the digital input process described later, where PI0 → WINR, that is, as shown in FIG. , Input register (P
I0) input data of 103 to work memory (W) 106
Is set to be written as the input signal WINR at the address 0 of the memory (step PA1). Next, step D5 in the delay processing described later is performed by using SR → WDD1 and SR
→ OR0, that is, the data of the register (SR) 410 is written to the address 8 of the work memory (W) 106 as the delay output WDD1, and the data of the register (SR) 410 is set to be transferred to the output register (OR0) 107. (Step PA2). Further, the step AI of the analog input processing described later is set as PI1 → WINP, that is, the input data of the input register (PI1) 104 is written to the address 0 of the work memory (W) as the input signal WINP (step PA3). . Next, step M7 in the mixing process described later is described in WRV3
→ OR1, that is, the reverb output WRV3 at address 13 of the work memory (W) 106 is output to the output register (OR
1) Set as processing to be transferred to 108 (step P
A4).

Next, the processing of the program list variable routine B will be described. The processing of the program list variable routine B shifts when the mode selection switch is set to mode 2 in step S4 of FIG.
As shown in (1), first, a digital input processing step DI to be described later is performed by PI0 → WINP, that is, the input data of the input register (PI0) 103 is stored in the work memory (W).
It is set to be written as an input signal WINP at address 0 of 106 (step PB1). Next, step D5 in the delay processing described later is performed by SR → WDD1 and SR → OR1, that is, the data of the register (SR) 410 is written to the address 8 of the work memory (W) 106 as the delay output WDD1, and the register (SR) 41
The data of 0 is set to be transferred to the output register (OR1) 107 (step PB2). Further, a step AI of analog input processing described later is performed by PI1 → WIN
R, that is, the input data of the input register (PI1) 104 is transferred to the address 0 of the work memory (W) by the input signal WIN.
Set to be written as R (step PB
3). Next, step M7 in the mixing process described below.
WRV3 → OR0, that is, the work memory (W) 1
The reverb output WRV3 at address 13 of 06 is set as a process of transferring the output to the output register (OR0) 107 (step PB4).

As described above, the area for writing data to the work memory (W) 106 is designated in accordance with the mode 1 or mode 2 by the processing of the program list variable routine, and the data in the work memory (W) 106 is The output destination is specified. When the program list variable routine processing is completed in accordance with the set mode, the microprogram and the coefficients are transferred to the DSP 13 as shown in step S7 in FIG.

Next, the processing in the DSP 13 will be described. D
The SP 13 performs the effect adding process by sequentially performing the processes shown in FIG. That is, the DSP 13 performs digital input processing (step T1) according to the microprogram transferred from the microcomputer 16.
The processing is executed in the order of → chorus processing (step T2) → delay processing (step T3) → analog input processing (step T4) → reverb processing (step T5).

Hereinafter, each processing will be sequentially described. Digital Input Processing First, digital input processing will be described with reference to FIG. The input audio signal WIN is input from the A / D converter 11 shown in FIG. 2 to the input terminal Ei of the DSP 13, and is set from the input terminal Ei to the input register (PI0) 103 shown in FIG. The input audio signal WIN set in the input register (PI0) 103 corresponds to the setting process of the program list variable routine, as shown in FIG.
In the mode 1, the input audio signal set in the input register (PI0) 103 is stored in the work memory (W) 106.
Is written as an input signal WINR to the address 1 of the memory (W). In the mode 2, the input audio signal set in the input register (PI) 103 is written as an input signal WINR to the address 0 of the work memory (W) 106 (step D).
I). That is, the address 1 of the work memory (W) 106 is an address for storing input data for a reverb effect adding process, and the address 0 is an address for storing input data for a chorus effect adding process. Therefore, the work memory (W) 1 corresponds to the set mode.
The write address of the input signal to 06 is changed. Now that the mode 2 is set, the input register (P
I) The input audio signal set in 103 is written to the address 0 of the work memory (W) 106 as the input signal WINR.

Next, the chorus processing will be described with reference to FIG. When the input signal is written to the address 0 of the work memory (W) 106 as the input signal WINR, the DSP 13
Performs a chorus process.

In the chorus processing, first, the sawtooth rate WLF1 is read from the work memory (W) 106 and transferred to the register (M1) 304 of the multiplier 300, and the sawtooth rate PRAT is read from the coefficient memory (P) 105. The data is transferred to the register (M0) 303 (step C1). Also,
The input signal WINP is read from the work memory (W) 106 and transferred to the area of the address (00) of the delay memory 211 (step C1). Next, register (M1) 3
The sawtooth wave rate WLF1 of 04 and the sawtooth rate PRAT of the register (M0) 303 are transferred to the multiplier 306 for multiplication processing (WLF1 × PRAT), and the multiplication result is transferred to the register (A0) 403 of the addition / subtraction unit 400 ( Step C2). Further, it reads the sawtooth wave rate WCC0 from the work memory (W) 106 and transfers it to the register (A1) 404 (step C2). Saw wave rate WCC0 of register (A1) 404
And the multiplication result of the register (A0) 403
7, the result of the multiplication is subtracted from the sawtooth wave rate WCC0 (WCC0- (WLF1.times.PRAT)), and the subtraction result is transferred to the register (AR) 408 (step C3). The sign flag F (AR) is output from the register (AR) 408 to the control circuit 102 as sign data SF0, and the constant WZRO and the sawtooth wave rate WCC0 are read from the work memory (W) 106, and the constant WZRO is stored in the register (A1). ) 4
In step 04, the sawtooth wave rate W CC0 is transferred to the register (A0) 403 (step C3).

In step C4, it is determined whether the code data SF0 is 1 (the code data SF0 is 1
Check if F0 is 0) and check that code data SF0 is 1
If not, that is, if the sign data SF0 indicates positive, first, the data in the register (AR) 408 is transferred to the register (SR) 410, and then the register (A)
1) The constant WZRO of 404 and the sawtooth rate WCC0 of the register (A0) 403 are transferred to the adder / subtractor 407, and are added (WZRO + WCC0). This addition result is stored in a register (A
(R) 408 (step C5). On the other hand, when the code data SF0 is 1 in step C4, that is, when the code data SF0 indicates negative,
The data of the register (AR) 408 is stored in the register (SR) 4
10 and then the constant W of the register (A1) 404
The ZRO and the sawtooth rate WC0 of the register (A0) 403 are transferred to the adder / subtractor 407, and the sawtooth rate WC is calculated from the constant WZRO.
Subtract C0 (WZRO-WCC0). The result of the subtraction is transferred to the register (AR) 408 (step C6). That is, the processing of steps C1 to C6 means that the multiplier 31, adder 32, code detector 33, and ALU 34 of the chorus processing unit 30 shown in FIG.

Next, at step C7, the register (SR)
The subtraction result of step C3 transferred to 410 {WCC0-
(WLF1 × PRAT)} is transferred to the work memory (W) 106 and written as the sawtooth wave rate WCC0, and the register (A
R) 408 is added to the register (A
R) Transfer to 408. The delay memory 211
The input signal WINP transferred to the work memory (W) 106 is delayed by a predetermined time T00 + AR, that is, the input signal WINP stored at the address (00 + AR) of the memory 211 is delayed.
And write it to address 5 as chorus delay output WCC2 (step C7).

The chorus delay output WCC2 and the input signal WINP are read from the work memory (W) 106, and the chorus delay output WCC2 is stored in the register (A0) 403 and the input signal WI
NP is transferred to the register (A1) 404 (Step C)
8). The chorus delay output WCC2 of the register (A0) 403 and the input signal WINP of the register (A1) 404 are transferred to the adder / subtractor 407, and are added (WCC2 + WINP).
Then, the result of the addition is transferred to the work memory (W) 106 and written into the address 6 as the chorus output WCC3 (step C9). The input signal can be output in a state where it is temporally shifted based on the triangular wave by the chorus processing, and a signal to which a so-called chorus effect is added can be obtained.

Delay Processing Next, the delay processing will be described with reference to FIG. In the present embodiment, a chorus-processed signal is subjected to delay processing. Therefore, in the delay processing, the chorus processing is performed, and the delay processing is performed on the chorus output WCC3 written at the address 6 of the work memory (W) 106.

Then, the chorus output WCC3 is read out from the work memory (W) 106 and transferred to the area of the address (01) of the delay memory 211, where
The chorus output WCC3 delayed by a predetermined time at 11, that is, from the area of the address (02) of the delay memory 211 to the work memory (W) 106, is written to the address 7 as the delay delay output WD0 (step D1).
This delay output WD0 is stored in the work memory (W) 10
6 is transferred to the register (A0) 403, and the chorus output WCC3 is read from the work memory (W) 106 and transferred to the register (A1) 404 (step D2). The delay output WDD0 of the register (A0) 403 and the chorus output WCC3 of the register (A1) 404 are transferred to the adder / subtractor 407 and added (WDD0 + W
CC3), and transfers the addition result to the register (AR) 408 (step D5). Register this addition result in the register (AR)
408 is transferred to the register (SR) 410 and set (step D4). The addition result set in the register (SR) 410 is transferred to the work memory (W) 106 and stored in the address 8 of the work memory (W) 106. Delay output W
The data is written as DD1 and is used for the processing in step D2 (step D5). This register (SR) 4
The addition result set to 10 is transferred to the output register (OR0) 107 or the output register (OR1) 108 according to the mode setting, that is, according to the setting of the program list variable routine processing. That is, when the mode 1 is set, the register (SR) 410
Is transferred to the output register (OR0) 107,
When mode 2 is set, the register (SR)
The result of addition at 410 is transferred to the output register (OR1) 108 (step D5).

As described above, in the delay processing, an input signal can be sequentially output with a predetermined time delay. The signal subjected to this delay processing is output to an output register (OR0).
Which process is to be performed next is set depending on whether the data is transferred to 107 or the output register (OR1) 108. That is, when transferred to the output register (OR0) 107, the processed signal is output to the D / A converter 14 of FIG. 2 as a final output signal via the output terminal EO and transferred to the output register (OR1) 108. Then, the signal is output to the distortion circuit 17 via the output terminal Ao and subjected to distortion processing.

Now, since the mode 2 is set, the processed signal subjected to the delay processing is output to the output register (OR
1) Transferred to 108, and output register (OR1) 108
Circuit 1 through a D / A converter 15
7 is output.

The processed signal subjected to the distortion processing by the distortion circuit 17 is digitally converted by the A / D converter 12, and then input to the input terminal Ai of the DSP 13. The input signal input to the input terminal Ai is made to correspond to the setting mode, and an area to be written in the work memory (W) 106 is determined by an analog input process described below.

Analog Input Processing Next, the analog input processing will be described with reference to FIG. The analog input processing is performed by the distortion circuit 17
Is a process for setting which effect adding process is to be performed next by the DSP 13 for an input signal that has been subjected to a distortion process as an effect adding process in an analog manner. Specifically, the work memory (W ) 106
The writing area for the is determined.

That is, the input signal input to the input terminal Ai from the distortion circuit 17 via the A / D converter 12 is set in the input register (PI1) 104, and the input signal set in the input register (PI1) 104 is The write area for the work memory (W) 106 is determined in accordance with the setting of the program list variable routine process. When the mode is set to mode 1, the input signal set in the input register (PI1) 104 is written to the address 0 of the work memory (W) 106 as the input signal WINP. The input signal set in (PI1) 104 is stored in address 1 of the work memory (W) 106, and the input signal W
Write as INR (step AI). When set as the input signal WINP, it is handled as an input signal for chorus processing as described above, and when set as an input signal WINR, it is handled as an input signal for reverb processing as described above. Since it is assumed that mode 2 is set as the mode, the input register (PI1)
The input signal set to 104 is the work memory (W)
The input signal WINR is written into the input signal 106, and is subjected to reverb processing.

Reverb processing Next, the reverb processing will be described with reference to FIGS. As shown in FIG. 19, the reverb process includes an all-pass filter process (step OF), a comb filter α
Processing (step αF), comb filter β processing (step βF), comb filter γ processing (step γF), and mixing processing (step M) are sequentially performed.
Hereinafter, the above processes will be sequentially described.

First, regarding the all-pass filter processing,
A description will be given based on FIG. This all-pass filter processing corresponds to the processing in the all-pass filter processing unit 50 in FIG. 5, and firstly, the processing signal delayed from the delay memory 211 by a predetermined delay time T02, that is, the delay memory 2
The signal stored in the area of the address (02) of No. 11 is transferred to the register (M1) 304, and the all-pass filter coefficient PALK is read out from the coefficient memory (P) 105 and transferred to the register (M0) 303 (step OF1). ). The processing signal of the register (M1) 304 and the all-pass filter coefficient PALK of the register (M0) 303 are transferred to the multiplier 306 for multiplication processing, and the multiplication result is transferred to the register (A0) 403 of the addition / subtraction unit 400 (step OF2). Next, the input signal WINR is read from the work memory (W) 106 and transferred to the register (A1) 404 (step OF2), and the multiplication result of the register (A0) 403 and the input signal WINR of the register (A1) 404 are added / subtracted. The data is transferred to 407 for addition processing. The result of this addition is transferred to the register (AR) 408 (step OF3), and the register (AR) 408 is further transferred to the register (SR) 41.
In addition to the transfer to 0, the addition result set in the register (AR) 408 is transferred to the register (M1) 304 of the multiplication unit (step OF4). Also, a coefficient memory (P) 1
05, the all-pass filter coefficient PALL is read and transferred to the register (M0) 303 (step OF4), and the step OF3 set in the register (SR) 410 is performed.
Is transferred to the area of the address (03) of the delay memory 211, and the addition result set in the register (M1) 304 and the all-pass filter coefficient PALL of the register (M0) 303 are transferred to the multiplier 306 for multiplication. After processing, the multiplication result is transferred to the register (MR) 307 (step OF5). Next, a delay signal delayed from the area of the address (02) of the delay memory 211 by a predetermined time is transferred to the register (A1) 404 (step OF).
5).

When the setting of the multiplication result in the register (MR) 307 and the setting of the delay signal in the register (A1) 404 are completed, the multiplication result of the register (MR) 307 and the delay signal of the register (A1) 404 are added and subtracted. 407 to perform addition processing, and store the addition result in a register (A
R) 408 (step OF6). The result of this addition is transferred to register (SR) 410 (step OF).
7) Further, the data is transferred from the register (SR) 410 to the work memory (W) 106 and written into the address 9 as the all-pass filter output WALM (step OF8). The processed signal subjected to the all-pass filter processing by the above processing is output to the work memory (W) 106 by the all-pass filter output WAL.
Written as M.

The processed signal that has been subjected to the all-pass filtering is, as shown in FIG.
0, are output to the comb filter β70 and the comb filter γ80, and the respective comb filter processes are performed.
Each comb filter process is sequentially performed using the work memory (W) 106.

First, the comb filter α processing will be described with reference to FIG. In the comb filter α processing, the delay processing signal T06 delayed for a predetermined time is transferred from the area of the address (06) of the delay memory 211 to the register (M1) 304 of the multiplier 300, and the comb-shaped filtering is performed from the coefficient memory (P) 105. The coefficient PCOM is read and transferred to the register (M0) 303 (step αF1). The delay processing signal T06 of the register (M1) 304 and the comb filtering coefficient PCOM of the register (M1) 304 are transferred to the multiplier 306 for multiplication processing, and the multiplication result is transferred to the register (MR) 307 (step αF2). Also,
The all-pass filter output WALM is read from the work memory (W) 106, and the register (A
1) Transfer to 404 (step αF2), and register (M
R) The multiplication result of 307 and the all-pass filter output WALM of the register (A1) 404 are transferred to the adder / subtractor 407 to perform an addition process (step αF3). The result of the addition is transferred to the register (AR) 408, and a delay processing signal T05 delayed by a predetermined time from the area of the address (05) of the delay memory 211 is stored in the register (A0) 40.
3 (step αF3).

The result of addition of the register (AR) 408 is transferred to the register (SR) 410, and the result of addition and the delay processing signal T05 of the register (A0) 403 are transferred to the adder / subtractor 407 for addition processing. AR) 4
08 (step αF4). The addition result of step αF3 set in the register (SR) 410 in step αF4 is transferred to the area of the address (05) of the delay memory 211 as the delay processing signal T04, and
R) 408 is transferred to the register (SR) 410 (step αF5). This register (SR) 410
Is transferred to the work memory (W) 106, and is written into the address 10 of the work memory (W) 106 as the comb filter α output WRV0 (step αF6).

Similarly to the above comb filter α processing, the comb filter β processing and the comb filter γ processing
3, the result of the comb filter β processing is set as the comb filter β output WRV1 at the address 11 of the work memory (W) 106, and the result of the comb filter γ processing is set as the address of the work memory (W) 106. 12 is written as a comb filter γ output WRV2.

When the processing result of each comb filter processing is written into the work memory (W) 106, the processing signals subjected to each comb filter processing are mixed.

Next, the mixing process will be described with reference to FIG. In the mixing process, first, the work memory (W)
The comb filter α output WRV0 and the comb filter β output WRV1 are read from 106, and the comb filter α output WRV0 is transferred to the register (A0) 403 of the addition / subtraction unit 400, and the comb filter β output WRV1 is transferred to the register (A1) 404 (step M1). ). The comb filter α output WRV0 of the register (A0) 403 and the comb filter β output WRV1 of the register (A1) 404 are transferred to the adder / subtractor 407 for addition processing, and the addition result is transferred to the register (AR) 408 (step M2). . The result of this addition is stored in register (A1) 4
04, the comb filter γ output WRV2 is read from the work memory (W) 106 and the register (A0) 403 is read out.
(Step M3). These registers (A1)
The addition result of 404 and the comb filter γ output WRV2 of the register (A0) 403 are transferred to the adder / subtractor 407 for addition processing, and the addition result is transferred to the register (AR) 408 (step M4). This addition result is stored in a register (SR) 4
10 to the work memory (W) 106 (step M5), and the address 13 of the work memory (W) 106
As the reverb output WRV3 (step M
6). The output register of the reverb output WRV3 written in the work memory (W) 106 is determined according to the processing of the program list variable routine. That is, when the mode 1 is set, the work memory (W)
The reverb output WRV3 is read from 106 and transferred to the output register (OR1) 108. When the mode 2 is set, the reverb output WRV3 is read from the work memory (W) 106, and the output register (OR
0) Transfer to 107. Output register (OR1) 108
Is output to the D / A converter 15 via the output terminal AO, is output from the D / A converter 15 to the distortion circuit 17, and is subjected to distortion processing. The output register (OR0) 10
The reverb output WRV3 transferred to the D / A converter 7 is output from the output terminal EO to the D / A converter 14, converted into an analog signal by the D / A converter 14, and then converted as a final output signal into the tone control unit 5 in FIG. Is output to Now that the mode 2 is set, the reverb output WRV3 is read from the work memory (W) 106 and output to the output register (OR
0) 107 and output from the output register (OR0) 107 to the D / A converter 14 via the output terminal EO as a final output signal.

As described above, by changing the writing area in the work memory (W) 106, not only the order of the plurality of effect adding processes by digital processing in the DSP 13 can be changed, but also the effect adding process in the DSP 13 can be performed. And the order of the effect adding processing by the analog processing in the distortion circuit 17 can be appropriately changed.
The order of the effect adding process by digital processing and the effect adding process by analog processing can be easily and easily changed without changing the physical connection between the SP 13 and the distortion circuit 17. As a result, it is possible to generate a more varied musical tone.

In the above embodiment, the DSP 13
Has been described, the reverb processing, the chorus processing, and the delay processing are performed, and the chorus processing and the delay processing are continuously performed. However, the effect adding processing performed by the DSP 13 is not limited to these processings. Needless to say.

Further, in the above embodiment, the distortion processing is employed as the analog effect adding processing, but it is needless to say that the present invention is not limited to this.

[0087]

According to the first and second aspects of the present invention, the input data stored in the input memory means by the signal selecting means.
At least two types of force sound signal and analog effect added signal
How to supply for the kind of digital effect addition processing
And the at least two types of digital effect addition processing
The final output signal of the output memory
Area to remember and input signal to the analog effect adding means
Change which of the areas to store
Thus, the connection order of the digital effect adding unit and the analog effect adding unit can be changed without changing the physical connection relationship.
Since it can be changed as appropriate, the processing order of the digital effect adding means and the analog effect adding means can be changed as appropriate. As a result, the order of effect addition when a plurality of effects are added can be easily changed, and intended effects can be easily added.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an electronic stringed instrument as one embodiment of an effect adding device of the present invention.

FIG. 2 is a block diagram of the electronic circuit unit of FIG. 1;

FIG. 3 is a circuit diagram of the distortion circuit of FIG. 1;

FIG. 4 is a block diagram schematically showing chorus processing and delay processing of the DSP of FIG. 1;

FIG. 5 is a block diagram schematically showing a reverb process of the DSP of FIG. 1;

FIG. 6 is a detailed circuit configuration diagram of the DSP of FIG. 2;

FIG. 7 is a view showing filter coefficients stored in a coefficient memory (P) of FIG. 6;

FIG. 8 is a view showing various data stored in a work memory (W) in FIG. 6;

FIG. 9 is a flowchart illustrating a mode setting process.

FIG. 10 is a diagram showing a processing order of each effect adding process in mode 1;

FIG. 11 is a diagram showing a processing order of each effect adding process in a mode 2;

FIG. 12 is a flowchart showing a program list variable routine A process in mode 1;

FIG. 13 is a flowchart showing a program list variable routine B process in mode 2;

FIG. 14 is a flowchart showing a basic procedure of each processing in the DSP in a mode 2;

FIG. 15 is a flowchart showing details of digital input processing.

FIG. 16 is a flowchart showing the detailed processing contents of the chorus processing.

FIG. 17 is a flowchart showing the detailed processing contents of the delay processing.

FIG. 18 is a flowchart showing detailed processing contents of analog input processing.

FIG. 19 is a flowchart showing the details of reverb processing;

FIG. 20 is a flowchart illustrating detailed processing contents of an all-pass filter processing.

FIG. 21 is a flowchart showing details of the comb filter α processing.

FIG. 22 is a flowchart showing the detailed processing contents of the comb filter β processing.

FIG. 23 is a flowchart showing the details of comb filter γ processing;

FIG. 24 is a flowchart showing detailed processing content of the mixing processing.

[Explanation of symbols]

 Reference Signs List 1 electronic stringed instrument 2 pickup 4 electronic circuit section 5 tone control section 6 volume 7 output terminal 11, 12 A / D converter 13 DSP 14, 15 D / A converter 16 microcomputer 17 distortion circuit 18 console 21 buffer 22 amplifier circuit 23 Clip circuit 24 Amplification circuit 101 Program memory 102 Control circuit 103 Input register (PI0) 104 Input register (PI1) 105 Coefficient memory (P) 106 Work memory (W) 107 Output register (OR0) 108 Output register (OR1) 200 Delay Processing unit 300 Multiplication unit 400 Addition / subtraction unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G10H 1/08-1/16 G10H 1/00

Claims (2)

(57) [Claims] 1. An input audio signal using an analog element.
Analog effect adding means for effect adding processing, an area for storing an input audio signal, and the analog effect adding
Input memory device having an area for storing the output signal of the means
And digital processing of at least two types of effect adding processing.
Means for adding digital effects, an area for storing a final output signal, and the analog effect adding means.
An output memory means having an area for storing an input signal to the means; and an input sound signal stored in the input memory means.
For each of the output signals of the analog effect adding means,
Digital effect adding means with at least two kinds of effects
Processing to be performed, and
Each output with at least one of two types of effect processing
Storing a signal as a final output signal of the output memory means.
Stores the area and the input signal to the analog effect adding means
Signal selection means for selecting which of the areas to be supplied . 2. The effect adding device according to claim 1, wherein said analog effect adding means is a distortion circuit.