JP3136868B2 - Asynchronous spread spectrum communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous spread spectrum communication system using matched pulses in direct spread modulation.

[0002]

2. Description of the Related Art Conventionally, in spread spectrum communication using direct spread modulation, a delay detection method has been used as a method that does not require a PN code (pseudo noise sequence) synchronization device on the receiving side. In this differential detection method, after transmitting data is differentially converted on the transmitting side, the data is multiplied with a PN code to obtain a spread spectrum signal, and the receiving side spreads the received spread spectrum signal and the received spread spectrum signal by one bit. The product is multiplied with a signal delayed by one minute (corresponding to one cycle of the PN code), and a data signal is demodulated using a low-frequency component of the multiplied signal.

FIG. 4 is a block diagram of a conventional differential detection system.
FIG. 5 shows the signal waveform of each part. FIG. 4A shows a block diagram on the transmission side. In the figure, source binary data input from a signal line 500 is input to an exclusive OR gate 50. The other input of the exclusive OR gate 50 is input from the signal line 501, and the exclusive OR gate 50
, An exclusive OR operation is performed, and a so-called precoded signal is output to the signal line 502. Signal line 5
02 is input to the delay circuit 51 and the source binary data 1
The signal is delayed and output to the signal line 501.

The clock generation circuit 54 outputs a clock signal for generating a modulation PN code to a signal line 504. P
The N code generator 53 generates a modulation PN code according to the clock signal from the signal line 504 and outputs the generated PN code to the signal line 503. The multiplier 52 multiplies the signal from the signal line 502 by the signal from the signal line 503 and outputs the product to the signal line 505. The signal from the signal line 505 is supplied to the carrier signal generator 56.
Is multiplied by the carrier signal from the
07.

FIG. 4B shows a block diagram of the receiving side.
In the figure, a received spread spectrum signal from a signal line 508 is input to a SAW correlator 57. SAW correlator 5
Reference numeral 7 outputs a carrier matched pulse signal having positive and negative phase information to the signal line 509 for each data bit (one cycle of the PN code) according to the polarity of the transmission PN code.
The matched pulse signal from the signal line 509 is
Is input to a delay circuit 58 having a delay time of one bit of data. The multiplier 59 multiplies the matched pulse signal from the signal line 509 by the delayed matched pulse signal from the signal line 510, outputs the result to the signal line 511, and the data demodulation circuit 60 demodulates information data.

FIG. 5 shows the signal waveform of each part. FIG. 5 (a)
5B shows the waveform of the source binary data of the signal line 500, FIG. 5B shows the precoded signal waveform of the signal line 502,
FIG. 5C shows a matched pulse signal including a carrier on the signal line 509, FIG. 5D shows a matched pulse signal delayed by one period of the PN code on the signal line 510, and FIG.
Shows the waveform of the signal line 511, and FIG. 5F shows the demodulated data waveform of the signal line 512.

[0007]

In the conventional spread spectrum communication system described above, a delay time of one cycle of the PN code is required in the carrier frequency band on the receiving side. In order to obtain this delay time, in addition to the above-described method using a SAW delay line, a baseband signal is converted by synchronizing with a carrier frequency signal, and the baseband signal is digitally converted using a clock signal. Although there is a method of performing this, both methods require a complicated circuit configuration and are expensive.

Accordingly, the present invention provides a square-law detection of a matched pulse including a carrier frequency instead of a carrier frequency band on the receiving side.
Circuit is detected by using the detected matched pulse in the baseband obtained by the above method and the detected matched pulse and the matched pulse delayed by one period of the PN code, thereby making the circuit simple and inexpensive. It is an object of the present invention to realize a configurable spread spectrum communication system.

[0009]

In order to solve the above-mentioned problems, a spread spectrum communication system according to the present invention detects a rising portion of source binary data on a transmission side in a spread spectrum communication system using direct spread modulation. Means, PN code generating means for outputting a PN code initialized each time the rising portion is detected, and fixing the PN code output from the PN code generating means in accordance with the polarity of the source binary data And output the
Means for multiplying the selectively output PN code by a carrier frequency signal to transmit a spread spectrum signal, and comprising: a receiving side for selectively receiving the spread spectrum signal from among the received spread spectrum signals. Means for detecting the output PN code and generating a matched pulse for each period of the PN code; means for square-detecting the matched pulse; A delay means for delaying by a period, a signal detected by square detection as a first input signal, a signal delayed by the delay means as a second input signal, and the first input signal being the second input signal. The demodulation means for demodulating the source binary data by outputting the binary data in the first state and outputting the second input signal in the second state prior to the input. Even without it is characterized in that it comprises four means.

Further, on the receiving side, the pulse width of the square-detected first input signal is shaped so as to be wider than the pulse width of the second input signal delayed by one period of the PN code. It is a feature.

[0011]

According to the above-mentioned method, the receiving side can demodulate the data by delaying the matched pulse in the baseband. In particular, on the transmitting side, each time the pulse of the source binary data rises, the PN code is generated. To initialize the PN
Since the code is transmitted, one cycle of the PN code is data 1
The communication speed can be increased to a speed corresponding to a bit. On the receiving side, the squared detection of the matched pulse can improve the S / N ratio of the matched pulse.

Further, on the receiving side, the pulse width of the first and second input signals is shaped so that the falling signal of the demodulated data is included in the rising signal. Variations can be absorbed and accurate data can be demodulated.

[0013]

Embodiments of the present invention will be described below in detail. FIG. 1 is a block diagram showing an embodiment of a transmitting side for realizing the asynchronous spread spectrum communication system of the present invention.

In FIG. 1A, source binary data input from a signal line 100 is input to a leading edge detection circuit 10 by a binary signal.
The rising edge of the value data pulse is detected. The leading edge signal indicating the rising edge of the detected binary data is output to the signal line 101 and input to the PN code generator 12. The PN code generator 12 is initialized by the leading edge signal from the signal line 101 so that the PN code is output from the beginning of the code, and is output to the signal line 102.
The signal on the signal line 103 is fixed to the ground potential. Of course, the signal on the signal line 103 may output a PN code having low cross-correlation with the PN code on the signal line 102. The selection circuit 11 selects signals from the signal lines 102 and 103 according to the polarity of the source binary data, and
5 is output. In the clock generation circuit 13, the modulation PN
A clock signal for generating a code is output to a signal line 104.

The spread spectrum signal from signal line 105 is a P-spectrum signal selected according to the polarity of the source binary information data signal.
This is an N code, and is multiplied by the carrier frequency signal from the carrier frequency signal generation circuit 15 in the multiplier 14. Signal line 10
The product signal of 7 is band-limited by the band pass filter 16 and outputs a transmission spread spectrum signal to the signal line 108.

FIG. 1B shows a circuit example of the selection circuit 11 shown in FIG. In FIG. 1B, when the binary data signal from the signal line 100 is at the H (high) level, the signal line 102
And outputs the signal from the signal line 103 to the signal line 109 when the binary data signal is at the L (low) level. The PN code selected by the binary data signal from the signal line 109 is latched by the D flip-flop 20 by the clock signal from the signal line 104 and output to the signal line 105 as a spread spectrum signal.

FIG. 2 is a block diagram showing one embodiment of the receiving side for realizing the present invention. In FIG. 2A, a received spread spectrum signal input from a signal line 200 is input to a multiplier 20. The other input of the multiplier 20 is input from the signal line 201, and is multiplied by the local signal from the local oscillation frequency signal generator 21 and the received spread spectrum signal from the signal line 200, and the intermediate frequency spectrum is added to the signal line 202. Output as a spread signal.

The intermediate frequency spread spectrum signal from the signal line 202 is band-limited by the band-pass filter 22,
The signal is output to the signal line 203. The intermediate frequency spread spectrum signal from the signal line 203 is supplied to the next SAW
The signal is amplified to the optimum input level of the correlator 24. The SAW correlator 24 outputs a matched pulse signal to the signal line 205 for each period of the PN code whose bit pattern matches.

Since this matched pulse signal contains a carrier component of an intermediate frequency, a double balanced signal is used.
Square detection is performed by the modulator 25, and the low-pass filter 2
In step 6, the low-frequency component is extracted and output to the signal line 207. With this square detection operation and LPF band limitation,
The signal-to-noise ratio of the pulse signal can be improved.

In the matched pulse shaping circuit 27, the matched pulse signal is shaped into a wide pulse and the signal
8 and output as a set signal of the flip-flop circuit 30. The pulse width of the set signal is set wider than the pulse width of a reset signal described later. The wide pulse signal on the signal line 208 is also input to the delay circuit 28, delayed by one cycle of the PN code in the delay circuit 28, and output to the signal line 209. The delayed wide pulse signal from the signal line 209 is supplied to the edge detection circuit 29.
The leading edge is extracted by the flip-flop circuit 30.
Is output to the signal line 210 as the reset signal.

The flip-flop circuit 30 is a set-priority set-reset flip-flop circuit.
The source binary data is demodulated by the set signal from the signal line 208 and the reset signal from the signal line 210,
Output to 2.

FIG. 2B shows a circuit example of the set priority flip-flop circuit 30. A set signal is input from the signal line 208 and a reset signal is input from the signal line 210. The reset signal is valid only when the set signal is at the L level, and only when the reset pulse is input. , A valid reset on the signal line 214 as a negative pulse
Output as a pulse. The set pulse signal is valid regardless of whether the reset pulse signal is at the H level or the L level. When the set pulse signal is input, the signal line 213 is output.
Is output as a negative pulse.

The set pulse signal on the signal line 213 and the reset pulse signal on the signal line 214 are input to the D flip-flops 36 and 37, and are synchronized with the clock signal 211 from the clock signal generator 31. Signal line 215
, And a reset pulse signal from the signal line 216 are input to a set / reset flip-flop circuit composed of logic gate elements 38 and 39, and a demodulated data signal is output to the signal line 217. The signal is output to the signal line 212 through the flip-flop 40.

FIG. 3 shows the signal waveform of each part. FIG. 3 (a)
Indicates source binary data of the signal line 100 in the block diagram on the transmission side in FIG. FIG. 3B shows a signal waveform of the signal line 101 and shows a leading edge signal from which the leading edge of binary data is extracted by the leading edge detection circuit 10. FIG. 3C shows the signal line 10.
2 shows a PN code signal initialized each time the leading edge signal 101 is detected in the signal waveform 2. FIG. 3D shows the signal waveform of the signal line 105, which is the output signal of the selection circuit 11 selected by the polarity of the binary data. The signal on the signal line 103 is a signal fixed to the ground potential.

As described above, the transmitting side resets the PN code every time a pulse of the source binary data rises, and transmits the PN code from the beginning of the PN code.
The communication speed can be increased to a speed where one cycle of the PN code corresponds to one bit of the source binary data.

FIG. 3E shows a signal waveform of a reception matched pulse on the signal line 207 in the block diagram of the reception side in FIG. FIG. 3F shows a matched pulse signal in which the matched pulse shaping circuit 27 of the signal line 208 is widely pulse-shaped. FIG. 3G shows a delayed matched pulse signal on the signal line 209, and FIG. 3H shows an edge extraction signal of the delayed matched pulse signal on the signal line 210. FIG.
The edge extraction signal of (h) is extracted in a relationship that is temporally included with respect to the wide delayed matched pulse signal of FIG. FIG. 3I shows demodulated data output from the set-priority flip-flop circuit 30.

As described above, on the receiving side, data is not demodulated by using the phase information of the carrier wave as in the related art.
Since the double balanced modulator is used, the S / N of the matched pulse can be improved, that is, the BER can be improved. Furthermore, by setting the pulse width so that the reset pulse signal is included in the set pulse signal, the dispersion of the delayed reset pulse signal can be absorbed by the wide-shaped set pulse signal. The operation of setting and resetting can be ensured, and correct demodulated data can be obtained.

[0028]

As described above, according to the spread spectrum communication system of the present invention, instead of performing delay detection using a SAW delay line in the IF stage as in the prior art, the base station after square detection is used. Since the data is demodulated using the matched pulse detected in the band, the circuit configuration can be simplified and the cost reduction effect is enormous.

In particular, on the transmitting side, it is possible to increase the communication speed to a speed in which one cycle of the PN code corresponds to one bit of data. On the receiving side, it is possible to improve the S / N ratio of matched pulses, Variation in delay time of matched pulse and jitter can be absorbed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a transmission side in an embodiment of a spread spectrum communication system according to the present invention.

FIG. 2 is a block diagram of a receiving side in the embodiment.

FIG. 3 is a signal waveform diagram of each part on the transmission / reception side in the embodiment.

FIG. 4 is a block diagram of a conventional spread spectrum communication system.

FIG. 5 is a signal waveform diagram of each part of the same system.

[Explanation of symbols]

 Reference Signs List 10 Leading edge detection circuit 11 Selection circuit 12, 53 PN code generator 13, 31, 54 Clock signal generator 14, 20, 52, 55, 59 Multiplier 15, 56 Radio carrier signal generator 16, 22, Bandpass filter 21 Local oscillation frequency signal generator 23 Amplifier circuit 24, 57 SAW correlator 25 Double balanced modulator 26 Low pass filter 27 Matched pulse shaping circuit 28, 58 Matched pulse delay circuit 51 Data delay circuit 29 Delayed matched pulse edge Detection circuit 30 set priority flip-flop circuit 50 exclusive OR operation gate element 60 data demodulation circuit

Claims (2)

(57) [Claims] In a spread spectrum communication system using direct spread modulation, means for detecting a rising portion of source binary data and a PN code initialized each time the rising portion is detected are output to a transmitting side. PN code generation means, a PN code output from the PN code generation means according to the polarity of the source binary data, and a fixed ground potential
And at least four means for multiplying the selectively output PN code by a carrier frequency signal and sending out a spread spectrum signal, wherein a receiving side receives the spread spectrum signal. From the signal
Detecting the selectively output PN code,
Means for generating a matched pulse for each cycle of the N code; means for square-detecting the matched pulse;
Delay means for delaying the squared detected matched pulse by one period of the PN code; a signal detected by the square detection as a first input signal; a signal delayed by the delay means as a second input signal; The first input signal is output in the first state among the polarities of the binary data in priority to the input of the second input signal, and the second input signal is output in the second state. A spread spectrum communication system comprising at least four demodulation means for demodulating source binary data. 2. A receiving side wherein the pulse width of the square-detected first input signal is delayed by one period of the PN code.
2. The spread spectrum communication method according to claim 1, wherein the pulse width is shaped so as to be wider than the pulse width of the input signal.