JP3136895B2 - Non-volatile memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory cell of a side wall storage type, and more particularly to a method of electrically writing / writing data.
The present invention relates to a nonvolatile memory cell for an erasable read only storage device (EEPROM).

[0002]

2. Description of the Related Art Non-volatile memory cells include
In addition to the EEPROM, there is a read-only storage device (EPROM) which can electrically write data but does not electrically erase data.

FIG. 8 shows a sidewall storage type nonvolatile memory cell 80 for an EPROM. Such a sidewall storage type nonvolatile memory cell 80 is disclosed in U.S. Pat. No. 5,051,793.

The memory cell 80 includes a P-type silicon substrate 81, a source region 82 and a drain region 83 formed in the substrate 81, a gate insulating film 84 having a uniform thickness formed on the substrate 81, Floating gate electrodes 85 a and 85 b formed on the gate insulating film 84 and a control gate electrode 86 are provided. Floating gate electrodes 85a and 85
5b are located on both sides of the control gate electrode 86 like a pair of side walls (sidewalls) of the control gate electrode 86. The floating gate electrodes 85a and 85b and the control gate electrode 86 are electrically insulated from each other by an insulating film located therebetween. The width (size in the channel length direction) of the control gate electrode 86 is shorter than the channel length, and a part of the floating gate electrodes 85a and 85b covers a part of the channel.

When the potential of the drain region 83 is made sufficiently higher than the potential of the source region 82, electrons emitted from the source region 82 follow a potential gradient (electric field) formed between the source region 82 and the drain region 83. Is accelerated in the direction of the drain region 83. The electrons that have obtained a high speed cause avalanche decay near the drain region 83, and generate many high-energy electrons (hot electrons). Part of the generated hot electrons crosses over the potential barrier of the gate insulating film 84 to form the drain region 8.
It is injected into the floating gate electrode 85b on the third side. When charges (electrons) are injected into the floating gate electrode 85b, the potential of the floating gate electrode 85b decreases, and thereby, the transistor threshold of the memory cell increases.

In this way, each memory cell can take two electrically stable states (logic "high" or logic "low") according to its threshold. As a result, each memory cell can store 1-bit information. For example, arbitrary information is stored by selectively increasing the threshold value of a desired memory cell and lowering the threshold value of another memory cell among a plurality of nonvolatile memory cells arranged in a matrix. Can be.

[0007]

The above-described sidewall storage type nonvolatile memory cell has the following problems.

In order to prevent a data reading error, the amount of charges injected into the floating gate electrode 85b may be increased. For that purpose, it is necessary to increase the electric field near the drain region 83. To increase this electric field,
It is necessary to apply a high voltage to the drain region 83. However, when such a high voltage is applied to the drain region 83, the n-type drain region 83 and the p-type substrate 81
The depletion layer of the PN junction formed by the semiconductor device extends deeply toward the source region 82. Then, the hot electrons generated by the avalanche collapse are converted into the gate insulating film 8.
4 is injected into a portion directly below the control gate electrode 86. In order to avoid such hot erotron injection, it is necessary to reduce the voltage applied to the drain region 83. However, this reduces the amount of charge (write capacity) injected into the floating gate electrode 85b, which may cause a data reading error.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a sidewall storage type nonvolatile memory cell having a large write capacity.

[0010]

[0011]

A non-volatile memory cell according to the present invention is provided with a first conductivity type semiconductor layer having an upper surface region and provided in the upper surface region of the semiconductor layer and opposed to each other at a certain distance. A second conductivity type source region and a second conductivity type drain region, a channel region provided in the upper surface region of the semiconductor layer and located between the source region and the drain region, A first portion covering the source region, a second portion covering at least a portion of the drain region, and a third portion covering the channel region. A first gate insulating film having a portion, a first floating gate electrode provided on the first portion of the first gate insulating film, and a first floating gate electrode provided on the second portion of the first gate insulating film. 2 The floating gate electrode and the first gate A control gate electrode provided on the third portion of the film and electrically insulated from the first and second floating gate electrodes, provided between the control gate electrode and the first floating gate electrode; A first insulating film that capacitively couples the control gate electrode and the first floating gate electrode; and a first insulating film provided between the control gate electrode and the second floating gate electrode, wherein the control gate electrode and the second floating gate are provided. A second insulating film that capacitively couples the electrode with the second insulating film.
The degree of capacitive coupling by the first insulating film is different from the degree of capacitive coupling by the second insulating film, and at the time of writing data, the source is controlled according to the voltage applied to the control gate electrode. Part of the electric charge in the region and / or the drain region is injected into the first floating gate electrode and / or the second floating gate electrode through the first portion and / or the second portion of the one insulating film. Thus, the above object is achieved.

In one embodiment, the thickness of the first insulating film is different from the thickness of the second insulating film.

In one embodiment, a dielectric constant of the first insulating film is different from a dielectric constant of the second insulating film.

In one embodiment, a second gate insulating film provided to cover the first and second floating gate electrodes, a first portion covering the first floating gate electrode, and the second floating gate electrode. A second gate insulating film having a second portion covering the gate electrode; a third floating gate electrode provided on the first portion of the second gate insulating film; and a second gate insulating film provided on the second gate insulating film. And a fourth floating gate electrode provided on the portion, wherein the third and fourth floating gate electrodes are capacitively coupled to the control gate electrode, and when writing the data, According to the voltage applied to the gate electrode,
Part of the electric charge in the source region and / or the drain region passes through the first part and / or the second part of the one gate insulating film to form the first floating gate electrode and / or the second part.
Or injected into the second floating gate electrode, and through the first portion and / or the second portion of the second gate insulating film,
It is implanted into the third floating gate electrode and / or the fourth floating gate electrode.

Still another non-volatile memory cell of the present invention comprises:
A first conductivity type semiconductor layer having an upper surface region, a second conductivity type source region and a second conductivity type drain region provided in the upper surface region of the semiconductor layer and facing each other at a certain distance; A channel region provided in the upper surface region of the semiconductor layer and located between the source region and the drain region;
A first gate insulating film provided on the upper surface region of the semiconductor layer, the first gate insulating film covering at least a part of the source region;
A first gate insulating film having a portion, a second portion covering at least a part of the drain region, and a third portion covering the channel region; and a first gate insulating film provided on the first portion of the first gate insulating film. A first floating gate electrode, a second floating gate electrode provided on the second portion of the first gate insulating film, and a first floating gate electrode provided on the third portion of the first gate insulating film. A control gate electrode electrically insulated from the second floating gate electrode and a second gate insulating film provided to cover the first and second floating gate electrodes, the second gate insulating film covering the first floating gate electrode; A second gate insulating film having a first portion and a second portion covering the second floating gate electrode; a third floating gate electrode provided on the first portion of the second gate insulating film; A fourth floating gate electrode provided on the second portion of the gate insulating film; The first, second, third, and fourth floating gate electrodes are capacitively coupled to the control gate electrode, and at the time of data writing, according to a voltage applied to the control gate electrode. , The source region and / or
Or a part of the charge in the drain region is injected into the first floating gate electrode and / or the second floating gate electrode through the first part and / or the second part of the one gate insulating film; Further, the second gate insulating film is injected into the third floating gate electrode and / or the fourth floating gate electrode through the first portion and / or the second portion, thereby achieving the above object.

In one embodiment, the thickness of the first portion of the first gate insulating film is equal to the thickness of the second portion.

In one embodiment, the thickness of the first portion of the second gate insulating film is equal to the thickness of the second portion.

In one embodiment, the thickness of the second portion is greater than the thickness of the first portion of the first gate insulating film.

In one embodiment, the thickness of the first portion is larger than the thickness of the second portion of the second gate insulating film.

In one embodiment, the control gate electrode completely covers the channel region.

In one embodiment, the control gate electrode covers a part of the channel region, and at least one of the first and second floating gate electrodes covers another part of the channel region.

Still another nonvolatile memory cell of the present invention is:
A first conductivity type semiconductor layer having an upper surface region, a second conductivity type source region and a second conductivity type drain region provided in the upper surface region of the semiconductor layer and facing each other at a certain distance; A channel region provided in the upper surface region of the semiconductor layer and located between the source region and the drain region;
A first gate insulating film provided on the upper surface region of the semiconductor layer, the first portion covering a part of the source region, the second portion covering a part of the drain region, and the channel region. A first gate insulating film having a third portion covering the first portion, a first portion covering the other part of the source region, the first portion being a second gate insulating film provided on the upper surface region of the semiconductor layer; A second gate insulating film having a second portion covering another portion of the drain region, a first floating gate electrode provided on the first portion of the first gate insulating film, and the first gate insulating film A second floating gate electrode provided on the second portion of
A control gate electrode provided on the third portion of the gate insulating film and electrically insulated from the first and second floating gate electrodes; and a control gate electrode provided on the first portion of the second gate insulating film. A third floating gate electrode, and a fourth floating gate electrode provided on the second portion of the second gate insulating film, wherein the first, second, third, and fourth floating gate electrodes are , Which is capacitively coupled to the control gate electrode, and at the time of writing data, according to a voltage applied to the control gate electrode.
A part of the electric charge in the source region and / or the drain region is changed by the first part and / or the second part of the one gate insulating film.
Through the first floating gate electrode and / or the second
Implanted into the floating gate electrode and through the first portion and / or the second portion of the second gate insulating film into the third floating gate electrode and / or the fourth floating gate electrode, whereby The above object is achieved.

In one embodiment, the thickness of the first portion of the first gate insulating film is equal to the thickness of the second portion.

In one embodiment, the thickness of the first portion of the second gate insulating film is equal to the thickness of the second portion.

In one embodiment, the thickness of the second portion is greater than the thickness of the first portion of the first gate insulating film.

In one embodiment, the thickness of the first portion is larger than the thickness of the second portion of the second gate insulating film.

In one embodiment, the control gate electrode completely covers the channel region.

In one embodiment, the control gate electrode covers a part of the channel region, and at least one of the first and second floating gate electrodes covers another part of the channel region. .

Still another nonvolatile memory cell of the present invention is:
A first conductivity type semiconductor layer having an upper surface region, a second conductivity type source region and a second conductivity type drain region provided in the upper surface region of the semiconductor layer and facing each other at a certain distance; A channel region provided in the upper surface region of the semiconductor layer and located between the source region and the drain region;
A first gate insulating film provided on the upper surface region of the semiconductor layer, the first portion covering a part of the source region, the second portion covering a part of the drain region, and the channel region. A first gate insulating film having a third portion covering the first portion, an insulating film provided on the upper surface region of the semiconductor layer, the first portion covering another portion of the source region, and a first portion of the drain region. An insulating film having a second portion covering another part, a first floating gate electrode provided on the first portion of the first gate insulating film, and an insulating film on the second portion of the first gate insulating film; A second floating gate electrode provided on the first portion of the insulating film, a third floating gate electrode provided on the first portion of the insulating film, and a fourth floating gate electrode provided on the second portion of the insulating film. A third floating gate electrode provided between the first floating gate electrode and the third floating gate electrode.
A gate insulating film; and a fourth gate insulating film provided between the second floating gate electrode and the fourth floating gate electrode, wherein the first, second, third and fourth gate insulating films are provided. The floating gate electrode is capacitively coupled to the control gate electrode. When data is written, one of charges in the source region and / or the drain region depends on a voltage applied to the control gate electrode. A part is injected into the first floating gate electrode and / or the second floating gate electrode through the first portion and / or the second portion of the one gate insulating film;
Injection is made into the third floating gate electrode and / or the fourth floating gate electrode through the gate insulation and / or the fourth gate insulating film, whereby the object is achieved.

[0030]

The floating gate electrode provided above the source region and the drain region is capacitively coupled to the control gate electrode. By adjusting the voltage applied to the control gate electrode, charges are injected from a source region and / or a drain region into a desired floating gate electrode. Source area and / or
Alternatively, the resistance of the diffusion layer in the drain region changes in accordance with the amount of charge stored in the floating gate electrode located thereabove. Therefore, at the time of data reading, by detecting the magnitude of the drain current, it is possible to detect a change in the resistance of the source region or the drain region, thereby making it possible to know the charge accumulation state of the floating gate electrode. .
By using a plurality of floating gate electrodes and adjusting the thickness of a gate insulating film through which electric charges need to cross, multivalued data can be stored in a nonvolatile manner. As described above, in the point that the diffusion layer resistance of the source region and / or the drain region is changed according to the charge accumulation state of the floating gate electrode, the effect of the present invention is to change the inversion threshold value of the channel region. Is different from the operation of the nonvolatile memory cell of FIG.

[0031]

【Example】

(Embodiment 1) FIG. 1 (c) shows a sectional structure of a side wall storage type nonvolatile memory cell according to the present invention. Hereinafter, CMOS having a design rule (minimum dimension) of 0.5 to 1.0 μm
The present invention will be described for a memory cell manufactured using the process.

This memory cell has a p-type silicon substrate 11
An n-type source region 24 and an n-type drain region 25 which are provided in an upper surface region of each other and are opposed to each other at a certain distance (about 0.25 μm);
5 and a channel region located between them. The source region 24 and the drain region 25 are typically impurity diffusion regions having a thickness of about 0.1 μm, and the surface concentration of the n-type impurity is 10 ²⁰ to 10 ²¹ cm ⁻³ . The silicon substrate 11 is doped with a p-type impurity of about 10 ¹⁷ cm ⁻³ .

On the silicon substrate 11, a gate insulating film is provided. This gate insulating film is formed in the source region 24.
, A second portion (thickness: 10 nm) 13b that covers the drain region 25, and a third portion (thickness: 20 nm) 12 that covers the channel region. In this embodiment, the first portion 1 of the gate insulating film
The thickness 3a and the second portion 13b are equal to each other, and both are thinner than the third portion 13c of the gate insulating film. First portion 13a and second portion 13b of gate insulating film
May be a thickness (about 5 nm) or more at which a Fowler-Nordheim current (FN current) can flow. The thickness of the third portion 13c of the gate insulating film is equal to that of the first portion 13a.
And the second portion 13b may be thicker. Further, the third portion 13c of the gate insulating film may have a multilayer structure of an oxide film and a silicon nitride film.

A first floating gate electrode 17a is provided on the first portion 13a of the gate insulating film, and a second floating gate electrode 17b is provided on the second portion 13b of the gate insulating film. Further, a control gate electrode 14 is provided on the third portion 13c of the gate insulating film. The control gate electrode 14 is electrically insulated from the first and second floating gate electrodes 17a and 17b by an insulating film having a thickness of 15 nm. Control gate electrode 14, floating gate electrode 17
a and 17b can typically be formed from polycrystalline silicon, polycide, or the like.

The gate length (length measured along the channel length direction) of the control gate electrode 14 of this embodiment is about 0.25.
μm, and the gate width (length measured along a direction perpendicular to the channel length direction) is about 2 μm. The gate length of the floating gate electrodes 17a and 17b is about 0.1 to 0.15 μm, and the gate width is equal to the gate width of the control gate electrode 14.

As shown in FIG. 1C, the memory cell is covered with an interlayer insulating film 18 formed on a silicon substrate 11. A contact hole reaching the source region 24 and the drain region 25 is provided in the interlayer insulating film 18. In addition, on the substrate 11, a source electrode 20S that contacts the source region 24 via a contact hole and a drain electrode 20D that contacts the drain region 25 are provided.

The operation of the present memory cell will be described below with reference to FIGS. 2A to 2C.

First, the write operation will be described. Potentials of 10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24 (source electrode 20S), and the drain region 25 (drain electrode 20D), respectively. Then, the potential of the control gate electrode 14 with respect to the source region 24 and the drain region 25 increases to 10 volts. The potentials of the floating gate electrodes 17a and 17b increase to a level required for generating an FN current due to capacitive coupling with the control gate electrode 14. More specifically, for example,
When the potential of the control gate electrode 14 is increased from 0 volts to 10 volts with a rise time of about 1 to 2 nanoseconds, the potentials of the floating gate electrodes 17a and 17b temporarily become 15 volts due to "overshoot". Rise to the extent. As a result, as shown in FIG.
Electrons in the source region 24 and the drain region 25 tunnel through the first and second portions of the gate insulating film, respectively, and are injected into the floating gate electrodes 17a and 17b on both sides of the control gate electrode 14. After the electrons are injected into the floating gate electrodes 17a and 17b, even if the potential of the control gate electrode 14 is lowered below 10 volts, each of the floating gate electrodes 17a and 17b is injected because it is surrounded by the insulating film. The electrons are held in the floating gate electrodes 17a and 17b.

Of the plurality of memory cells, a potential of 10 volts is selectively applied to the control gate electrode 14 of a specific memory cell, and 0 V is applied to the control gate electrode 14 of a non-selected memory cell. Give a potential of volts. Thus, electrons can be stored only in the floating gate electrodes 17a and 17b of the selected memory cell.

Next, the read operation will be described. In the control gate electrode 14, the source region 24 and the drain region 25,
A potential of 5 volts, 0 volt and 1 volt is applied, respectively. In the present embodiment, since the threshold value of the memory cell transistor is set to a value lower than 5 volts (for example, 1 volt), as shown in FIG.
A conduction channel 29 is formed between 4 and drain region 25. As a result, electrons move from the source region 24 to the drain region 25, and a certain amount of drain current is obtained.

In this embodiment, since the floating gate electrodes 17a and 17b are located outside the channel region, the threshold value of the memory cell transistor when the floating gate electrodes 17a and 17b do not store electrons and the floating gate electrodes 17a and 17b The threshold values when the gate electrodes 17a and 17b store electrons are substantially equal. Therefore, in each case, a similar conduction channel 29 is formed between the source region 24 and the drain region 25. In each case, electrons move from the source region 24 to the drain region 25, and the drain current increases. can get. However, as shown in FIG. 2B, when the floating gate electrodes 17a and 17b store electrons, the presence of the stored electrons depends on the source region 24 and the drain region 2.
5 (parasitic resistance 31). As a result, the drain current when the floating gate electrodes 17a and 17b store electrons is lower than the drain current when the floating gate electrodes 17a and 17b do not store electrons. Figure 3 shows the relationship between drain current and (I _D) and the drain voltage (V _D). As can be seen from FIG. 3, the data "0" depends on the magnitude of the drain current.
And "1" are identified.

As described above, in the sidewall storage type nonvolatile memory cell according to the present invention, one-bit information is not stored depending on the threshold value of the memory cell transistor. In the present invention, one-bit information is stored according to the magnitude of the parasitic resistance of the source region 24 and the drain region 25 located immediately below the floating gate electrodes 17a and 17b.
When the floating gate electrodes 17a and 17b store a large number of electrons, the source region 2 near the floating gate electrodes 17a and 17b is affected by the electric field formed by the electrons.
It is considered that the electrons in the region 4 and the drain region 25 decrease, and the electric resistance in the region increases. Since the magnitude of the drain current changes according to the magnitude of the parasitic resistance of the source region 24 and the drain region 25, data can be identified based on the magnitude of the drain current.

In order to execute data reading practically, the drain current in a state where data is written is:
80 of the drain current when no data is written
It may be necessary to have a magnitude of less than a percentage. In order to read data without error, the drain current in a state where data is written preferably has a magnitude of 70% or less of the drain current in a state where data is not written.

In order to increase the change in the drain current in accordance with the accumulation / non-accumulation of the electric charges in the floating gate electrodes 17a and 17b, for example, the gate length of the floating gate electrodes 17a and 17b is increased, The thickness of the first and second portions is reduced.

Next, the erasing operation will be described. A potential of −10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24, and the drain region 25, respectively. Then, the potentials of the floating gate electrodes 17a and 17b drop to a sufficiently low level due to capacitive coupling with the control gate electrode 14. As a result, as shown in FIG. 2C, the electrons stored in the floating gate electrodes 17a and 17b are changed to the floating gate electrodes 17a and 17b.
From the source region 24 and the drain region 25 (emission).

When the memory cell of FIG. 8 is compared with the memory cell of this embodiment, there is a great difference particularly in the following point.

(1) In the memory cell of FIG. 8, electrons are injected from the channel region into the floating gate electrode 85b. Therefore, in the memory cell of FIG. 8, a part of the floating gate electrode 85b needs to cover a part of the channel region. In contrast, in the present embodiment, electrons are injected from the source region 24 and the drain region 25 into the floating gate electrodes 17a and 17b, respectively. Therefore, in the memory cell of the present embodiment, it is not necessary that a part of the floating gate electrodes 17a and 17b cover a part of the channel region.

(2) In the memory cell shown in FIG. 8, in order to write data, it is necessary to generate hot electrons at the end of the channel region. Some of the generated hot electrons are injected into the floating gate electrode 85b, but the remaining part may be trapped in the gate insulating film 84 on the channel region. On the other hand, in the present embodiment, electrons are transferred from the source region 24 and the drain region 25 to the floating gate electrode 17a by the FN conduction mechanism.
And 17b. Therefore, generation of hot electrons is not necessary for writing data. Therefore, according to the present invention, hot electrons are hardly trapped in the third portion 13c of the gate insulating film, and the reliability of the memory cell is hardly deteriorated.

(3) In the memory cell of FIG. 8, the electrons stored in the floating gate electrodes 17a and 17b cannot be electrically removed, so that data cannot be electrically erased. In the memory cell of this embodiment, since the injection of electrons by the FN conduction mechanism is employed, data can be electrically erased.

Next, referring to FIGS. 1A to 1C,
A method for manufacturing the above memory cell will be described.

First, after forming a relatively thick oxide film (thickness: 20 nm) to be the third portion 13c of the gate oxide film on the upper surface of the silicon substrate 11, a polycrystalline silicon film is formed on the oxide film by CVD. Deposit. This polycrystalline silicon film is patterned into a predetermined wiring shape by a photolithography process and an etching process, and the control gate electrode 1 is formed.
4 is formed. After etching the polycrystalline silicon film, the thick oxide film located in a region other than the region below the control gate electrode 14 is also continuously removed. Thus, the thick oxide film (the third portion 13c of the gate insulating film) and the control gate electrode 14 thereon cover the channel region of the memory cell transistor in the silicon substrate 11, as shown in FIG. It will be.

Next, arsenic ions are implanted into the surface of the silicon substrate 11 using the control gate electrode 14 as a mask, and the high-concentration impurity diffusion regions (source region 24 and drain region 25) are self-aligned with the control gate electrode 14. It is formed.

An insulating film (thickness: 15 nm) for separating the floating gate electrodes 13a and 13b from the control gate electrode 14.
Is formed on the side surface of the control gate electrode 14, and then a thin oxide film (thickness: 10n) is formed on the exposed surface of the silicon substrate 11.
m). This thin oxide film is the first portion 13a and the second portion 13b of the gate insulating film.

Thereafter, a polycrystalline silicon film is deposited on the silicon substrate 11 so as to cover the thin oxide film by the CVD method. Next, by anisotropic etching technology,
By etching this polycrystalline silicon film from its upper surface without using a mask, the polycrystalline silicon film located in a region other than the side portion of the control gate electrode 14 is removed,
Thereby, the side wall type floating gate electrode 17 is formed.
a and 17b are formed on the sides of the control gate electrode 14 (FIG. 1B).

Thereafter, using a conventional technique, the interlayer insulating film 18 is deposited, a contact hole is formed, and the source electrode 20 is formed.
By performing steps such as formation of S and the drain electrode 20D, the structure shown in FIG. 1C is obtained.

In this embodiment, a pair of sidewall-type floating gate electrodes 17a and 17b provided on both sides of the control gate electrode 14 are used as floating gate electrodes for storing electric charges. ), One floating gate electrode 17 provided on one side of the control gate electrode 14 (on the source region 24 or on the drain region 25) may be used. The presence or absence of charge accumulation by the single floating gate electrode 17 changes the resistance of the impurity diffusion layer located immediately below the floating gate electrode 17, whereby the value of the drain current at the time of data reading can be detected. Can be changed at the level. One floating gate electrode 17
In a non-volatile memory cell of the type that accumulates charges, the voltage applied to the control gate electrode is increased so that the source resistance or the drain resistance can be changed within a detectable range by one floating gate electrode 17, or Alternatively, it is preferable to increase the facing area between the floating gate electrode 17 and the diffusion layer. Further, the shape of the floating gate electrode 17 is not limited to the sidewall shape. As shown in FIG. 9A, the floating gate electrode 17a is formed so as to cover a part of the upper part of the control gate electrode 14. May be.

Further, the source region 24 and the drain region 2
9 (b) to adjust the diffusion layer resistance on both sides of FIG.
As shown in (1), one floating gate electrode 17 integrally connected above the control gate electrode 14 may be used.

(Embodiment 2) Hereinafter, FIGS.
With reference to (c), another sidewall storage type nonvolatile memory cell according to the present invention will be described. FIG. 4C shows a cross-sectional structure of the memory cell. In FIG. 4C, the same reference numerals are given to the same components as those of the memory cell in FIG. 1C. A major structural difference between the memory cell of FIG. 1C and the memory cell of this embodiment lies in the configuration of the gate insulating film. Hereinafter, the configuration of the present embodiment will be described focusing on the configuration of the gate insulating film.

The gate insulating film of this embodiment is also formed in the source region 2
A first portion (thickness: 10 nm) 13a covering the drain region 4, a second portion (thickness: 15 nm) 13b covering the drain region 25, and a third portion (thickness: 20 nm) 12 covering the channel region.
have. First portion 13 of gate insulating film of the present embodiment
a and the second portion 13b are both the third portion of the gate insulating film.
It is thinner than the portion 13c. In this regard, the present embodiment
It has a configuration similar to that of the above-described embodiment. However, the configuration of this embodiment is different from the configuration of the above-described embodiment in that the first portion 13a of the gate insulating film is thinner than the second portion 13b. In the present embodiment, the second portion 13b of the gate insulating film
Has a two-layer structure.

The operation of the memory cell according to the present embodiment will be described below with reference to FIGS. 5 (a) to 5 (d).

First, the write operation will be described. Potentials of 10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24 (source electrode 20S), and the drain region 25 (drain electrode 20D), respectively. Then, the potentials of the floating gate electrodes 17a and 17b increase due to capacitive coupling with the control gate electrode 14. If the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a and 17b rises to, for example, about 15 volts due to overshoot. As a result, FIG.
As shown in (a), electrons in the source region 24 tunnel through the first portion 13a of the gate insulating film and are injected into the floating gate electrode 17a. At this time, no FN current flows through the second portion 13b of the gate insulating film. This is because the thickness of the second portion 13b is set to such a thickness that the FN current hardly flows in the second portion 13b even when a potential of 10 V is applied to the control gate electrode 14. After the electrons are injected into the floating gate electrode 17a, even if the potential of the control gate electrode 14 is lowered below 10 volts, the electrons injected into the floating gate electrode 17a are surrounded by the insulating film. Is retained.

Next, a case where electrons are injected into the floating gate electrodes 17a and 17b on both sides of the control gate electrode 14 will be described. In this case, the control gate electrode 14 and the source region 24
And 15 volts, 0 volts, and 0 volts, respectively, to the drain region 25 and the drain region 25, respectively. Then, the floating gate electrode 17 for the source region 24 and the drain region 25
The potentials of a and 17b both rise to the potential level required for FN current generation. If the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the floating gate electrodes 17a and 17
The potential of b rises, for example, to about 20 volts.
As a result, as shown in FIG.
4 and the electrons in the drain region 25 tunnel through the first and second portions of the gate insulating film and pass through.
It is injected into the floating gate electrodes 17a and 17b on both sides.
After the electrons are injected into the floating gate electrodes 17a and 17b, even if the potential of the control gate electrode 14 is lowered below 15 volts, the floating gate electrode is surrounded by the insulating film.
The injected electrons are retained.

FIG. 6 shows floating gate electrodes 17a and 17b.
Of the charge (Q (c)) accumulated by the control gate electrode 1
4 to the voltage (V_CG). Voltage V_CGIs the
1, the charge amount Q (c) is equal to the voltage V1.
_CGIncreases in proportion to the voltage V _CGIs equal to the first voltage V1.
In this case, the charge amount Q (c) becomes equal to Q1. On the other hand,
Pressure V_CGIs between the first voltage V1 and the second voltage V2
At this time, the charge amount Q (c) is_CGIncreases in proportion to
Voltage V_CGIs equal to the second voltage V2, the charge amount Q
(C) becomes equal to the voltage Q2. Voltage V_CGIs the first
When the voltage is between the voltage V1 and the second voltage V2, the voltage V_CGof
As the charge increases, the charge amount Q (c) sharply increases. This reason
The reason is the voltage V_CGIs less than the first voltage V1,
Although electrons were injected only into the idle gate electrode
On the other hand, the voltage V_CGAre greater than or equal to the first voltage V1,
Electrons are injected into the floating gate electrode
That's why.

As described above, in the memory cell transistor of this embodiment, only one of the pair of floating gate electrodes 17a and 17b is in the electron accumulation state, both of them are in the electron accumulation state, or both of them are in the electron accumulation state. Three states can be taken depending on whether the state is the non-accumulation state. Thus, according to the present embodiment, any one of the ternary logic data “0”, “1”, and “2” can be written in each memory cell. In order to inject electrons into both or one of the pair of floating gate electrodes 17a and 17b, the thickness of the first portion 13
a, the thickness 13b of the second portion, and the magnitude of the potential (first potential and second potential) applied to the control gate electrode 14 must be adjusted. That is, at the first potential (eg, 10 volts), electrons are injected into only one floating gate electrode (eg, 17a), and at the second potential (eg, 15 volts), electrons are injected into both floating gate electrodes 17a and 17b. Are implanted, the first and second potentials and the thickness of the first portion 13a and the second portion 13b of the gate insulating film are determined.

Next, the read operation will be described. The reading operation in this embodiment is performed substantially in the same manner as the reading operation in the above-described embodiment. That is, the control gate electrode 14, the source region 24, and the drain region 25
5 volts, 0 volts, and 1 volts, respectively, are applied to form conduction channels 29, as shown in FIG. 5 (c). Then, the source region 24 and the drain region 2
The magnitude of the current (drain current) flowing between 5 is detected. The magnitude of the drain current changes according to the magnitude of the parasitic resistances 31a and 31b shown in FIG. More specifically, the drain current increases in the order of the case where none of the floating gate electrodes 17a and 17b stores electrons, the case where one of them accumulates, and the case where both accumulate. Figure 7 shows the relationship between drain current and (I _D) and the drain voltage (V _D). As can be seen from FIG. 7, data "0", "1" and "2" are identified according to the magnitude of the drain current.

The erasing operation in this embodiment is similar to that shown in FIG.
As shown in (d), the operation is substantially the same as the erase operation in the above-described embodiment. However, in order to emit electrons from both the floating gate electrodes 17a and 17b, the voltage applied to the control gate electrode 14 is adjusted to, for example, -15 volts.

Next, referring to FIGS. 4A to 4C,
A method for manufacturing the above memory cell will be described.

First, after forming a relatively thick oxide film (thickness: 20 nm) to be the third portion 13c of the gate oxide film on the upper surface of the silicon substrate 11, a polycrystalline silicon film is formed on the oxide film by CVD. Deposit. This oxide film is preferably formed by a thermal oxidation method from the viewpoint of reliability.
To further improve the reliability, the surface of the oxide film may be nitrided.

Next, the control gate electrode 14 is formed by patterning the polycrystalline silicon film into a predetermined wiring shape by a photolithography step and an etching step. After etching the polycrystalline silicon film, the oxide film located in a region other than the region below the control gate electrode 14 is also continuously removed. Thus, as shown in FIG. 4A, a thick oxide film (the third portion 13 of the gate insulating film) is formed.
c) and the control gate electrode 14 thereon covers the channel region of the memory cell transistor in the silicon substrate 11.

Next, arsenic ions are implanted into the surface of the silicon substrate 11 using the control gate electrode 14 as a mask, and the high-concentration impurity diffusion regions (source region 24 and drain region 25) are self-aligned with the control gate electrode 14. It is formed.

An insulating film for separating the floating gate electrodes 17 a and 17 b from the control gate electrode 14 is formed on the control gate electrode 1.
4, a thin oxide film is formed on the exposed surface of the silicon substrate 11. This thin oxide film is the first portion 13a and the second portion 13b of the gate insulating film.

Next, a step of making the thickness of the second portion 13b of the gate insulating film larger than the thickness of the first portion 13a is performed.
As a method of selectively increasing the thickness of the second portion 13b of the gate insulating film, for example, the following method is available.

(1) After forming a thin insulating film on a region including the first portion and the second portion of the gate insulating film, an etching mask is formed only on the second portion of the gate insulating film. Thereafter, by etching the thin insulating film located in a region where the etching mask is not covered, the thin insulating film can be left on the second portion of the gate insulating film. As a result, the thickness of the second portion of the gate insulating film becomes larger than the thickness of the first portion by the thickness of the thin insulating film.

(2) After forming an oxidation preventing layer (for example, a layer made of a silicon nitride film) in a region other than the second portion 13b of the gate insulating film, a thermal oxidation step is performed. A thermal oxide film grows by this thermal oxidation step, and the thickness of the second portion 13b of the gate oxide film that is not covered with the oxidation prevention layer increases by the grown thickness.

After the thickness of the second portion 13b of the gate insulating film is made larger than the thickness of the first portion 13a by any of the above methods, the first and second portions of the gate insulating film are formed by the CVD method. Is deposited on silicon substrate 11 so as to cover. Next, this polycrystalline silicon film is etched from its upper surface without using a mask by a highly anisotropic etching technique, so that the polycrystalline silicon film located in a region other than the side portion of the control gate electrode 14 is formed. Is removed, thereby forming sidewall type floating gate electrodes 17a and 17b on the sides of the control gate electrode 14 (FIG. 4B).

After that, using an ordinary technique, the interlayer insulating film 18 is deposited, a contact hole is formed, and the source electrode 20 is formed.
By performing steps such as formation of S and the drain electrode 20D, the structure shown in FIG. 4C is obtained.

(Embodiment 3) Referring to FIG.
A description will be given of still another sidewall storage type nonvolatile memory cell according to the present invention. FIG. 10 shows a cross-sectional structure of the memory cell. In FIG. 10, the same components as those of the memory cell in FIG. 1C are given the same reference numerals. The main difference in structure between the memory cell of FIG. 1C and the memory cell of this embodiment lies in the configuration of the insulating film provided between the control gate electrode and the floating gate electrode. Hereinafter, the configuration of the present embodiment will be described focusing on the configuration of the insulating film.

The thickness of the insulating film provided between the first floating gate electrode 17a and the control gate electrode 14 is as follows.
5 nm . On the other hand, the thickness of the insulating film provided between the second floating gate electrode 17b and the control gate electrode 14 is 15 nm. The insulating film provided between the first floating gate electrode 17a and the control gate electrode 14 has a two-layer structure. The second layer is an insulating sidewall provided on the left side of the control gate electrode. (Thickness: 2.5 nm)
22. In order to form the insulating sidewall 22 only on the control gate electrode 14 side, first, an insulating sidewall is formed on both sides of the control gate electrode 14 by a known method, and then a pattern exposing the right sidewall is formed. The right side wall may be selectively etched using the above photoresist. In order to perform this selective etching with good controllability, the control gate electrode 14 is required.
Is preferably formed from a material different from the material of the insulating film 12 that directly covers the insulating sidewalls 22.

According to the above configuration, the first floating gate electrode 1
7a and the degree of capacitive coupling between the control gate electrode 14
This will be different from the degree of capacitive coupling between the second floating gate electrode 17b and the control gate electrode 14. Therefore, when a certain potential is applied to the control gate electrode 14, the potential of the first floating gate electrode 17a and the potential of the second floating gate electrode 17b show different values. This means that the first floating gate electrode 17a and the source region 2
4 of the gate insulating film 13 located between
Is applied to the first portion of the gate insulating film 13 located between the second floating gate electrode 17a and the drain region 25.
This means that the voltages applied to the part 13b are different.
In this point, the present embodiment is different from the first embodiment.

Next, the write operation of the nonvolatile memory cell of this embodiment will be described. Potentials of 10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24 (source electrode 20S), and the drain region 25 (drain electrode 20D), respectively. Then, the potentials of the floating gate electrodes 17a and 17b increase due to capacitive coupling with the control gate electrode 14. As a result, electrons in the source region 24 tunnel through the first portion 13a of the gate insulating film, and are injected into the floating gate electrode 17a. At this time, the second portion 13b of the gate insulating film
, No FN current flows. That is, even if a potential of 10 volts is applied to the control gate electrode 14, the floating gate electrode 17
b is relatively small, so that FN
The second portion 13 has a voltage at which a current hardly flows.
This is because it is applied to b. After the electrons are injected into the floating gate electrode 17a, even if the potential of the control gate electrode 14 is lowered below 10 volts,
Since a is surrounded by an insulating film, the floating gate electrode 17a
The electrons injected into are kept.

Next, a case where electrons are injected into the floating gate electrodes 17a and 17b on both sides of the control gate electrode 14 will be described. In this case, the control gate electrode 14 and the source region 24
And 15 volts, 0 volts, and 0 volts, respectively, to the drain region 25 and the drain region 25, respectively. Then, the floating gate electrode 17 for the source region 24 and the drain region 25
The potentials of a and 17b both rise to the potential level required for FN current generation. As a result, the electrons in the source region 24 and the drain region 25 are transferred to the first region of the gate insulating film.
The tunneling passes through the portion and the second portion, and is injected into the floating gate electrodes 17a and 17b on both sides. After the electrons are injected into the floating gate electrodes 17a and 17b, even if the potential of the control gate electrode 14 is lowered below 15 volts, the injected electrons are retained because the floating gate electrode is surrounded by the insulating film. .

As described above, in the memory cell transistor of the present embodiment, similarly to the above-described embodiment, only one of the pair of floating gate electrodes 17a and 17b is in the electron accumulation state, or both of them are in the electron accumulation state. , Or both of them are in the non-accumulation state. Thus, according to the present embodiment, ternary logic data "
Any one of “0”, “1”, and “2” can be written to each memory cell.

The reading operation in this embodiment is the same as the reading operation in the above-described embodiment (FIGS.
(See (d)). Further, the erasing operation according to the present embodiment is executed in substantially the same manner as the erasing operation according to the above-described embodiment.

A method for manufacturing the memory cell of this embodiment,
The difference between the method of manufacturing the memory cell of the first embodiment and the method of manufacturing the memory cell of the first embodiment is that the first and second floating gate electrodes 17a and 17b
Prior to the step of forming a gate insulating film, there is a step of selectively increasing only the thickness of the source-side insulating film.

In this embodiment, the control gate electrode 14 and the first
The thickness of the insulating film that capacitively couples the floating gate electrode 17a and the thickness of the insulating film that capacitively couples the control gate electrode 14 and the second floating gate electrode 17b are different from each other. Thus, the degree of capacitive coupling between the control gate electrode 14 and the first floating gate electrode 17a is different from the degree of capacitive coupling between the control gate electrode 14 and the first floating gate electrode 17a. .

The degree of capacitive coupling between the control gate electrode 14 and the first floating gate electrode 17a
In order to make the degree of capacitive coupling between the first and second floating gate electrodes 17a different from each other, in addition to varying the thickness of the insulating film, the dielectric constant of the left and right insulating films may be changed. Good.

(Embodiment 4) FIG. 11D shows a sectional structure of still another side wall accumulation type nonvolatile memory cell according to the present invention. Hereinafter, the present invention will be described for a memory cell manufactured using a CMOS process having a design rule (minimum dimension) of 0.5 to 1.0 μm.

This memory cell has a p-type silicon substrate 11
An n-type source region 24 and an n-type drain region 25 which are provided in an upper surface region of each other and are opposed to each other at a certain distance (about 0.25 μm);
5 and a channel region located between them. The source region 24 and the drain region 25 are typically impurity diffusion regions having a thickness of about 0.1 μm, and the surface concentration of the n-type impurity is 10 ²⁰ to 10 ²¹ cm ⁻³ . The silicon substrate 11 is doped with a p-type impurity of about 10 ¹⁷ cm ⁻³ .

The first gate insulating film is provided on the silicon substrate 11. The first gate insulating film has a first portion (thickness: 10 nm) 13 a covering the source region 24 and a second portion (thickness: 10 nm) 13 covering the drain region 25.
b, and a third portion covering the channel region (thickness: 20 n
m) 12. In this embodiment, the first portion 13a and the second portion 13b of the first gate insulating film have the same thickness. First portion 13 of first gate insulating film
The thickness of “a” and the second portion 13 b may be a thickness (about 5 nm) or more at which a Fowler-Nordheim current (FN current) can flow. First portion 13 of first gate insulating film
a, a first floating gate electrode 17a is provided on the first floating gate electrode 17a.
A second floating gate electrode 17b is provided on the second portion 13b of the gate insulating film. Further, a control gate electrode 14 is provided on the third portion 13c of the first gate insulating film. The control gate electrode 14 is formed of an insulating film,
And are electrically insulated from the second floating gate electrodes 17a and 17b. The control gate electrode 14 and the floating gate electrodes 17a and 17b can be typically formed of polycrystalline silicon, polycide, or the like.

The gate length (the length measured along the channel length direction) of the control gate electrode 14 of this embodiment is about 0.25.
μm, and the gate width (length measured along a direction perpendicular to the channel length direction) is about 2 μm. The gate length of the floating gate electrodes 17a and 17b is about 0.1 to 0.15 μm, and the gate width is equal to the gate width of the control gate electrode 14.

The memory cell of this embodiment further has a second gate insulating film covering the first floating gate electrode 17a and the second floating gate electrode 17b. This second gate insulating film has a first portion (thickness:
12.5 nm ) 130a and a second portion (thickness: 12.5 nm ) 130b covering the second floating gate electrode 17b. Further, the first portion 130 of the second gate insulating film
The third floating gate electrode 17c is provided on the second gate insulating film, and the fourth floating gate electrode 17c is provided on the second portion 130b of the second gate insulating film.
A floating gate electrode 17d is provided.

The third and fourth floating gate electrodes 17c
And 17d are capacitively coupled to the control gate electrode 14 by the third portion 130c of the second gate insulating film and the insulating film 12. The second and third floating gate electrodes 17c and 17d can also typically be formed from polycrystalline silicon or the like.

The thickness of the third portion 13c of the first gate insulating film may be larger than the total thickness of the first portion 13a of the first gate insulating film and the first portion 130a of the second gate insulating film.

As shown in FIG. 11D, the memory cell of the present embodiment has an interlayer insulating film 18 formed on a silicon substrate 11.
Covered by A contact hole reaching the source region 24 and the drain region 25 is provided in the interlayer insulating film 18. In addition, on the substrate 11, a source electrode 20S that contacts the source region 24 via a contact hole and a drain electrode 20D that contacts the drain region 25 are provided.

Next, a method for manufacturing the above-mentioned memory cell will be described with reference to FIGS.

First, the third portion 13c of the first gate oxide film
After a relatively thick oxide film (thickness: 20 nm) is formed on the upper surface of the silicon substrate 11, a polycrystalline silicon film is deposited on the oxide film by a CVD method. The polycrystalline silicon film is patterned into a predetermined wiring shape by a photolithography process and an etching process, and the control gate electrode 14 is formed. After etching the polycrystalline silicon film, the thick oxide film located in a region other than the region below the control gate electrode 14 is also continuously removed. Thus, the thick oxide film (the third portion 13c of the gate insulating film) and the control gate electrode 14 thereon cover the channel region of the memory cell transistor in the silicon substrate 11, as shown in FIG. It will be.

Next, arsenic ions are implanted into the surface of the silicon substrate 11 using the control gate electrode 14 as a mask, and the high-concentration impurity diffusion regions (source region 24 and drain region 25) are self-aligned with the control gate electrode 14. It is formed.

An insulating film (thickness: 15 nm) 1 for separating the floating gate electrodes 17a and 17b from the control gate electrode 14
2 is formed on the side and top surfaces of the control gate electrode 14, and then a thin oxide film (thickness: 10 nm) is formed on the exposed surface of the silicon substrate 11. This thin oxide film is the first portion 13a and the second portion 13b of the first gate insulating film.

Thereafter, a polycrystalline silicon film is deposited on the silicon substrate 11 so as to cover the thin oxide film by the CVD method. Next, by anisotropic etching technology,
By etching this polycrystalline silicon film from its upper surface without using a mask, the polycrystalline silicon film located in a region other than the side portion of the control gate electrode 14 is removed,
Thereby, the side wall type floating gate electrode 17 is formed.
a and 17b are formed on the sides of the control gate electrode 14 (FIG. 11B).

Next, after depositing an oxide film to be a second gate insulating film on the silicon substrate 11 by the CVD method,
Further, a polycrystalline silicon film is deposited on the silicon substrate 11 by a CVD method. Thereafter, this polycrystalline silicon film is etched from its upper surface without using a mask by a highly anisotropic etching technique, so that the polycrystalline silicon film located in a region other than the side portion of control gate electrode 14 is formed. Is removed, thereby forming sidewall-type third and fourth floating gate electrodes 17a and 17b on the sides of the control gate electrode 14 (FIG. 11D).

Thereafter, the interlayer insulating film 18 is deposited, a contact hole is formed, and the source electrode 20 is formed using a usual technique.
By performing steps such as formation of S and the drain electrode 20D, the structure shown in FIG. 11D is obtained.

The operation of the present memory cell will be described below with reference to FIGS. 12 (a) and 12 (b).

First, the write operation will be described. Potentials of 10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24 (source electrode 20S), and the drain region 25 (drain electrode 20D), respectively. Then, the potential of the control gate electrode 14 with respect to the source region 24 and the drain region 25 increases to 10 volts. The potentials of the floating gate electrodes 17a and 17b increase to a level required for generating an FN current due to capacitive coupling with the control gate electrode 14. As a result, as shown in FIG. 12A, the source region 24 and the drain region 25 are formed.
Are located in the first and second gate insulating films, respectively.
Tunneling through the part and passing through it, the control gate electrode 1
4 are injected into the floating gate electrodes 17a and 17b on both sides. After the electrons are injected into the floating gate electrodes 17a and 17b, even if the potential of the control gate electrode 14 is lowered below 10 volts, each of the floating gate electrodes 17a and 17b is injected because it is surrounded by the insulating film. The electrons are held in the floating gate electrodes 17a and 17b.

Of the plurality of memory cells, a potential of 10 volts is selectively applied to the control gate electrode 14 of a specific memory cell, and 0 V is applied to the control gate electrode 14 of an unselected memory cell. Give a potential of volts. Thus, electrons can be stored only in the floating gate electrodes 17a and 17b of the selected memory cell.

Next, the control gate electrode 14 and the source region 2
4 (source electrode 20S) and drain region 25 (drain electrode 20D) are applied with potentials of 12.5 volts, 0 volts, and 0 volts, respectively. Then, the source area 2
4 and the potential of the control gate electrode 14 with respect to the drain region 25 rise to 12.5 volts. Floating gate electrode 17
The potentials at a, 17b, 17c, and 17d rise due to capacitive coupling with the control gate electrode 14, thereby increasing the level required to generate an FN current in the first gate insulating film and the second gate insulating film. To increase. As a result, as shown in FIG. 12B, the electrons in the source region 24 and the electrons in the drain region 25 pass through the first and second portions of the first gate insulating film by tunneling, respectively.
The floating gate electrodes 17a on both sides of the control gate electrode 14
And 17b, are further tunneled through the first and second portions 130a and 130b of the second gate insulating film, and the third and fourth floating gate electrodes 17c are formed.
And 17d.

In the memory cell of this embodiment, the thickness of the third portion 13c of the first gate insulating film is equal to the first portion of the first gate insulating film.
The thickness 13a of the portion (or the thickness 13b of the second portion) and the thickness 130a (or the second thickness) of the first portion of the second gate insulating film.
It is manufactured to be thicker than the sum of the thicknesses 130b) of the portions.

After electrons are injected into the floating gate electrodes 17a, 17b, 17c and 17d, even if the potential of the control gate electrode 14 is lowered below 10 volts, the floating gate electrode 1
Since each of 7a, 17b, 17c and 17d is surrounded by an insulating film, the injected electrons are
a, 17b, 17c and 17d.

As described above, in the memory cell transistor of this embodiment, the pair of floating gate electrodes 17a and 17b are in the electron accumulation state or the pair of floating gate electrodes 1
There are three possible states depending on whether 7a, 17b, 17c and 17d are in the electron accumulation state or both are in the non-accumulation state. Thus, according to the present embodiment, any one of the ternary logic data “0”, “1”, and “2” can be written in each memory cell.

In the memory cell of this embodiment, the relationship between the accumulated charge and the applied voltage is the same as the relationship shown in FIG. The relationship between the drain current and the drain voltage is similar to that shown in FIG. Thus, the reading operation in this embodiment is performed substantially in the same manner as the reading operation in the above-described embodiment. Further, the erasing operation according to the present embodiment is executed in substantially the same manner as the erasing operation according to the above-described embodiment.

Embodiment 5 Hereinafter, referring to FIG.
Another sidewall storage type nonvolatile memory cell according to the present invention will be described. FIG. 13 shows a cross-sectional structure of the memory cell. In FIG. 13, the same reference numerals are given to the same components as those of the memory cell in FIG. 11D. The major structural difference between the memory cell of FIG. 11D and the memory cell of this embodiment lies in the configuration of the first and second gate insulating films. Hereinafter, the configuration of this embodiment will be described focusing on the configuration of these gate insulating films.

The first gate insulating film of this embodiment is different from that of FIG.
As in the case of the memory cell of (d), a first portion (thickness: 10 nm) 13a covering the source region 24, a second portion (thickness: 12.5 nm) 13b covering the drain region 25, and a second portion (thickness: 12.5 nm) covering the channel region. It has three portions (thickness: 20 nm) 12. Further, both the first portion 13a and the second portion 13b of the first gate insulating film of the present embodiment are thinner than the third portion 13c of the first gate insulating film. In this regard, the present embodiment has a configuration similar to that of the above-described embodiment. However, in the present memory cell, the first portion 1 of the first gate insulating film 1
The configuration of this embodiment differs from the configuration of the above-described embodiment in that 3a is thinner than the second portion 13b. First of this embodiment
The second portion 13b of the gate insulating film has a two-layer structure.

The second gate insulating film of the present embodiment has a first portion (having a thickness of 17.5 n) covering the first floating gate electrode.
m) and a second portion (thickness: 1) covering the second floating gate electrode
5 nm), but the thickness of the first portion is greater than the thickness of the second portion. The first part of the second gate insulating film is 2
It has a layered structure.

FIGS. 14 (a), (b), and FIG.
The operation of the present memory cell will be described with reference to (a) to (c).

First, the write operation will be described. Potentials of 10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24 (source electrode 20S), and the drain region 25 (drain electrode 20D), respectively. Then, the potentials of the floating gate electrodes 17a, 17b, 17c and 17d increase due to capacitive coupling with the control gate electrode 14. If the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the floating gate electrodes 17a, 17b,
The potential of 17c and 17d rises, for example, to about 15 volts. As a result, as shown in FIG. 14A, electrons in the source region 24 tunnel through the first portion 13a of the first gate insulating film and are injected into the floating gate electrode 17a. At this time, no FN current flows through the second portion 13b of the first gate insulating film. This is because the thickness of the second portion 13b is set to such a thickness that the FN current hardly flows in the second portion 13b even when a potential of 10 V is applied to the control gate electrode 14. After electrons are injected into the floating gate electrode 17a,
Even if the potential of the control gate electrode 14 is lowered below 10 volts, the electrons injected into the floating gate electrode 17a are retained because the floating gate electrode 17a is surrounded by the insulating film.

Next, a case where electrons are injected into the floating gate electrodes 17a and 17b on both sides of the control gate electrode 14 will be described. In this case, the control gate electrode 14 and the source region 24
And 12.5 volts in the drain region 25, respectively.
Apply 0 volt and 0 volt potential. Then, the potentials of the floating gate electrodes 17a, 17b, 17c and 17d with respect to the source region 24 and the drain region 25 increase.
Assuming that the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a, 17b, 17c and 17d increases to, for example, about 15 volts due to overshoot. As a result, as shown in FIG. 14B, electrons in the source region 24 and the drain region 25 tunnel through the first portion 13a and the second portion 13b of the first gate insulating film and pass through both sides. It is injected into the floating gate electrodes 17a and 17b. At this time, the configuration is such that electrons are not injected into the floating gate electrodes 17c and 17d due to the presence of the second gate insulating film. Even after the electrons are injected into the floating gate electrodes 17a and 17b, even if the potential of the control gate electrode 14 is lowered below 12.5 volts, the injected electrons are retained because the floating gate electrode is surrounded by the insulating film. Is done.

Next, the control gate electrode 14 and the source region 2
4 (source electrode 20S) and drain region 25 (drain electrode 20D) are given potentials of 15 volts, 0 volts, and 0 volts, respectively. Then, the floating gate electrode 1
The potentials of 7c and 17d increase due to capacitive coupling with the control gate electrode 14. Assuming that the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17c and 17d rises to, for example, about 17.5 volts due to overshoot. As a result, as shown in FIG.
The electrons in the source region 24 correspond to the second in the first gate insulating film.
Tunneling passes through the portion 13a and is injected into the first floating gate electrode 17a. At this time, simultaneously, the electrons in the drain region 25 are transferred to the second portion 13 of the first gate insulating film.
a and the second portion 130b of the second gate insulating film are tunneled through and pass through the second and fourth floating gate electrodes 17a.
b and 17d. At this time, no FN current flows through the first portion 130a of the second gate insulating film. That is, even when a potential of 15 volts is applied to the control gate electrode 14, the second portion of the second gate insulating film has a thickness such that FN current hardly flows in the second portion 130a.
This is because the thickness of the portion 130a is set. After the electrons are injected into the floating gate electrodes 17a, 17b and 17d, the electrons injected into the floating gate electrodes 17a, 17b and 17d are retained even if the potential of the control gate electrode 14 is lowered below 15 volts.

Next, the four floating gate electrodes 17a, 17
The case where electrons are injected into b, 17c and 17d will be described. In this case, 17.5 volts and 0
Apply a volt and 0 volt potential. Then, the floating gate electrode 1 for the source region 24 and the drain region 25
7a, 17b, 17c and 17d all have F
It rises to the potential level required for N current generation. Assuming that the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a and 17b increases to, for example, about 20 volts due to overshoot. As a result, as shown in FIG. 15B, electrons in the source region 24 and the drain region 25 pass through the first and second gate insulating films by tunneling, and the floating gate electrodes 17a, 17b, 17c and 17
d. Floating gate electrodes 17a, 17b, 17
After the electrons are injected into c and 17d, the control gate electrode 1
Even if the potential of 4 is lowered below 20 volts, the injected electrons are retained.

FIG. 16 and FIG. 17 are graphs of the present embodiment, and correspond to the graphs of FIG. 6 and FIG.
As shown in FIGS. 15 and 16, according to the memory cell of the present embodiment, quinary data can be stored.

The erasing operation is performed substantially in the same manner as the erasing operation in the above-described embodiment (FIG. 15).
(C)).

The method of manufacturing the present memory cell and FIG.
The difference from (a) to the manufacturing method shown in FIG. 12E is that the step of forming the first and second gate insulating films of the memory cell of the present embodiment selectively sets the thickness of the first portion or the second portion. Or a step of reducing the thickness.

(Embodiment 6) FIG. 18D shows a cross-sectional structure of still another side wall storage type nonvolatile memory cell according to the present invention. Hereinafter, the present invention will be described for a memory cell manufactured using a CMOS process having a design rule (minimum dimension) of 0.5 to 1.0 μm.

This memory cell is a p-type silicon substrate 11
An n-type source region 24 and an n-type drain region 25 which are provided in an upper surface region of each other and are opposed to each other at a certain distance (about 0.25 μm);
5 and a channel region located between them. The source region 24 and the drain region 25 are typically impurity diffusion regions having a thickness of about 0.1 μm, and the surface concentration of the n-type impurity is 10 ²⁰ to 10 ²¹ cm ⁻³ . The silicon substrate 11 is doped with a p-type impurity of about 10 ¹⁷ cm ⁻³ .

On the silicon substrate 11, a first gate insulating film is provided. This first gate insulating film has a first portion (thickness: 10 nm) 13 covering a part of the source region 24.
a, a second portion (thickness: 1) covering a portion of the drain region 25;
0 nm) 13b and a third portion (thickness: 20 nm) 12 covering the channel region.

Further, on the silicon substrate 11, a second gate insulating film is provided. This second gate insulating film
A first portion (thickness: 15) covering another portion of the source region 24
nm) 130a and a second portion (thickness: 17.5 nm) 130b covering another portion of the drain region 25.

In the present embodiment, the first portion 13a of the first gate insulating film is thinner than the second portion (two-layer structure) 13b,
The first portion (two-layer structure) 130a of the second gate insulating film is
It is formed thinner than the second portion (three-layer structure) 130b. This is done so that the memory cell can store quinary data. In order to store the ternary data, the first portion 13a and the second portion 13b of the first gate insulating film have the same thickness, and the first portion 130a and the second portion 130b of the second gate insulating film have the same thickness. Should be equal in thickness.

The first floating gate electrode 17a is provided on the first portion 13a of the first gate insulating film, and the second floating gate electrode 17b is provided on the second portion 13b of the gate insulating film. Also, the third portion 13c of the gate insulating film
The control gate electrode 14 is provided thereon. The control gate electrode 14 is formed by the insulating film 12 having a thickness of 20 nm.
It is electrically insulated from the first and second floating gate electrodes 17a and 17b.

A third floating gate electrode 17c is provided on the first portion 130a of the second gate insulating film, and a fourth floating gate electrode 1c is provided on the second portion 130b of the second gate insulating film.
7d is provided.

Each of the third floating gate electrode 17c and the fourth floating gate electrode 17d is an insulating film (thickness: 20 n
m) It is electrically insulated from the first and second floating gate electrodes 17a and 17b by 50a and 50b.

Further, the present memory cell is covered with an interlayer insulating film 18 formed on the silicon substrate 11. A contact hole reaching the source region 24 and the drain region 25 is provided in the interlayer insulating film 18. In addition, on the substrate 11, a source electrode 20S that contacts the source region 24 via a contact hole and a drain electrode 20D that contacts the drain region 25 are provided.

According to this embodiment, the third and fourth floating gate electrodes 17c and 17d are connected to the source region 24 and the drain region 25 via the thin second gate insulating film, respectively.
Facing. Therefore, the third and fourth floating gate electrodes 17c and 17d can receive electrons from the source region 24 and the drain region 25 via the second gate insulating film, respectively. In other words, the first and second
Charges do not move between the floating gate electrodes 17a and 17b and the third and fourth floating gate electrodes 17c and 17d.

FIGS. 19A, 19B and 20
The operation of the present memory cell will be described with reference to (a) to (c).

First, the write operation will be described. Potentials of 10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24 (source electrode 20S), and the drain region 25 (drain electrode 20D), respectively. Then, the potentials of the floating gate electrodes 17a and 17b increase due to capacitive coupling with the control gate electrode 14. If the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a and 17b rises to, for example, about 15 volts due to overshoot. As a result, FIG.
As shown in (a), electrons in the source region 24 tunnel through the first portion 13a of the first gate insulating film and are injected into the floating gate electrode 17a.
At this time, the second portion 13b of the first gate insulating film
No FN current flows through the gate insulating film. It is 10
Even if a voltage of volt is applied to the control gate electrode 14, the thicknesses of the second gate insulating film and the second gate insulating film are set to such a thickness that FN current hardly flows in the second portion 13b and the second gate insulating film. Because it is. Floating gate electrode 17a
After the electrons are injected into the gate, the potential of the control gate electrode 14 is set to 1
Even when the voltage is lowered to less than 0 volt, the electrons injected into the floating gate electrode 17a are retained because the floating gate electrode 17a is surrounded by the insulating film.

Next, a case where electrons are injected into the floating gate electrodes 17a and 17b will be described. In this case, 12.5 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24, and the drain region 25, respectively. Then, the source region 24 and the drain region 2
5, the potential of the floating gate electrodes 17a and 17b is
In both cases, the potential rises to the potential level required for generating the FN current. If the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a and 17b rises to, for example, about 15 volts due to overshoot. As a result, FIG.
As shown in (b), electrons in the source region 24 and the drain region 25 tunnel through the first and second portions of the first gate insulating film and are injected into the floating gate electrodes 17a and 17b. You. Floating gate electrode 1
After the electrons are injected into 7a and 17b, even if the potential of the control gate electrode 14 is lowered below 12.5 volts, the injected electrons are retained because the floating gate electrode is surrounded by the insulating film.

Next, the control gate electrode 14 and the source region 2
4 (source electrode 20S) and drain region 25 (drain electrode 20D) are given potentials of 15 volts, 0 volts, and 0 volts, respectively. Then, the floating gate electrode 1
The potentials of 7c and 17d increase due to capacitive coupling with the control gate electrode 14. Assuming that the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17c and 17d rises to, for example, about 17.5 volts due to overshoot. As a result, as shown in FIG.
The electrons in the source region 24 correspond to the second in the first gate insulating film.
Tunneling passes through the portion 13a and is injected into the first floating gate electrode 17a. At this time, simultaneously, the electrons in the drain region 25 are transferred to the second portion 13 of the first gate insulating film.
a and the second portion 130b of the second gate insulating film are tunneled through, and injected into the second and fourth floating gate electrodes 17b and 17d, respectively. At this time, the second
No FN current flows through the first portion 130a of the gate insulating film. It applies a potential of 15 volts to the control gate electrode 1
4, the second portion 130a of the second gate insulating film
This is because the thickness of the second portion 130a of the second gate insulating film is set to a thickness at which almost no FN current flows. After the electrons are injected into the floating gate electrodes 17a, 17b and 17d, the electrons injected into the floating gate electrodes 17a, 17b and 17d are retained even if the potential of the control gate electrode 14 is lowered below 15 volts.

Next, the four floating gate electrodes 17a, 17
The case where electrons are injected into b, 17c and 17d will be described. In this case, 17.5 volts and 0
Apply a volt and 0 volt potential. Then, the floating gate electrode 1 for the source region 24 and the drain region 25
7a, 17b, 17c and 17d all have F
It rises to the potential level required for N current generation. Assuming that the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a, 17b, 17c, and 17d increases to, for example, about 20 volts due to overshoot. As a result, FIG.
As shown in FIG. 2B, electrons in the source region 24 and the drain region 25 tunnel through the first and second gate insulating films, respectively, to form the floating gate electrode 17.
a, 17b, 17c and 17d. After the electrons are injected into the floating gate electrodes 17a, 17b, 17c and 17d, the injected electrons are retained even if the potential of the control gate electrode 14 is lowered below 20 volts.

As described above, according to the memory cell of this embodiment, it is possible to store quinary data. The erasing operation is performed substantially in the same manner as the erasing operation in the above-described embodiment (FIG. 20C).

Next, a method of manufacturing the above-mentioned memory cell will be described with reference to FIGS. 18 (a) to 18 (d).

First, the third portion 13c of the first gate oxide film
After a relatively thick oxide film (thickness: 20 nm) is formed on the upper surface of the silicon substrate 11, a polycrystalline silicon film is deposited on the oxide film by a CVD method. The polycrystalline silicon film is patterned into a predetermined wiring shape by a photolithography process and an etching process, and the control gate electrode 14 is formed. After etching the polycrystalline silicon film, the thick oxide film located in a region other than the region below the control gate electrode 14 is also continuously removed. Thus, the thick oxide film (the third portion 13c of the first gate insulating film) and the control gate electrode 14 thereon are formed on the silicon substrate 11 in the channel region of the memory cell transistor, as shown in FIG. Will be covered.

Next, arsenic ions are implanted into the surface of the silicon substrate 11 using the control gate electrode 14 as a mask, and the high-concentration impurity diffusion regions (source region 24 and drain region 25) are self-aligned with the control gate electrode 14. It is formed.

Insulating film (thickness: 15 nm) 1 for separating floating gate electrodes 13a and 13b from control gate electrode 14
2 is formed on the side surface of the control gate electrode 14 and then a thin oxide film (thickness: 10
nm). This thin oxide film forms a first portion 13a of the first gate insulating film, a part of the second portion 13b,
This constitutes a part of the gate insulating film.

In this thin oxide film, the drain region 25
Selectively depositing another thin insulating film on the portion located above the first portion of the first gate insulating film;
A second portion 13c thicker than 3a is formed.

After that, a polycrystalline silicon film is deposited on the silicon substrate 11 so as to cover the thin oxide film by the CVD method. Next, by anisotropic etching technology,
By etching this polycrystalline silicon film from its upper surface without using a mask, the polycrystalline silicon film located in a region other than the side portion of the control gate electrode 14 is removed,
Thereby, the side wall type floating gate electrode 17 is formed.
a and 17b are formed on the sides of the control gate electrode 14 (FIG. 18B).

Next, the floating gate electrode 17 is formed by the CVD method.
A relatively thick insulating film 50a, 50b is formed on a and 17b. The insulating films 50a and 50b are formed on the floating gate electrodes 17c and 17d and the floating gate electrodes 17a and 17d to be formed next.
7b.

Thereafter, a thin oxide film to be a part of the second gate insulating film is deposited on the thin oxide film on the substrate by the CVD method. At this time, the thickness of the oxide film on the source region 24 is selectively increased. Thus, the second gate insulating films 130a and 130b are formed.

Further, a polycrystalline silicon film is deposited on the substrate 11 by a CVD method so as to cover the second gate insulating film. After that, with the highly anisotropic etching technology,
By etching this polycrystalline silicon film from its upper surface without using a mask, the polycrystalline silicon film located in a region other than the side portion of the control gate electrode 14 is removed,
As a result, the third and fourth sidewall floating gate electrodes 17c and 17d are formed on the sides of the control gate electrode 14 (FIG. 18C).

After that, using an ordinary technique, the interlayer insulating film 18 is deposited, a contact hole is formed, and the source electrode 20 is formed.
By performing steps such as formation of S and the drain electrode 20D, the structure shown in FIG. 18D is obtained.

(Embodiment 7) FIG. 21D shows a sectional structure of still another side wall accumulation type nonvolatile memory cell according to the present invention. Hereinafter, the present invention will be described for a memory cell manufactured using a CMOS process having a design rule (minimum dimension) of 0.5 to 1.0 μm.

This memory cell is a p-type silicon substrate 11
An n-type source region 24 and an n-type drain region 25 which are provided in an upper surface region of each other and are opposed to each other at a certain distance (about 0.25 μm);
5 and a channel region located between them. The source region 24 and the drain region 25 are typically impurity diffusion regions having a thickness of about 0.1 μm, and the surface concentration of the n-type impurity is 10 ²⁰ to 10 ²¹ cm ⁻³ . The silicon substrate 11 is doped with a p-type impurity of about 10 ¹⁷ cm ⁻³ .

On silicon substrate 11, a thin oxide film functioning as a first gate insulating film is provided. The first gate insulating film includes a first portion (thickness: 10 nm) 13a covering a part of the source region 24, a second portion (thickness: 12.5 nm) 13b covering a part of the drain region 25, and a channel region. And a third portion (thickness: 20 nm) 13c that covers the second portion. On the third portion 13c of the first gate insulating film,
A control gate 14 is provided, and the top and side surfaces of the control gate 14 are covered with the thick insulating film 12.

Of the thin insulating films constituting the first portion 13a and the second portion 13b of the first gate insulating film, a pair of thick insulating films 55a and 55b are formed on portions near the control gate 14.
Are formed. The third and fourth floating gate electrodes 17c are formed on the pair of thick insulating films 55a and 55b, respectively.
And 17d are provided.

In this embodiment, the first and second floating gate electrodes 17a and 17b are formed outside the third and fourth floating gate electrodes 17c and 17d. Between the first and second floating gate electrodes 17a and 17b and the third and fourth floating gate electrodes 17c and 17d, third and fourth gate insulating films 135a and 135b are provided, respectively.
Is provided.

In this embodiment, the first portion 13a of the first gate insulating film is formed thinner than the second portion 13b, and the third gate insulating film 135a is formed thicker than the fourth gate insulating film 135b. I have. This is done so that the memory cell can store quinary data. In order to store ternary data, the first portion 13a and the second portion 13b of the first gate insulating film have the same thickness,
In addition, the third gate insulating film and the fourth gate insulating film may have the same thickness.

Further, as shown in FIG. 21D, the present memory cell is covered with an interlayer insulating film 18 formed on a silicon substrate 11. In the interlayer insulating film 18,
A contact hole reaching the source region 24 and the drain region 25 is provided. Also, on the substrate 11,
A source electrode 20S contacting the source region 24 via a contact hole and a drain electrode 20D contacting the drain region 25 are provided.

According to the present embodiment, the third and fourth floating gate electrodes 17c and 17d are each formed of the thick insulating film 55.
The source region 24 and the drain region 25 are opposed to each other via a and 55b. Therefore, the third and fourth floating gate electrodes 17c and 17d are connected to the source region 2 via the first and second floating gate electrodes 17a and 17b, respectively.
4 and the drain region 25. In other words, the first and second floating gate electrodes 17a
And 17b and the source region 24 and the drain region 25, the charge does not move directly.

FIGS. 22 (a) and 22 (b) and FIG.
3 (a) to 3 (c), the operation of the present memory cell will be described.

First, the write operation will be described. Potentials of 10 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24 (source electrode 20S), and the drain region 25 (drain electrode 20D), respectively. Then, the floating gate electrodes 17a, 17b, 17c,
The potential of 17d increases due to capacitive coupling with the control gate electrode 14. When the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the floating gate electrodes 17a, 17b, 1
The potentials of 7c and 17d rise, for example, to about 15 volts. As a result, as shown in FIG. 22A, electrons in the source region 24 tunnel through the first portion 13a of the first gate insulating film and are injected into the floating gate electrode 17a. At this time, no FN current flows through the second portion 13b of the first gate insulating film. The thickness of the second portion 13b is set to a thickness such that almost no FN current flows through the second portion 13b of the first gate insulating film even when a potential of 10 volts is applied to the control gate electrode 14. Because there is. After the electrons are injected into the floating gate electrode 17a, even if the potential of the control gate electrode 14 is lowered below 10 volts, the electrons injected into the floating gate electrode 17a are surrounded by the insulating film. Is retained.

Next, a case where electrons are injected into the floating gate electrodes 17a and 17b will be described. In this case, potentials of 12.5 volts, 0 volts, and 0 volts are applied to the control gate electrode 14, the source region 24, and the drain region 25, respectively. Then, the source region 24 and the drain region 2
5, the potential of the floating gate electrodes 17a and 17b is
Both rise to the potential level required for FN current generation. If the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the floating gate electrodes 17a, 17b, 17c, and 17d are overshot.
Rises to, for example, about 15 volts. As a result, as shown in FIG.
4 and the drain region 25 are tunneled through the first portion 13a and the second portion 13b of the first gate insulating film, and the floating gate electrodes 17a and 17 on both sides.
b. After electrons are injected into the floating gate electrodes 17a and 17b, the potential of the control gate electrode 14 is set to 12.
Even if the voltage drops below 5 volts, the injected electrons are retained because the floating gate electrode is surrounded by the insulating film.

Next, the control gate electrode 14 and the source region 2
4 (source electrode 20S) and drain region 25 (drain electrode 20D) are given potentials of 15 volts, 0 volts, and 0 volts, respectively. Then, the floating gate electrode 1
The potentials of 7a, 17b, 17c and 17d increase due to capacitive coupling with the control gate electrode 14. Assuming that the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a, 17b, 17c, and 17d increases to about 17.5 volts due to overshoot. as a result,
As shown in FIG. 23A, electrons in the source region 24 pass through the second portion 13a of the first gate insulating film by tunneling, and are injected into the first floating gate electrode 17a. At this time, at the same time, the electrons in the drain region 25 are
Tunneling passes through the second portion 13a of the first gate insulating film and the inside of the fourth gate insulating film, and is injected into the second and fourth floating gate electrodes 17b and 17d, respectively. At this time, no FN current flows through the third gate insulating film.
That is, the thickness of the second portion 130a of the second gate insulating film is set to a thickness such that almost no FN current flows in the third gate insulating film even when a potential of 15 volts is applied to the control gate electrode 14. Because. The floating gate electrode 17a,
After the electrons are injected into 17b and 17d, the electrons injected into floating gate electrodes 17a, 17b and 17d are retained even if the potential of control gate electrode 14 is lowered below 15 volts.

Next, the four floating gate electrodes 17a, 17
The case where electrons are injected into b, 17c and 17d will be described. In this case, 17.5 volts and 0
Apply a volt and 0 volt potential. Then, the floating gate electrode 1 for the source region 24 and the drain region 25
7a, 17b, 17c and 17d all have F
It rises to the potential level required for N current generation. Assuming that the rise time of the voltage applied to the control gate electrode 14 is 1 to 2 nanoseconds, the potential of the floating gate electrodes 17a, 17b, 17c, and 17d increases to, for example, about 20 volts due to overshoot. As a result, FIG.
As shown in FIG. 2B, electrons in the source region 24 and the drain region 25 tunnel through the first and second gate insulating films, respectively, to form the floating gate electrode 17.
a, 17b, 17c and 17d. After the electrons are injected into the floating gate electrodes 17a, 17b, 17c and 17d, the injected electrons are retained even if the potential of the control gate electrode 14 is lowered below 20 volts.

As described above, according to the memory cell of this embodiment, it is possible to store quinary data. The erasing operation is performed substantially in the same manner as the erasing operation in the above-described embodiment (FIG. 23C).

Next, a method for manufacturing the above memory cell will be described with reference to FIGS. 21 (a) to 21 (d).

First, the third portion 13c of the first gate oxide film
After a relatively thick oxide film (thickness: 20 nm) is formed on the upper surface of the silicon substrate 11, a polycrystalline silicon film is deposited on the oxide film by a CVD method. The polycrystalline silicon film is patterned into a predetermined wiring shape by a photolithography process and an etching process, and the control gate electrode 14 is formed. After etching the polycrystalline silicon film, the thick oxide film located in a region other than the region below the control gate electrode 14 is also continuously removed. Thus, the thick oxide film (the third portion 13c of the first gate insulating film) and the control gate electrode 14 thereon are formed on the silicon substrate 11 in the channel region of the memory cell transistor, as shown in FIG. Will be covered.

Next, arsenic ions are implanted into the surface of the silicon substrate 11 using the control gate electrode 14 as a mask, and the high-concentration impurity diffusion regions (source region 24 and drain region 25) are self-aligned with the control gate electrode 14. It is formed.

Insulating film (thickness: 20 nm) 1 for separating floating gate electrodes 17a and 17b from control gate electrode 14
2 is formed on the side surface of the control gate electrode 14, and then a thin oxide film (thickness: 1) is formed on the exposed surface of the silicon substrate 11.
0 nm ). This thin oxide film is a film that forms part of the first portion 13a and the second portion 13b of the first gate insulating film. Thereafter, the drain region 2 is formed by the CVD method.
5, a thin oxide film is selectively deposited, thereby forming the second portion 13b of the first gate insulating film.

Next, thick oxide films 55a and 55b are formed on the substrate 11 so as to cover the first portion 13a and the second portion 13b of the first gate insulating film. This thick oxide film 55
a and 55b insulate and isolate the third and fourth floating gate electrodes 17c and 17d from the substrate 11.

After that, the thick oxide film 5 is formed by CVD.
A polycrystalline silicon film is deposited on the silicon substrate 11 so as to cover 5a and 55b. Next, this polycrystalline silicon film is etched from its upper surface without using a mask by a highly anisotropic etching technique, so that the polycrystalline silicon film located in a region other than the side portion of the control gate electrode 14 is formed. Is removed, thereby forming sidewall type floating gate electrodes 17c and 17d on the sides of the control gate electrode 14 (FIG. 21B).

Next, the floating gate electrode 17 is formed by the CVD method.
Third and fourth gate insulating films 135a and 135b are formed on a and 17b, respectively. In this embodiment, the third gate insulating film 135a is replaced with the fourth gate insulating film 135b.
It is formed thicker.

Further, a polycrystalline silicon film is deposited on the substrate 11 by a CVD method so as to cover the third and fourth gate insulating films 135a and 135b. Thereafter, this polycrystalline silicon film is etched from its upper surface without using a mask by a highly anisotropic etching technique, so that the polycrystalline silicon film located in a region other than the side portion of control gate electrode 14 is formed. , Thereby removing the sidewall-type first and second floating gate electrodes 17a and 17b.
Are formed on the sides of the control gate electrode 14 (FIG. 21).
(C)).

Thereafter, the interlayer insulating film 18 is deposited, a contact hole is formed, and the source electrode 20 is formed using a usual technique.
By performing steps such as formation of S and the drain electrode 20D, the structure shown in FIG. 21D is obtained.

[0170]

According to the present invention, a floating gate electrode provided above a source region and a drain region is capacitively coupled to a control gate electrode, and a desired voltage can be adjusted by adjusting a voltage applied to the control gate electrode. Electric charges are injected into the floating gate electrode from the source region and / or the drain region.
As a result, the resistance of the diffusion layer in the source region and / or the drain region changes in accordance with the amount of charge stored in the floating gate electrode located above the source region and / or the drain region. In addition, a change in resistance of the source region or the drain region can be detected.

As described above, according to the present invention, there is provided a sidewall accumulation type nonvolatile memory cell which can store multi-value data independently. Also, since hot electrons are hardly injected into the gate insulating film under the control gate electrode,
High reliability of data reading is realized.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views showing steps of manufacturing a nonvolatile memory cell according to the present invention.

FIGS. 2A to 2C are diagrams for explaining an operation of a memory cell;

[Figure 3] characteristic diagram showing the relationship between the drain current (I _D) and the drain voltage (V _D) in the memory cell shown in FIG. 1 (c)

4 (a) to 4 (c) are cross-sectional views showing steps of manufacturing another nonvolatile memory cell according to the present invention.

FIG. 5 is a diagram illustrating an operation of the memory cell shown in FIG.

FIG. 6 is a characteristic diagram showing the relationship between the amount of charge (Q (c)) accumulated in the floating gate electrode of the memory cell shown in FIG. 4C and the voltage (V _CG ) applied to the control gate electrode.

FIG. 7 is a characteristic diagram showing a relationship between a drain current (I _D ) and a drain voltage (V _D ) in the memory cell shown in FIG.

FIG. 8 is a sectional view showing an example of a conventional side wall storage type nonvolatile memory cell.

FIGS. 9A and 9B are cross-sectional views showing an improved example of the nonvolatile memory cell of FIG. 1;

FIG. 10 is a sectional view showing still another nonvolatile memory cell according to the present invention;

FIGS. 11A to 11D are cross-sectional views showing steps of manufacturing another nonvolatile memory cell according to the present invention.

FIGS. 12A and 12B are diagrams for explaining the operation of the memory cell shown in FIG. 11D;

FIG. 13 is a cross-sectional view showing another nonvolatile memory cell according to the present invention.

14A and 14B are diagrams for explaining the operation of the memory cell shown in FIG. 13;

FIGS. 15A to 15C are diagrams for explaining the operation of the memory cell shown in FIG. 13;

16 is a characteristic diagram showing the relationship between the amount of charge (Q (c)) stored in the floating gate electrode of the memory cell shown in FIG. 13 and the voltage (V _CG ) applied to the control gate electrode

[17] characteristic diagram showing the relationship between the drain current (I _D) and the drain voltage (V _D) in the memory cell shown in FIG. 13

FIGS. 18A to 18D are cross-sectional views showing steps of manufacturing another nonvolatile memory cell according to the present invention.

FIGS. 19A and 19B are diagrams for explaining the operation of the memory cell shown in FIG.

FIGS. 20A to 20C are diagrams for explaining the operation of the memory cell shown in FIG.

21 (a) to (d) are cross-sectional views showing steps of manufacturing another nonvolatile memory cell according to the present invention.

FIGS. 22A and 22B are diagrams for explaining the operation of the memory cell shown in FIG. 21D;

FIGS. 23A to 23C are diagrams for explaining the operation of the memory cell shown in FIG.

[Explanation of symbols]

 Reference Signs List 11 p-type silicon substrate 12 third portion of gate insulating film 13a first portion of gate insulating film 13b second portion of gate insulating film 14 control gate electrode 17a first floating gate electrode 17b second floating gate electrode 18 interlayer insulating film 20S Source electrode 20D Drain electrode 24 N-type source region 25 N-type drain region 31 Parasitic resistance

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (19)

(57) [Claims] A first conductivity type semiconductor layer having an upper surface region; a second conductivity type source region and a second conductivity type provided in the upper surface region of the semiconductor layer and facing each other at a certain distance. A drain region, a channel region provided in the upper surface region of the semiconductor layer, located between the source region and the drain region, and a first gate insulating film provided on the upper surface region of the semiconductor layer. And a first covering at least a part of the source region.
A first gate insulating film having a portion, a second portion covering at least a portion of the drain region, and a third portion covering the channel region; and a first gate insulating film provided on the first portion of the first gate insulating film. A first floating gate electrode, a second floating gate electrode provided on the second portion of the first gate insulating film, and a first floating gate electrode provided on the third portion of the first gate insulating film;
A control gate electrode electrically insulated from the second floating gate electrode; and a control gate electrode provided between the control gate electrode and the first floating gate electrode, wherein a capacitance is provided between the control gate electrode and the first floating gate electrode. A first insulating film to be coupled, and a second insulating film provided between the control gate electrode and the second floating gate electrode, and capacitively coupling the control gate electrode and the second floating gate electrode. The degree of capacitive coupling by the first insulating film is different from the degree of capacitive coupling by the second insulating film, and is applied to the control gate electrode during data writing. Depending on the applied voltage, a part of the electric charge in the source region and / or the drain region passes through the first portion and / or the second portion of the first insulating film and the first floating gate electrode and / or the second portion. Or the second floating gate electrode Injected, non-volatile memory cell. 2. The nonvolatile memory cell according to claim 1, wherein a thickness of said first insulating film is different from a thickness of said second insulating film. 3. The nonvolatile memory cell according to claim 2, wherein a dielectric constant of said first insulating film is different from a dielectric constant of said second insulating film. 4. A second gate insulating film provided so as to cover the first and second floating gate electrodes, the first portion covering the first floating gate electrode, and the second floating gate electrode. A second gate insulating film having a second portion to cover; a third floating gate electrode provided on the first portion of the second gate insulating film; and a second gate insulating film on the second portion of the second gate insulating film. And a fourth floating gate electrode provided, wherein the third and fourth floating gate electrodes are capacitively coupled to the control gate electrode, and when the data is written, the third and fourth floating gate electrodes are connected to the control gate electrode. In response to the applied voltage, a portion of the charge in the source region and / or the drain region passes through the first portion and / or the second portion of the first gate insulating film to the first floating gate. To the electrode and / or the second floating gate electrode 2. The non-volatile memory according to claim 1, wherein the second gate insulating film is injected into the third floating gate electrode and / or the fourth floating gate electrode through the first portion and / or the second portion of the second gate insulating film. Memory cells. 5. A first conductivity type semiconductor layer having an upper surface region, a second conductivity type source region and a second conductivity type provided in the upper surface region of the semiconductor layer and facing each other at a certain distance. A drain region, a channel region provided in the upper surface region of the semiconductor layer, located between the source region and the drain region, and a first gate insulating film provided on the upper surface region of the semiconductor layer. And a first covering at least a part of the source region.
A first gate insulating film having a portion, a second portion covering at least a portion of the drain region, and a third portion covering the channel region; and a first gate insulating film provided on the first portion of the first gate insulating film. A first floating gate electrode, a second floating gate electrode provided on the second portion of the first gate insulating film, and a first floating gate electrode provided on the third portion of the first gate insulating film;
A control gate electrode electrically insulated from the second floating gate electrode, and a second gate insulating film provided to cover the first and second floating gate electrodes, wherein the first floating gate electrode is A second gate insulating film having a first portion covering the second floating gate electrode and a second portion covering the second floating gate electrode; a third floating gate electrode provided on the first portion of the second gate insulating film; And a fourth floating gate electrode provided on the second portion of the second gate insulating film, wherein the first, second, third and fourth floating gate electrodes are capacitively coupled to the control gate electrode. At the time of writing data, part of the electric charge in the source region and / or the drain region is changed according to the voltage applied to the control gate electrode. Through the portion and / or the second portion, the first floating gate The third floating gate electrode and / or the fourth floating gate electrode are injected into the electrode and / or the second floating gate electrode, and through the first part and / or the second part of the second gate insulating film. Non-volatile memory cells to be implanted into. 6. The nonvolatile memory cell according to claim 5, wherein a thickness of said first portion of said first gate insulating film is equal to a thickness of said second portion. 7. The nonvolatile memory cell according to claim 5, wherein a thickness of said first portion of said second gate insulating film is equal to a thickness of said second portion. 8. The nonvolatile memory cell according to claim 5, wherein a thickness of said second portion is larger than a thickness of said first portion of said first gate insulating film. 9. The nonvolatile memory cell according to claim 8, wherein a thickness of said first portion is larger than a thickness of said second portion of said second gate insulating film. 10. The nonvolatile memory cell according to claim 6, wherein said control gate electrode completely covers said channel region. 11. The method of claim 6, wherein the control gate electrode covers a part of the channel region, and at least one of the first and second floating gate electrodes covers another part of the channel region. The non-volatile memory cell according to claim 1. 12. A first conductivity type semiconductor layer having an upper surface region, a second conductivity type source region and a second conductivity type provided in the upper surface region of the semiconductor layer and facing each other at a certain distance. A drain region, a channel region provided in the upper surface region of the semiconductor layer, located between the source region and the drain region, and a first gate insulating film provided on the upper surface region of the semiconductor layer. A first gate insulating film having a first portion covering a portion of the source region, a second portion covering a portion of the drain region, and a third portion covering the channel region; A first portion provided on the upper surface region, the first portion covering another portion of the source region;
A second gate insulating film having a second portion covering another part of the drain region; a first floating gate electrode provided on the first portion of the first gate insulating film; A second floating gate electrode provided on the second portion of the insulating film; a first floating gate electrode provided on the third portion of the first gate insulating film;
A control gate electrode electrically insulated from the second floating gate electrode; a third floating gate electrode provided on the first portion of the second gate insulating film; And a fourth floating gate electrode provided on the two portions, wherein the first, second, third, and fourth floating gate electrodes are capacitively coupled to the control gate electrode, and In the above, according to a voltage applied to the control gate electrode, a part of the electric charge in the source region and / or the drain region is changed to the first part and / or the second part of the one gate insulating film. Through the first floating gate electrode and / or the second floating gate electrode, and through the first portion and / or the second portion of the second gate insulating film. Or, the non- Nonvolatile memory cell. 13. The nonvolatile memory cell according to claim 12, wherein a thickness of said first portion of said first gate insulating film is equal to a thickness of said second portion. 14. The nonvolatile memory cell according to claim 12, wherein a thickness of said first portion of said second gate insulating film is equal to a thickness of said second portion. 15. The nonvolatile memory cell according to claim 12, wherein a thickness of said second portion is larger than a thickness of said first portion of said first gate insulating film. 16. The nonvolatile memory cell according to claim 15, wherein a thickness of said first portion is larger than a thickness of said second portion of said second gate insulating film. 17. The nonvolatile memory cell according to claim 12, wherein said control gate electrode completely covers said channel region. 18. The method according to claim 12, wherein the control gate electrode covers a part of the channel region, and at least one of the first and second floating gate electrodes covers another part of the channel region. The non-volatile memory cell according to claim 1. 19. A first conductivity type semiconductor layer having an upper surface region, a second conductivity type source region and a second conductivity type provided in the upper surface region of the semiconductor layer and facing each other at a certain distance. A drain region, a channel region provided in the upper surface region of the semiconductor layer, located between the source region and the drain region, and a first gate insulating film provided on the upper surface region of the semiconductor layer. A first gate insulating film having a first portion covering a portion of the source region, a second portion covering a portion of the drain region, and a third portion covering the channel region; An insulating film provided on the upper surface region, the insulating film having a first portion covering another portion of the source region, and a second portion covering another portion of the drain region; A first floating gate provided on the first portion of the gate insulating film; An electrode; a second floating gate electrode provided on the second portion of the first gate insulating film; a third floating gate electrode provided on the first portion of the insulating film; A fourth floating gate electrode provided on the second portion; a third gate insulating film provided between the first floating gate electrode and the third floating gate electrode; A fourth gate insulating film provided between the first, second, third, and fourth floating gate electrodes, wherein the first, second, third, and fourth floating gate electrodes are capacitively coupled to the control gate electrode. At the time of writing data, part of the electric charge in the source region and / or the drain region is changed according to the voltage applied to the control gate electrode. Through the portion and / or the second portion, the first floating gate electrode and / or the It is injected into the second floating gate electrode, also, through the third gate insulating and / or said fourth gate insulating film and are injected into the third floating gate electrode and / or the fourth floating gate electrode, the nonvolatile memory cell.