JP3136953B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
In particular, the present invention relates to a data processing device that processes moving image data.

[0002]

2. Description of the Related Art As a system for processing moving image data, there is an international moving image encoding / decoding system. For example, FIG. 2 and FIG. 3 are block diagrams respectively showing an example of an encoding device and an example of a decoding device of the international video encoding / decoding system.

Referring to FIG. 2 and FIG. 3, an inverse DCT circuit exists in both the encoding device and the decoding device. The reason why the encoding apparatus requires the inverse DCT circuit is that the reference image used for motion compensation prediction is decoded through quantization, inverse quantization, and inverse DCT processing. After performing the inverse quantization, the decoding apparatus decodes the image using inverse DCT and motion compensation. Depending on the operation method of the inverse DCT of each of the encoding device and the decoding device, an image decoded in the encoding device and an image output from the decoding device are different, and errors are accumulated. This is called an inverse DCT mismatch. H. International Standards In H.261 and MPEG1, all DCT coefficients are odd-numbered in a direction approaching zero to solve the inverse DCT mismatch.

FIG. 4 is a block diagram showing a detailed configuration of an inverse quantization circuit in these data processing devices.

Referring to FIG. 4, a multiplication circuit is used in the inverse quantization circuit, and a 0-direction rounding conversion circuit from an even number to an odd number for solving a DCT mismatch is added to the next stage. Each stage is provided with a limiter for preventing overflow, and a final stage is provided with a multiplexer for selecting whether the data is inversely quantized or not to be converted. In the case of decoding, the calculation in the variable length decoding is simply performed, and the processing with the absolute value is performed to reduce the amount of hardware. On the other hand, in the inverse DCT, 2
Therefore, a process of converting a signed absolute value expression into a two's complement expression is also required. Therefore, a zero-direction rounding conversion process from an even number to an odd number depending on the sign is required.

FIG. 5 is a circuit diagram showing a sign-dependent even-to-odd zero-direction rounding conversion circuit in a conventional data processing apparatus.

Referring to FIG. 5, this conversion circuit receives an absolute value input DI [17: 0] and a sign input SI as inputs, and converts it into an even-odd rounding conversion unit 5-1 and a two's complement operation unit 5-2.
And output means 5-3 for adding the sign of the most significant bit to the output of the two's complement arithmetic unit 5-2.
It outputs a zero-direction rounding conversion output DO [18: 0] from an even number to an odd number depending on the sign in the two's complement representation.

The even-odd rounding conversion unit 5-1 is a circuit for converting an absolute value from an even number to an odd number, that is, -1 for an even number other than 0, and outputs as it is for an odd number and 0. Reference numeral 5-2 denotes a circuit that outputs the output of 5-1 as it is when the sign is positive, and performs a two's complement operation when the sign is negative.

Continuing the description, the even-odd rounding conversion unit 5-1 includes a 0 detection circuit 501 that outputs "1" only when the input (DI [17: 0]) is 0, and an inverter 50.
2, 503, a 2-input AND 504, and a control signal (50
When the control signal is “0”, the input value is decremented. When the control signal is “0”, the input value is output as it is (hereinafter referred to as “through”). -2 is exclusive OR 506
And an incrementer 507 with a control signal that increments the input value when the control signal (SI) is "1" and passes through when the control signal (0) is "0".

Next, the operation will be described in detail with reference to FIG. First, the even-odd rounding conversion unit 5-1 will be described.

If DI [17: 0] is an odd number, DI
[0] becomes “1”, and the output of the inverter 503 becomes “0”. Since the output of the two-input logical product 504 becomes “0”, DI [17: 0] is passed through by the decrementer 505.

When DI [17: 0] is an even number other than 0,
DI [0] becomes “0” and the output of the inverter 503 becomes “1”. The output of the 0 detection circuit 501 is “0”.
And the output of the inverter 502 becomes “1”. Since the output of the two-input logical product 504 is “1”, DI [17: 0] is decremented by the decrementer 505.
That is, 1 is rounded in the 0 direction and becomes an odd number.

When DI [17: 0] is 0, the output of the 0 detection circuit 501 becomes "1" and the output of the inverter 502 becomes "0". Since the output of the two-input logical product 504 becomes “0”, DI [17: 0] is passed through by the decrementer 505.

Next, the two's complement arithmetic unit 5-2 will be described.

When the sign input SI is positive, the value becomes "0", the exclusive OR 506 outputs the other input without inverting the other input, and the incrementer 507 also passes through. That is, data conversion is not performed as a result.

If the sign input SI is negative, the value is "1", and the exclusive OR 506 inverts the other input and is incremented by the incrementer 507, so that the two's complement is obtained. become.

As understood from the above description, the absolute value input DI
When [17: 0] is an even number and the sign input SI is a positive number, that is, “0”, it is decremented by the even-odd rounding conversion unit 5-1 and passed through by the two's complement operation unit 5-2.
One is rounded in the zero direction.

When the absolute value input DI [17: 0] is an odd number and the sign input SI is a positive number, that is, "0", the even-odd conversion section 5-1 passes through and the 2's complement operation section 5-2 also performs the processing. The output value is the same as the input value because it is passed through.

When the absolute value input DI [17: 0] is an even number and the sign input SI is a negative number, that is, "1", it is decremented by the even-odd conversion unit 5-1 and decremented by two's complement operation unit 5-
Since the 2's complement is obtained by 2 and the most significant bit is "1", 1 is rounded toward 0.

If the absolute value input DI [17: 0] is an odd number and the sign input SI is a negative number, that is, "1", the even-odd conversion unit 5-1 passes through and the two's complement operation unit 5-2 outputs. Since two's complement is taken, only the sign is inverted.

When the absolute value input DI [17: 0] is 0 and the sign input SI is "0", the even-odd conversion section 5-1
In this case, the output value is 0 because the data is passed through and is also passed through by the two's complement arithmetic unit 5-2.

The above is summarized in Table 1.

[0023]

[0024]

The above-mentioned conventional data processing apparatus, in which the sign-dependent 0-direction rounding conversion circuit from an even number to an odd number has a problem that the circuit scale is large because it has an incrementer and a decrementer. I was

Accordingly, it is an object of the present invention to reduce the circuit scale of a data processing device for processing image data in accordance with the international video coding / decoding system.

[0026]

Therefore SUMMARY OF THE INVENTION The present invention converts rounded image data represented by the sign bit and absolute value in accordance with International moving picture coding and decoding system to zero direction from even to odd In a data processing apparatus having data conversion means for outputting data in two's complement representation, the data conversion means includes: zero detection means for detecting a zero value of an absolute value of the data; Decrementing means for decrementing, exclusive OR means for bit-inverting and outputting the output of the decrementing means when the data is a negative number, and corresponding to the output of the zero detecting means as converted data of the least significant bit of the absolute value And outputs the converted signal as the converted data from the second least significant bit to the most significant bit of the absolute value. And an output means for outputting a force.

Further, when the output means detects a zero value of the absolute value of the data, the output means outputs a zero value as the converted data of the absolute value.

Table 2 summarizes the inputs and outputs of the data conversion means.

[0029]

Further, the configuration of the data conversion means will be described in detail.

The sign-dependent zero-to-odd rounding conversion circuit in the data processing apparatus of the present invention changes the method of sign inversion to +1 after bit inversion and then to -1 and then bit inversion. The circuit configuration is based on the truth table shown in Table 2.

The major difference from Table 1 is the case of a negative even number, which is realized by subtracting -2 from what was conventionally performed with both -1 and +1. The value of -2 is equivalent to the value of -1 for the first bit or more. In other words, one decrementer can perform sign-dependent rounding in the zero direction from an even number to an odd number. That is, it is sufficient to divide the input data into the least significant bit and the other bits to perform the operation. Table 3 shows an equation in the case of division into the least significant bit and other bits. Note that “｛,,｝” means bit concatenation.

[0033]

First, when the code input SI is positive (0) and the data DI is an even number other than 0, a borrow always occurs, so that the data DI [17: 1] of bits 17 to 1 are generated. Is output after being decremented by 1. At that time, the least significant bit is always "1".

When the sign input SI is positive (0) and the data DI is an odd number, the input data is output as it is, so that the data DI [17: 1] of bits 17 to 1 is output as it is, and the least significant bit is output. Is always "1".

When the sign input SI is negative (1) and the data DI is an even number other than 0, the data DI [17: 1] of the bits 17-1 is reduced by -1 because it is inverted by -2.
Then, the output is inverted and the least significant bit is set to "1".

When the sign input SI is negative (1) and the data DI is an odd number, since the least significant bit is "1",
Even if the input data is decremented by 1, the data DI of bits 17 to 1
Since [17: 1] is not affected, it is only inverted and output as it is, and the least significant bit is inverted by 1-1 (= 0) and "1" is output.

When the data DI is 0, "0" is output as the least significant bit, and the data DI [1] of bits 17-1 is output.
7: 1] is output as it is.

The most significant bit DO [1] which is a sign bit
8], a sign input SI may be added to each of the outputs described above.

[0040]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of a sign-dependent even-to-odd zero-direction rounding conversion circuit in the data processing apparatus of the present invention.

Referring to FIG. 1, this conversion circuit receives an absolute value input DI [17: 0] and a sign input SI as inputs, and outputs a 0 detection circuit 101, inverters 102 and 10
3, a two-input logical product 104, a decrementer 105,
An exclusive OR 106, an output means 1-1 for adding the sign of the most significant bit, and a signal corresponding to the output of the 0 detection circuit 101 as the converted data of the least significant bit of the absolute value to output Output means 1-2 for outputting the corresponding bit output of the exclusive OR 106 as the conversion data from the bit to the most significant bit, and 0 from the even number to the odd number depending on the sign in the 2's complement representation The rounding conversion output DO [18: 0] is output.

Continuing the description, the 0 detection circuit 10
1 outputs “1” only when the absolute value input (DI [17: 0]) is 0. This output is inverted by the inverter 102 and connected to output means for outputting bit 0 of the output DO [18: 0]. Therefore, the output DO [1
The bit 0 of [8: 0] is 0 only when the input DI [17: 0] is 0, and otherwise outputs “1”. This is D in the truth table of Table 3.
It matches the least significant bit (DO [0]) of O [18: 0].

The decrementer 105 is a decrementer with a control signal. If input DI [17: 0] is 0, 0
The output of the detection circuit 101 becomes “1”,
2 is "0", the output of the two-input logical product 104 is "0", and the control signal of the decrementer 105 is "0", so that DI [17: 1] which is the input data of the decrementer 105 is used. (All 0) is passed through.

When the input DI [17: 0] is an odd number, D
Since I [0] is “1”, the input of the inverter 103 is “1” and the output is “0”, the output of the two-input AND circuit 104 is “0”, and the control signal of the decrementer 105 is “0”. Input data D of the decrementer 105
I [17: 1] is passed through.

When the input DI [17: 0] is an even number other than 0, the output of the 0 detection circuit 101 becomes "0" and the output of the inverter 102 becomes "1". Also, DI [0] is "0", so that the input of the inverter 103 is "0" and the output is "1", the output of the two-input logical product 104 is "1", and the control signal of the decrementer 105 is "1". 1 "
Therefore, the input data DI [1 of the decrementer 105
7: 1] is decremented.

The exclusive OR 106 is calculated by the decrementer 10
5 and the code input SI are input signals. When the sign input SI is positive (0), the output of the decrementer 105 is passed through, and when the sign input SI is negative (1), the output of the decrementer 105 is inverted.

Therefore, the output of the exclusive OR 106 is such that the sign input SI is positive (0) and the absolute value input DI
When [17: 0] is an even number other than 0, the input DI [1
7: 1], and the sign input SI is positive (0).
And when the absolute value input DI [17: 0] is an odd number, the input DI [17: 1] itself becomes the sign input SI
Is negative (1) and the absolute value input DI [17: 0] is 0
When the input DI [17: 1] is other than an even number, the value becomes a bit-inverted value after subtracting -1 from the input DI, and is input when the sign input SI is negative (1) and the absolute value input DI [17: 0] is an odd number. DI [17: 1] is a bit-inverted value, the sign input SI is positive (0), and the absolute value input DI [17:
When [0] is 0, the input DI [17: 1] is itself.

This corresponds to the output DO [1] of the truth table of Table 3.
8: 0] and the middle bit DO [17: 1].

Since the output DO [18] is configured to output the code input SI itself, it matches the most significant bit DO [18] of the output DO [18: 0] in the truth table of Table 3.

[0051]

As described above, in the data processing apparatus according to the present invention, the sign-dependent 0-to-odd rounding conversion circuit can be constituted by only one decrementer as an arithmetic circuit. This has the effect of greatly reducing the circuit scale.

More specifically, when a CMOS circuit is designed by a conventional method, an 18-bit decrementer is 252T.
rs, 18-bit incrementer is 252 Trs, 1
The 8-bit 0 detector is 46 Trs, the exclusive OR of 18 bits is 108 Trs, and the others are 4 Trs, for a total of 662.
Trs design was required. In contrast, the circuit of the present invention has a 17-bit decrementer of 238 Trs, 18 bits.
Bit 0 detector is 46 Trs, exclusive OR of 17 bits is 102 Trs, others are 4 Trs, 390 T in total
Since the design of rs is sufficient, there is an effect of reducing the size by 40% or more.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a zero-direction rounding conversion circuit in a data processing device of the present invention.

FIG. 2 is a block diagram illustrating a typical moving picture encoding device.

FIG. 3 is a block diagram showing a typical moving picture decoding device.

FIG. 4 is a block diagram showing a detailed configuration of an inverse quantization circuit in FIGS. 2 and 3;

FIG. 5 is a circuit diagram showing an example of a zero-direction rounding conversion circuit in a conventional data processing device.

[Explanation of symbols]

101, 5010 detector 102, 103, 502, 503 inverter 104, 504 two-input logical product 105, 505 decrementer 106, 506 exclusive OR 1-1, 1-2, 5-3 output means 201 discrete cosine transform ( DCT) circuit 202 Quantization circuit 203, 302 Inverse quantization circuit 204, 303 Inverse discrete cosine transform (DCT) circuit 205, 305 Frame memory 206, 304 Motion compensation circuit 207 Motion vector detection circuit 208, 306 Addition unit 209 Subtraction unit 210 Variable Length Encoding Circuit 301 Variable Length Decoding Circuit 401 Multiplication Circuit 402 Sign-Dependent O-to-Odd Rounding Conversion Circuit 403 Limiter Circuit 404 2-Input Multiplexer 507 Incrementer 5-1 Odd-to-Odd Rounding from Odd to Odd Conversion unit 5-2 Two's complement arithmetic unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-265709 (JP, A) JP-A-7-153195 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 7/30 H03M 7/30

Claims (2)

(57) [Claims] 1. Data conversion means for converting image data represented by code bits and absolute values in the direction of zero from an even number to an odd number in accordance with the international moving picture encoding / decoding system in a zero direction and outputting the result in a two's complement representation. In the data processing device having the above, the data conversion means includes: a zero detection means for detecting a zero value of an absolute value of the data; a decrement means for decrementing the absolute value when the data is even; When exclusive, the exclusive-OR means for inverting the output of the decrement means and outputting a signal corresponding to the output of the zero detection means as converted data of the least significant bit of the absolute value, Output means for outputting a corresponding bit output of the exclusive OR means as converted data from the second bit to the most significant bit. The data processing apparatus according to claim. 2. The data processing apparatus according to claim 1, wherein the output unit outputs a zero value as the converted data of the absolute value when detecting a zero value of the absolute value of the data.