JP3137045B2 - Method and apparatus for reducing drive loss of switching power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply, and more particularly, to a method for reducing drive loss.

[0002]

2. Description of the Related Art Battery-powered portable devices such as notebook computers are increasing. In these portable devices, 5V required by the device from battery power,
A step-down switching power supply circuit is generally used to generate a voltage such as 3.3V. In a step-down switching power supply circuit, the relationship between the input voltage, that is, the battery voltage and the output voltage required by the device is expressed as follows, where D is the duty cycle of the switching power supply circuit.

Output voltage = D × input voltage The duty cycle D can take a value from 0 to 1 by PWM control. Therefore, to control the output voltage to the input voltage, D = 1, that is, 100% duty cycle must be achieved.

On the other hand, when the PchMOS transistor Q1 is used for the main switch as in the conventional example of FIG. 6, the drive voltage of the main switch is in the range from ground to the input voltage. Since a portable device does not have a power supply other than a battery, a Pch which does not require a separate power supply in a driving circuit to achieve the above-described 100% duty cycle is required.
A circuit configuration using a MOS transistor as a main switch is required.

FIG. 7 shows an example of a drive circuit when a PchMOS transistor is used. Here, between the gate and the source of the PchMOS transistor Q1, as described above,
A voltage from the input voltage to the ground is applied. The maximum applicable voltage between the gate and source of the PchMOS transistor Q1 is defined as an absolute maximum rating, and is generally 15V to 20V. On the other hand, in the case of a notebook personal computer or the like, assuming that a battery is charged, a voltage of about 20 V may be applied as an input voltage to the switching power supply circuit. So Pch
In the conventional example of FIG. 6, the gate and source of the PchMOS transistor Q1 are clamped by the constant voltage diode ZD1 so as not to exceed the absolute maximum rating between the gate and source of the MOS transistor.

[0006]

In the above-described conventional switching power supply circuit, the input voltage is PchM
If the absolute value of the gate-source voltage of the OS transistor Q1 exceeds the absolute maximum rating, a loss occurs due to clamping. If the input voltage is V _IN , the zener voltage of the constant voltage diode, ie, the clamp voltage is V _Z , and the current flowing through the constant voltage diode at the time of clamping is I _Z , the loss at the time of clamping is as follows.

P _clamp = (V _IN -V _Z ) · I _Z · D Here, the period during which the transistor Q 1 is turned on is T _ON , Q 1
Is the switching cycle of T, D = T _ON / T indicates the duty cycle of Q1.

If a specific and general value is adopted in the case of a notebook personal computer, P _clamp = (25V-15V) × 5mA × 0.2 = 10
mW.

By making the clamp voltage as close as possible to the absolute maximum rating between the gate and source of the PchMOS transistor, it is possible to reduce the loss caused by clamping at the maximum input voltage.

[0010] However, the PchMOS transistor generates a loss depending on the drive voltage. Assuming that the driving voltage applied between the gate and the source of the PchMOS transistor is V _GS , the capacitance between the gate and the source of the PchMOS transistor is C _GS , and T is the switching cycle, the driving loss P _drive is expressed as follows.

[0011] Here _{P drive ≒ C GS · V GS} 2 / T, when the input voltage V _IN is lower than the clamp voltage V _Z, the drive voltage applied between the gate and source of the PchMOS transistor is approximately equal to the input voltage , P _drive ≒ C _GS · V _IN ² / T (when V _IN <V _Z ). That is, the drive loss of the PchMOS transistor increases in proportion to the square of the input voltage.

When V _IN is higher than V _Z , P _drive ≒ C _GS · V _Z ² / T (when V _IN ≧ V _Z ), and the drive loss is proportional to the square of V _Z. Increase.

[0013] In the case of a notebook computer, to adopt concrete and common values _{P drive ≒ 1500pF × (15V)} 2 / 3μs = 0.
1125W.

In order to extend the operation time of the portable device, it is necessary to suppress these losses as much as possible.

In the conventional switching power supply device described above, the drive voltage between the gate and the source of the Pch MOS transistor must be reduced as much as possible in order to reduce the drive loss. For this purpose, the clamp voltage must be reduced. . However, since the loss caused by clamping is proportional to the difference between the input voltage and the clamp voltage, there is a disadvantage that the loss at the time of clamping increases when the clamp voltage is reduced.

An object of the present invention is to provide a method and a device for reducing the drive loss of a switching power supply device in which the drive loss does not increase even if the clamp voltage is reduced.

[0017]

According to the present invention, there is provided a method of reducing driving loss of a switching power supply, comprising the steps of:
Driving a PchMOS transistor which is a main switch having a diode connected to a drain through a driving circuit; and connecting the PchMOS transistor with a gate connected to an anode and a source connected to the PchMOS transistor with a cathode connected to the PchMOS transistor.
Clamping a voltage applied between the gate and the source of the MOS transistor, turning on the Pch MOS transistor, and simultaneously exciting the energy storage inductor with the voltage clamped by the constant voltage diode; Regenerating the energy stored in the storage inductor to the input power supply.

In this method for reducing the driving loss of the switching power supply, the energy clamped during the ON period is stored in the inductor, and the energy is regenerated to the input power supply during the OFF time of the main switch, thereby preventing an increase in the driving loss. can do.

Providing a synchronous rectification NchMOS transistor in parallel with a diode connected to the drain of the PchMOS transistor as the main switch;
Driving the transistors so that the transistors are not turned on at the same time.

The switching power supply of the present invention receives a DC input voltage at the source, switches the input voltage and outputs an intermittent voltage from the drain, a main switching PchMOS transistor, an output voltage, an output current, PW that controls drive pulse width according to input voltage
An M control circuit; a first drive circuit for driving the PchMOS transistor in response to a supply of a control pulse signal from the PWM control circuit; and a smoothing circuit for smoothing the intermittent voltage and outputting an output voltage. In the power supply device, a constant voltage diode having an anode connected to the gate of the PchMOS transistor and a cathode connected to the source of the PchMOS transistor, for clamping a voltage applied between the gate and the source of the PchMOS transistor; A first driving PchMOS transistor for turning on the transistor, a driving NchMOS transistor,
Driving PchMOS transistor and the driving Nch
An inductor excited by energy clamped by the constant voltage diode by a MOS transistor.

Further, a second driving PchMOS transistor for turning off the PchMOS transistor which is a main switch according to a control signal of the PWM control circuit, and the inductor for regenerating energy of a clamp energy storage inductor to an input power supply. And a second diode connected between the other end of the inductor and the ground.

Also, the PchMOS as the main switch
An NchMOS transistor for synchronous rectification provided in parallel with a diode connected to the drain of the transistor;
It is desirable to have means for preventing the NchMOS transistor and the PchMOS transistor from turning on at the same time.

Further, the driving circuit may include a second driving circuit for driving the NchMOS transistor for synchronous rectification, and a constant voltage circuit for supplying a constant voltage to the driving circuit.

[0024]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a switching power supply according to a first embodiment of the present invention.

As shown in FIG. 1, the switching power supply of this embodiment has a PWM control circuit 1, a driving circuit 2, a PchMOS transistor Q1 as a main switch, a first driving PchMOS transistor Q2, and a second driving Pc.
hMOS transistor Q3, NchMOS transistor Q4, constant voltage diode ZD1, diodes D1, D
2, D3, a choke coil L1, an energy storage inductor L2, and an output smoothing capacitor C1.

[0027] The source of the PchMOS transistor Q1 is connected to a power source V _IN, the drain of the PchMOS transistor Q1 is connected to one end of the choke click coil L1, the period PchMOS transistor Q1 is on choke from the input supply V _IN The voltage smoothed by the output smoothing capacitor C1 through the coil L1 appears at the output terminal 3. Further, the cathode of the diode D3 is connected to the drain of the PchMOS transistor Q1.
While the OS transistor Q1 is off, the diode D3
A voltage appears at the output terminal 3 through the choke coil L1. In this step-down switching power supply circuit, P
Constant voltage diode ZD1 for clamping input power supply V _IN between gate and source of chMOS transistor Q1
Has a cathode connected to the source of the PchMOS transistor Q1, and an anode connected to the gate of the PchMOS transistor Q1. The first driving PchMOS transistor Q2 is for driving the PchMOS transistor Q1, and its source is connected to the source of the PchMOS transistor Q1 and its drain is connected to the gate of the PchMOS transistor Q1. The second driving PchMOS transistor Q3 and the NchMOS transistor Q4 are transistors for turning on the PchMOS transistor Q1, and include a constant voltage diode ZD.
1 is applied to the energy storage inductor L2, and the clamp energy is applied to the inductor L2.
It operates to accumulate in. Second driving PchMO
The source of the S transistor is a PchMOS transistor Q
1 and the drain is connected to one end of the inductor L2. Driving NchMOS transistor Q4
Is connected to the other end of the inductor L2, and the source is connected to the ground. Diodes D1 and D2
Works to regenerate the energy stored in the inductor L2 to the input power source V _IN during the ON period of the PchMOS transistor Q1. The cathode of the diode D1 is connected to the input power supply V.
_IN , the anode of D1 is Nch for driving the inductor L2
Connected to one end connected to MOS transistor Q4. The cathode of the diode D2 is connected to one end of the inductor L2 to which the driving PchMOS transistor Q3 is connected, and the anode of the diode D2 is connected to ground. The gates of the driving PchMOS transistors Q2 and Q3 and the NchMOS transistor Q4 are connected to the PWM control circuit 1 through the driving circuit 2 so as to be driven with an appropriate duty cycle.

FIG. 2 shows the output of the PWM control circuit 1 and Pch
Gate voltage of MOS transistor Q1 and NchMOS
Drain current of transistor Q4 and diodes D1, D
2 shows the lapse of time of the current flowing through the inductor 2 and the current flowing through the inductor L2.

As shown in FIG. 2, in the switching power supply of this embodiment, first, the output of the PWM control circuit 1 drives the gate of the PchMOS transistor Q1. In the period I, the driving MOS transistors Q3 and Q3
4 is turned on and P is passed through the stray capacitance C _S of the inductor L2.
This is a period during which a part of the charge between the gate and the source of the chMOS transistor Q1 is extracted.

The stray capacitance C of the inductor L2_S Is charged
Then, the clamp voltage by the constant voltage diode ZD1 becomes Q
1 sufficiently lower than the absolute maximum rated voltage between the gate and the source,
And the voltage is set high enough to drive Q1
In period II, the input power V _INTo constant voltage diode Z
An exciting current flows through the inductor L2 through D1.

In the period III, the driving transistors Q3,
After Q4 turns off, Q2 turns on. When Q2 is turned on, the gate and source of PchMOS transistor Q1 are short-circuited, and Q1 is cut off. On the other hand, the energy stored in the inductor L2 is regenerated to the input power supply _{VIN through} the diode D2, the inductor L2, and the diode D1, since Q3 and Q4 are off.

FIGS. 3 (a), 3 (b) and 3 (c)
The state of the switching power supply of FIG. 1 during periods I, II, and III of FIG. 1 is shown by a symbolized equivalent circuit.

In the switching power supply of this embodiment,
Emission due to the voltage clamped during the ON period of the main switch
Energy is stored in the inductor during the off period of the main switch.
Since the energy is regenerated to the input power supply,
Growth is prevented. That is, the inductor of the inductor L2
Lance_TwoAnd the peak of the current flowing through the inductor L2.
I_L Then, the energy stored in the inductor L2
Gi is (1/2) L_Two・ I_L ^TwoAnd switches at period T
(1/2) L _Two ・ I_L ^Two
/ T loss can be reduced. As a realistic value, L_TwoThe value of the
500 μH, I_L Is 50 mA and the period is 3 μs
The maximum possible loss improvement is 0.208W.

When the clamp voltage is set to about 5 V, it is possible to sufficiently drive Q1.
1 the drive loss, 1500pF × (5V) ² /3μs=0.0125W next, is about 1/10 the loss compared to the case of driving the Q1 at 15V as described above to reduce.

FIG. 4 is a circuit diagram of a second embodiment of the switching power supply of the present invention.

The switching power supply device of this embodiment is for portable equipment, and uses a synchronous rectification circuit for improving efficiency, that is, reducing loss. As shown in FIG. 4, as a configuration for a synchronous rectification circuit in the circuit of FIG.
The constant voltage circuit 4, the inverter INV1, the resistors R1, R2,
R3, R4, R5 and diodes D4, D5, D6, D
7, D8 and PchMOS transistors Q5, Q6, Q7
And have been added. NchMOS transistor Q5
Has a drain connected in parallel with the cathode of the diode D3 for synchronous rectification. Further, the gate of NchMOS transistor Q5 is driven with a phase opposite to that of driving Q1. Here, between the gate and source of Q5, an input power supply V _IN is applied to a drive circuit including Pch MOS transistors Q6 and Q7 through the constant voltage circuit 4. Resistance R
1, R2, D4, D5 and the inverter INV1 are
The S transistors Q2 and Q3 and Q4 are selected so as not to be turned on at the same time, the resistors R3, R4, D6 and D7 are selected so that the MOS transistors Q6 and Q7 are not turned on at the same time.
1 and the synchronous rectification transistor Q5 are simultaneously turned on.

In the switching power supply of this embodiment, the loss due to the diode D3 connected to the drain of the main switch Q1 is reduced by employing the synchronous rectification circuit, so that the drive loss reduction efficiency can be further improved.

FIG. 5 is a circuit diagram of a switching power supply according to a third embodiment of the present invention.

The switching power supply of this embodiment uses an inverter INV1, diodes D4 and D5, and resistors R1 and R2 instead of the drive circuit 2 shown in FIG. 1, and a synchronous rectification NchMOS transistor Q5, a diode D8 and a resistor R5. The configuration has been added.

NchMOS transistor Q5 for synchronous rectification
Is connected to the drain of the driving NchMOS transistor Q4, and the PchMOS transistor Q
The resistor R5 and the diode D
They are connected through eight parallel circuits.

Since the switching power supply of this embodiment employs a synchronous rectifier circuit as in the embodiment of FIG. 4, it is more effective in preventing an increase in drive loss and has the smallest number of parts. High efficiency.

[0042]

As described above, the present invention regenerates the energy stored in the inductor during the on-period of the main switch to the input power supply during the off-period, thereby increasing the drive loss even when the clamp voltage is reduced. The switching power supply device having the PchMOS transistor for synchronous rectification has an effect of realizing a switching power supply device with further reduced drive loss.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a switching power supply of the present invention.

FIG. 2 is a timing chart showing the operation of the switching power supply device of FIG.

3 (a), 3 (b) and 3 (c) are symbolized equivalent circuits for explaining the operation of the switching power supply device of FIG. 1;

FIG. 4 is a circuit diagram of a switching power supply device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a switching power supply device according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional switching power supply device.

7 is a circuit diagram of a drive circuit of the switching power supply device of FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 PWM control circuit 2 drive circuit 3 output terminal 4 constant voltage power supply Q1 main switch (PchMOS transistor) Q2 drive PchMOS transistor Q3 drive PchMOS transistor Q4 drive NchMOS transistor Q5 synchronous rectifier switch (NchMOS transistor) Q6, Q7 PchMOS transistor D1 , D2 Clamp energy regeneration diode D3 Flywheel diode D4, D5, D6, D7, D8 Diode ZD1 Clamp constant voltage diode V _IN input power supply L1 Choke coil C1 Output smoothing capacitance C _S stray capacitance L2 Clamp energy storage inductor R1 , R2, R3, R4, R5 resistance

Claims (6)

(57) [Claims] 1. A method for reducing driving loss of a switching power supply, comprising: driving a PchMOS transistor, which is a main switch having a diode connected to a drain, through a driving circuit by a PWM control circuit; and connecting an anode to a gate of the PchMOS transistor. The PchMOS is connected by a constant voltage diode having a cathode connected to the source of the PchMOS transistor.
Clamping the voltage applied between the gate and the source of the transistor; turning on the PchMOS transistor and exciting the energy storage inductor with the voltage clamped by the constant voltage diode; and energizing the energy storage inductor. Regenerating the energy stored in the inductor for the input power supply. 2. A step of providing an NchMOS transistor for synchronous rectification in parallel with a diode connected to a drain of a PchMOS transistor serving as the main switch, wherein the NchMOS transistor for synchronous rectification and the PchM transistor are provided.
Driving the OS transistor so that the OS transistor is not turned on at the same time. 3. A source supplied with a direct current input voltage,
A main switching PchMOS transistor for switching the input voltage to output an intermittent voltage from a drain, a PWM control circuit for controlling a drive pulse width corresponding to an output voltage, an output current, and an input voltage; In response to the supply of the control pulse signal, the PchMOS
In a switching power supply device comprising: a first drive circuit for driving a transistor; and a smoothing circuit for smoothing the intermittent voltage and outputting an output voltage, for clamping a voltage applied between a gate and a source of the PchMOS transistor. To the Pc
a constant-voltage diode connected to the gate of the hMOS transistor and having a cathode connected to the source of the PchMOS transistor, a first diode for turning on the PchMOS transistor;
A driving PchMOS transistor, a driving NchMOS transistor, and an inductor which is excited by the first driving PchMOS transistor and the energy clamped by the constant voltage diode by the driving NchMOS transistor. Switching power supply. 4. A second driving PchMOS transistor for turning off the PchMOS transistor as a main switch according to a control signal of the PWM control circuit, and the inductor for regenerating energy of a clamp energy storage inductor to an input power supply. 4. The switching power supply according to claim 3 , further comprising: a first diode connected between one end of the inductor and an input power supply; and a second diode connected between the other end of the inductor and ground. 5. 5. A means for preventing an NchMOS transistor for synchronous rectification provided in parallel with a diode connected to a drain of a PchMOS transistor serving as the main switch, and for simultaneously turning on the NchMOS transistor and the PchMOS transistor. The switching power supply device according to claim 4, comprising: 6. The switching power supply according to claim 5, further comprising a second drive circuit for driving the NchMOS transistor for synchronous rectification, and a constant voltage circuit for supplying a constant voltage to the drive circuit.