JP3137411B2 - Clock duty compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a clock duty compensating circuit for compensating a duty to a desired value even if the clock y) fluctuates.

[0002]

2. Description of the Related Art In recent years, in order to meet various needs of a high-speed broadband service, studies on introduction of an optical communication system to a subscriber system have been actively conducted.

For example, the optical transmission speed is 6 Mbps, 32
Mbps, 52 Mbps, 156 Mbps, 622 Mbps
Optical transmission modules (conversion modules from electric signals to optical signals) corresponding to transmission speeds such as s and 2.4 Gbps are being developed.

[0004] In such an optical transmission module, there is a demand for a small, high reliability, low power consumption, and low price optical interface unit.

For example, FIG. 2 shows a functional block diagram of a conventional optical transmission module.

In FIG. 2, NRZ data DA0 is supplied to a code conversion circuit 3. On the other hand, the input clock CK0
(Clock duty: the time ratio between the high level and the low level is, for example, 1: 1, that is, 50%, and the frequency is f0.) Is supplied to the tuning circuit 4. The tuning circuit 4 is a tuning circuit using a crystal oscillator or the like, and the tuning frequency is set to f0. The tuning circuit 4 outputs a sine wave signal S0 having a frequency f0 and supplies it to the limiter circuit 5. The limiter circuit 5 restricts the supplied sine wave signal S0 of the frequency f0 within a predetermined range and converts the sine wave signal S0 into a rectangular wave of Duty.
A clock CK1 of 50% is obtained and supplied to the code conversion circuit 3. The code conversion circuit 3 performs a logical AND operation on the supplied NRZ data by the supplied clock CK1 to perform RZ
The data is converted into data DA1 and supplied to the light emitting element drive circuit 7. The light emitting element driving circuit 7 converts the driving signal to a driving signal for driving the light emitting element 8 based on the RZ data DA1 and supplies the driving signal to the light emitting element 8. The light emitting element 8 converts the light signal into an optical signal DA2 according to the supplied drive signal and outputs the signal to the optical transmission line.

[0007]

In the optical transmission module as described above, the input clock CK0 is actually divided by a clock circuit PWB (module) or the like from a clock oscillated using a crystal oscillator or the like as an original oscillation. In many cases, and supplied to the optical transmission module.

The clock CK0 supplied in such a case
Is for high-speed optical transmission as in the optical transmission speed example above,
A high-speed clock is supplied. For example, RZ data is 32M
In bps, the pulse period of one clock is 1/32 MHz
(Sec) = 31.25 nsec, and when the duty of one clock is 50%, the pulse width of the high level is 15.625 nsec. Such a clock having a short pulse width is affected by an electromagnetic field generated by a digital signal or the like of another circuit even in a short signal line transmission line. Receive. Such a variation becomes a large ratio (notable to be ignored) when a high-speed clock is used. For example, the duty of the clock may vary within a range of about 50% ± 10%.

If such a change in the duty occurs, the output RZ data DA1 of the code conversion circuit 3 also has a change in the duty and further influences and changes the duty of the optically modulated optical signal. When the RZ data and the clock are extracted from the optical signal by the optical receiver module on the receiving side, the duty ratio of the optical signal is received while varying, so that the accurate R
Since there is a problem that the Z data and the clock cannot be extracted, only the fixed frequency f0 is extracted by the tuning circuit 4, and the clock CK1 of 50% duty is obtained by limiting the frequency by the limiter circuit 5. Since the tuning circuit is constituted by using a crystal oscillator or the like for the device 4, it is difficult to integrate the tuning circuit.
Was limited by the configuration.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to compensate for a duty to a desired value with a simple configuration even when a clock whose duty fluctuates is taken. It is to provide a clock duty compensating circuit that can achieve the above.

[0011]

In order to achieve the above object, the present invention has been realized by providing the first invention with the following characteristic means.

That is, (1) the input clock signal
The rising and falling edges of a pulsed waveform
Shaped to have a kana shape and output as a filter signal
And (2) the above-described standing of the filter signal.
Rising and falling coincide with the first threshold level
At the same timing, it is obtained by inverting the filter signal.
First inverting means for outputting a first inverted signal;
Of the first inverted signal of the second reference level with respect to a second threshold level.
Output a second inverted signal obtained by inverting
(2) an average of the first inverted signal
The difference between the level and the average level of this second inverted signal
, And a difference means for outputting the difference signal; (5)
The filter signal or the first threshold level is
The duty ratio of the first inverted signal.
Correction means for controlling the first inverted signal.
The duty of the second inversion signal is compensated to a predetermined value by controlling the duty.

[0013] The second invention is also provided with the following characteristic means.

That is, (1) the input clock signal
The rising and falling edges of a pulsed waveform
Shaped to have a kana shape and output as a filter signal
And (2) the above-described standing of the filter signal.
Rising and falling coincide with the first threshold level
At the same timing, it is obtained by inverting the filter signal.
First inverting means for outputting a first inverted signal;
The reference level signal for setting the desired clock duty
Reference signal output means for outputting a signal;
The difference between the average level of the inverted signal and this reference level signal
A difference means for calculating the minute and outputting the difference signal;
(5) The filter signal or the first threshold level is
By correcting with the difference signal, the duplication of the first inverted signal is performed.
Correction means for controlling the clock duty, and the clock duty of the first inverted signal is compensated to a predetermined value.

[0015]

According to the first aspect, the filter signal is
The waveform becomes blunt. The rise of this blunted waveform
And the first threshold level as a reference for inversion
By changing the relative level of the
Since the pulse width of the signal fluctuates, the
Can be controlled. Therefore, the input
Lock waveform is pulsed and duty fluctuates
Even in such a case, the clock compensated for the desired duty value
Output. Explain in more detail
According to the first aspect of the present invention, a difference between the average level value of the first inverted signal and the average level value of the second inverted signal is obtained, and the bias signal of the filter signal is corrected using the difference signal. since it is supplied like the first inverting means and the determination timing i.e. for the first threshold level
The rising and falling of the filter signal is the first
Is the correction timing that matches the threshold level, the duty of the first and second inverted signal that can be varied accordingly, and the average level value of the first inverted signal, a second
When the average level value of the inverted signal becomes equal (that is, when the duty becomes a predetermined value, for example, 50%), the difference signal value is output as 0, the updating of the bias correction value for the filter signal is stopped, and the A duty clock can be output from the first and second inversion means.

Further, by correcting the first threshold level of the first inverting means using the difference signal, the timing for determining the logical value of the input filter signal is corrected, and the first and second threshold values are corrected in the same manner as described above. Can be changed, and the average level value of the first inverted signal becomes equal to the average level value of the second inverted signal (that is, the duty becomes a predetermined value, for example, 50%).
And the difference signal value outputs 0 to stop updating the level correction with respect to the first threshold level, and output a clock of a predetermined duty from the first and second inverting means.

Further, according to the second aspect, the reference level signal is supplied to the difference means as a DC voltage signal corresponding to a desired duty or the like, so that the difference from the average level value of the inverted signal of the inversion means is obtained. By determining the value and supplying it to the inverting means by performing bias correction or the like on the filter signal based on the difference value, the determination timing for the threshold level is corrected, and the duty of the inverted signal can be changed accordingly, When the average level value of the inverted signal becomes equal to the reference level value (that is, the duty becomes a desired duty), the difference signal value is output as 0, the updating of the bias correction value for the filter signal is stopped, and the reference is performed. A clock having a desired duty corresponding to the level value can be output from the inversion means.

Further, by correcting the threshold level of the inverting means with the difference signal of the second invention, the timing for determining the logical value for the input filter signal is corrected, and the duty of the inverted signal is changed in the same manner as described above. When the average level value of the inverted signal becomes equal to the reference level value (that is, the desired duty is reached), the difference signal value outputs 0, and the updating of the level correction value for the threshold level is stopped. Thus, a clock having a desired duty corresponding to the reference level value can be output from the inversion means.

With the above configuration, it can be realized with a simple configuration, and can be compensated for a desired clock duty, which is suitable for integration.

[0020]

Next, an embodiment in which the present invention is applied to a clock duty compensation circuit of an optical transmission module will be described with reference to the drawings.

First Embodiment of Optical Transmission Module An object of the first embodiment is to provide an optical transmission module having a simple configuration and capable of performing optimum code conversion even when a clock whose duty varies. Realize.

In order to achieve this object, a clock duty compensating circuit for compensating the duty of the input clock whose duty fluctuates to 50% is provided, and the input NRZ data is converted to the RZ data using the compensated clock. To convert the RZ data into an optical signal.

FIG. 1 is a functional block diagram of the optical transmission module according to the first embodiment.

In FIG. 1, the optical transmission module includes a code conversion circuit 12, a light emitting element driving circuit 21, a light emitting element 22, and a clock duty compensation circuit 1. The clock duty compensation circuit includes one inverter 13 and 14, an operational amplifier 15, an input low-pass filter 10, resistors R17 and R16, a bias resistor R18, and a capacitor C19. The input low-pass filter 10 includes a resistor 24 and a capacitor C25.

The input NRZ data DA3 (FIG. 3B) is supplied to the code conversion circuit 12. On the other hand, input clock CK
2 (FIG. 3A) is the resistance 2 of the input low-pass filter circuit.
4 is supplied. Here, the cut-off frequency fc of the input low-pass filter circuit 10 is, for example, fc = 1 / (2
π · R24 · C25), and the values of R24 and C25 are set so that the relationship between the cutoff frequency fc and the pulse frequency f0 of the input clock CK2 satisfies the relationship f0 ≦ fc. More strictly, it is desirable to set in consideration of an allowable worst input clock Duty. The output of this input low-pass filter 10 is input clock CK2
Waveform that is somewhat distorted (smooth waveform)
(FIG. 3C), which is to make it easier to detect the rising timing of the inverter 13 from a low level to a high level. For example, if the rise is abrupt, there is a problem that it is practically difficult to detect a level change at the input of the inverter 13. Thus, the output signal S1 of the input low-pass filter 10 is supplied to the inverter 13.

The inverter 13 inverts the input signal S1 and supplies the inverted signal CK4 to the non-inverting input (non-inverting input) of the operational amplifier 15 via the inverter 14 and the resistor 16. The inverter 14 inverts the input signal CK4 to supply the inverted signal CK3 to the code conversion circuit 12 and to supply the inverted signal CK3
The signal is supplied to the negative-phase (-) input (inverted input) of the operational amplifier 15 through the line 17. Signal C output from inverter 13
K4 is an integrated signal SB4 whose high range is cut off by a low-pass filter composed of a resistor R16 and a capacitor C19.
Is supplied to the positive phase (+) input.

The output signal CK3 of the inverter 14 is also supplied to the negative phase (-) input of an integrated signal SB3 whose high frequency is cut off by a low-pass filter composed of a resistor R17 and a capacitor C19. Cutoff frequency of the above two low-pass filters 1 / (2π · R17 · C19) = f
c1 and cutoff frequency 1 / (2π · R16 · C1
9) = fc2 needs to have a relationship of fc1 = fc2, and it is desirable to have a relationship of R17 = R16. It is desirable that the relationship between the frequency f0 of the input clock CK2 and the relationship f0> fc1 = fc2 be set. That is, the rectangular signals supplied from the inverters 13 and 14 are sufficiently integrated to obtain an average direct current (DC) level with a small level change, and the positive phase (+) input and the negative phase (-) input of the operational amplifier 15 are obtained. In order to supply them.

Then, for example, Du of the input clock CK2
ty is 70% (that is, when the high level is 70% and the low level is 30%), and the duty of the output clock CK4 of the inverter 13 is 30% (that is, the high level is 30%).
And when the low level is 70%. ), The output of the inverter 14 is inverted and the duty of the clock CK3 becomes 70.
%. Then, for example, the clocks CK4 and CK3
Are defined as SB4 and SB3, the magnitude relationship of the integral value (DC level) in the case of Duty is a relationship of SB3> SB4, and the operational amplifier 15 is a differential amplifier. Output (SB4-SB3)
Is output to the inverter 1 via the bias resistor R18.
The signal S1 is supplied to the input 3 by performing the bias level correction for the differential output (SB4-SB3) on the signal S1.

For example, when the value of the above SB4 is 1 V,
If the value of 3 is 2V, SB4-SB3 = -1V is added to the signal S1 and supplied to the input of the inverter 13.
In this case, the direct current (DC) level (bias level) of the signal S1 is reduced by, for example, -1 V as compared with the level before the correction, so that the inverter 13 having a predetermined threshold level outputs
1 tends to detect the upper side of the waveform, and in such a tendency, the time required to detect the high level of the input waveform tends to be shorter, and the high level time width of the output waveform of the inverter 13 becomes shorter. The duty of the clock is reduced from 70% to 50%. When the value of SB4-SB3 becomes 0 after performing the above correction, it is determined that the duty has become 50%, and the updating of the bias correction is stopped. In this way, clocks CK3 and CK4 (FIGS. 3D and 3E) having a duty of 50% can be obtained.

As described above, the signal CK is obtained.
4 and the clock duty of the signal CK3 can be compensated to 50%. The reason for setting the clock duty to 50% is to set the duty of the output DA4 of the code conversion circuit 12 to 50%.
%, The duty of the optical signal is also set to 50%, and output to the transmission line, so that there is a high probability that a clock or data is obtained after converting the light in the optical receiving module on the receiving side into an electric signal and then obtaining it. It can be reproduced faithfully.

The clock CK3 obtained as described above is supplied to the code conversion circuit 12. The code conversion circuit 12 performs, for example, AND operation on the input NRZ data DA3 by the clock CK3 to obtain RZ data DA4 (FIG. 3F), and supplies the RZ data DA4 to the light emitting element driving circuit 21 to drive the light emitting element 22. And supplies it to the light emitting element 22. The light emitting element 22 converts the signal into an optical signal using a laser diode or the like and outputs the signal to a transmission line.

FIG. 3 is an operation timing chart of the optical transmission module according to the first embodiment.

In FIG. 3, (A) shows the waveform of the input clock CK2 whose duty fluctuates. (B)
Is the timing of the input NRZ data DA3. (C)
4 is a waveform diagram of the integrated output signal S1 of the input low-pass filter 10. (D) is an output of the inverter 14, and is a waveform diagram of the clock CK3 when the duty is compensated to 50%. (E) is an output of the inverter 13 and is a waveform diagram of the clock CK4 when the duty is compensated to 50%. (F) is an output of the code conversion circuit 12 and is a waveform chart converted into RZ data DA4.

According to the first embodiment, even if the clock CK2 whose clock duty fluctuates is supplied,
Since the duty of the clock CK3 supplied to the code conversion circuit 12 can always be compensated and supplied to 50%, the RZ data obtained by code conversion can also be compensated for the duty to 50%, and the RZ data is optically converted. And an optimal optical signal can be output.

The clock duty compensating circuit 1 does not use a crystal oscillator as in the prior art, but is composed of only a resistor, a capacitor, an inverter, and an operational amplifier. Therefore, the circuit configuration is simple and the integration is easy. This can contribute to downsizing of the optical transmission module.

Second Embodiment of Optical Transmission Module FIG. 4 is a functional block diagram of an optical transmission module according to a second embodiment.

In FIG. 4, the clock duty compensating circuit 2 of the optical transmission module eliminates the resistor R17 of FIG. 1 and provides a reference power supply circuit 26 instead. It is configured to supply to the phase (-) input (inverting input), and one end of the capacitor C19 is connected to the ground.
Other configurations were realized with the same configuration as FIG. The same functional blocks as those in FIG. 1 are denoted by the same reference numerals.

The clock duty compensation circuit 2 previously determines a reference voltage signal Vref for compensating for a predetermined clock duty from the reference power supply circuit 26 and supplies the reference voltage signal Vref to the negative phase (−) of the operational amplifier 15. On the other hand, the inverter 13 supplies the inverted signal CK4 to the low-pass filter including the resistor R16 and the capacitor C19 to obtain an average direct current (DC) level signal SB4 as in FIG. (Non-inverting input).

The operational amplifier 15 outputs a difference between the direct current (DC) level signal SB4 and the reference voltage signal Vref, and supplies this difference voltage signal to the inverter 13 via the bias resistor R18. By doing so, the bias voltage of the integration signal S1 is corrected by the difference voltage signal and supplied to the inverter 13.

When the bias voltage of the integration signal S1 changes, 1 and 0 are determined by the predetermined threshold value of the inverter 13 as described in the first embodiment. A logic 1 for the integration signal S1 is determined. Since the timing can be changed, the output pulse width of the inverter 13 can be changed, that is, the clock duty can be changed. Then, the direct current (DC) level signal SB4
The output of the inverter 13 is corrected until the difference between the reference voltage signal Vref and the reference voltage signal Vref becomes zero.
Is supplied to the inverter 14 after being compensated for by a predetermined clock duty corresponding to.

The code conversion and optical conversion after the inverter 14 are the same as those in the first embodiment, so that the description of the operation is omitted.

The reason why the inverters 13 and 14 are connected in two stages is a two-stage configuration in order to make the phases of the input NRZ data DA3 and the clock the same.

According to the above second embodiment, even if the clock CK2 whose clock duty fluctuates is supplied,
Since the duty of the clock CK3 supplied to the code conversion circuit 12 can always be compensated and supplied to the duty corresponding to the reference voltage signal, the duty can also be constantly compensated for the RZ data obtained by code conversion. Data can be optically converted to output an optimal optical signal.

The clock duty compensating circuit 1 does not use a conventional crystal oscillator, and is composed of only a resistor, a capacitor, an inverter, an operational amplifier, and a reference power supply circuit. Thus, integration can be facilitated, and the optical transmission module can be downsized.

The clock duty can be freely changed by changing the reference voltage signal Vref.

In FIGS. 1 and 4 of the above embodiment,
Although the input low-pass filter 10 is used, the invention is not limited to this. For example, the basic clock frequency f0 of the input clock CK2 is stored, and it can be realized by a band-pass filter, for example, on the premise that a frequency component higher than the frequency f0 is not included. In FIGS. 1 and 4, the input low-pass filter 10 may be configured using an active element (for example, an operational amplifier).

In FIGS. 1 and 4 of the above embodiment,
Although the operational amplifier 15 is used, the invention is not limited to this. For example, it can also be realized by configuring a differential circuit using a bipolar transistor, an FET, or the like. In FIGS. 1 and 4, the inverters 13 and 14 as digital gates are used, but the invention is not limited to this. For example, it can be realized by a configuration in which inversion is performed by an operational amplifier or the like.

In the above embodiment, the voltage is corrected by the bias of the signal S1 at the output of the operational amplifier 15, but the present invention is not limited to this. For example, instead of correcting the bias of the signal S1, inversion is performed by an operational amplifier to change the threshold level for determining the logic level, and the threshold level for inversion is corrected by the output of the operational amplifier 15. Also, the clock duty can be compensated to a desired value.

In the optical transmission module of the above embodiment, the transmission of an optical signal has been described. However, the optical receiving module for extracting data and a clock from the optical signal output from the optical transmission module is also used for the clock duty compensation. Circuits can be applied. For example, when an optical receiving module receives an optical signal, it converts the optical signal into an electrical signal by a light receiving element, and supplies the electrical signal as received RZ data to, for example, a decoding conversion circuit. Further, a clock is extracted from the received RZ data by a clock extracting circuit, and when the duty of the clock fluctuates due to the influence of the transmission line, the fluctuating clock is detected by the clock compensating circuit of FIG. 1 or FIG. The duty can be compensated to a desired value, and the RZ data can be converted into NRZ data and output by the decoding conversion circuit using the compensated clock.

In the code conversion circuit 12 shown in FIGS. 1 and 4 in the above embodiment, an example has been described in which input NRZ data is converted into RZ data. However, the present invention is not limited to this. For example, CMI (Co
The present invention can also be applied to a code conversion circuit that converts a code into a de Mark Inversion (de Mark Inversion) code. This CMI code converts, for example, logic 0 of input NRZ data to 01,
It is obtained by converting 1 to 11 or 00. This code conversion circuit also has several D flip-flops,
It can be easily realized with several logic gates.

In the above embodiments, the clock duty compensation circuit is applied to the optical transmission module as an example. However, the present invention is not limited to this. In addition, the present invention can be applied to circuits and devices that require a clock.

[0052]

As described above, according to the clock duty compensation circuits of the first and second inventions, the input pulse
Even if the duty of the clock with the
Rise and fall of filter signal with trapped waveform
Relative to the first threshold level serving as a reference for inversion.
The pulse width of the first inverted signal by changing the
, The duty of the first inverted signal is controlled.
Can be Therefore, the waveform of the input clock
Is pulsed and the duty fluctuates.
Output a clock compensated to the desired duty value.
Can be In addition, since each means has a simple configuration and is easy to integrate, it can contribute to the miniaturization of the circuit.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an optical transmission module according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram of an optical transmission module according to a conventional example.

FIG. 3 is an operation timing chart of the optical transmission module according to the first embodiment of the present invention.

FIG. 4 is a functional block diagram of an optical transmission module according to a second embodiment of the present invention.

[Explanation of symbols]

1, 2, clock duty compensation circuit, 10 input low-pass filter, 13, 14 inverter, 15 operational amplifier, 26 reference power supply circuit, C19 capacitor, R1
6, R17: resistance.

Claims (2)

(57) [Claims] 1. A pulse-like waveform of an input clock signal.
The rise and fall into a smooth shape.
Filter that outputs the signal as a filter signal
Means and the rising and falling of the filter signal
At the timing that matches the first threshold level,
Output a first inverted signal obtained by inverting the data signal.
1 inversion means and the first inversion signal with reference to a second threshold level.
A second inverted signal obtained by further inversion is output.
Second inverting means, an average level of the first inverted signal, and the second inverted signal.
Obtain the difference from the average level of the signal and calculate the difference signal.
A difference means for outputting the filter signal or the first threshold level.
The duty ratio of the first inverted signal.
And a correction means for controlling the duty ratio of the second inverted signal to control the duty ratio of the first inverted signal to a predetermined value. 2. A pulse-like waveform of an input clock signal.
The rise and fall into a smooth shape.
Filter that outputs the signal as a filter signal
Means and the rising and falling of the filter signal
At the timing that matches the first threshold level,
Output a first inverted signal obtained by inverting the data signal.
1 inversion means and a reference level for setting a desired clock duty
A reference signal output means for outputting a signal; an average level of the first inverted signal;
A difference method for calculating a difference from a signal and outputting the difference signal
Stage and the filter signal or first threshold level
The duty ratio of the first inverted signal.
A clock duty compensating circuit comprising: a correction unit that controls the clock duty of the first inverted signal to a predetermined value.