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JP3137765B2 - Power converter using semiconductor element with control pole for rectifier circuit - Google Patents
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JP3137765B2 - Power converter using semiconductor element with control pole for rectifier circuit - Google Patents

Power converter using semiconductor element with control pole for rectifier circuit

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Publication number
JP3137765B2
JP3137765B2 JP04261129A JP26112992A JP3137765B2 JP 3137765 B2 JP3137765 B2 JP 3137765B2 JP 04261129 A JP04261129 A JP 04261129A JP 26112992 A JP26112992 A JP 26112992A JP 3137765 B2 JP3137765 B2 JP 3137765B2
Authority
JP
Japan
Prior art keywords
semiconductor element
voltage
control
control electrode
transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP04261129A
Other languages
Japanese (ja)
Other versions
JPH06113537A (en
Inventor
直樹 村上
肇 並木
一彦 榊原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
NTT Inc USA
Original Assignee
Nippon Telegraph and Telephone Corp
NTT Inc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, NTT Inc USA filed Critical Nippon Telegraph and Telephone Corp
Priority to JP04261129A priority Critical patent/JP3137765B2/en
Publication of JPH06113537A publication Critical patent/JPH06113537A/en
Application granted granted Critical
Publication of JP3137765B2 publication Critical patent/JP3137765B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は整流手段としてFETの
ような制御極付半導体素子を用いて、整流回路の低損失
化を図るようにした電力変換装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter which uses a semiconductor device with a control electrode such as an FET as a rectifier to reduce the loss of a rectifier circuit.

【0002】[0002]

【従来の技術】制御極付半導体素子を整流回路に使用し
た電力変換装置の従来例の回路構成を図3に、その動作
波形を図4に示す。
2. Description of the Related Art FIG. 3 shows a circuit configuration of a conventional example of a power converter using a semiconductor element with a control electrode in a rectifier circuit, and FIG. 4 shows operation waveforms thereof.

【0003】図3において、1は直流電源、2はFET
のようなスイッチング素子、3はトランス、4,5はF
ETのような制御極付半導体素子であって4は整流用制
御極付半導体素子、5はフライホイール用制御極付半導
体素子、6は平滑用チョークコイル、7は平滑用コンデ
ンサ、8は出力端子、9,10はそれぞれ制御極付半導
体素子4,5の寄生ダイオード、n1はトランス3の1
次巻線、n2はトランス3の2次巻線である。
In FIG. 3, 1 is a DC power supply and 2 is a FET.
, 3 is a transformer, 4 and 5 are F
A semiconductor element with a control electrode such as ET, 4 is a semiconductor element with a control electrode for rectification, 5 is a semiconductor element with a control electrode for flywheel, 6 is a choke coil for smoothing, 7 is a capacitor for smoothing, and 8 is an output terminal. , 9 and 10 are parasitic diodes of the semiconductor elements 4 and 5 with control electrodes, respectively, and n 1 is one of the transformers 3.
A secondary winding, n 2, is a secondary winding of the transformer 3.

【0004】トランス3の1次巻線n1には、直流電源
1とスイッチング素子2の直列回路が接続されている。
一方、トランス3の2次巻線n2の一側(黒丸印(・
印)側)には、平滑用チョークコイル6と平滑用コンデ
ンサ7の直列回路にフライホイール用制御極付半導体素
子5を並列に接続した回路におけるフライホイール用制
御極付半導体素子5の一端が直接接続され、2次巻線n
2の他側には、前記回路におけるフライホイール用制御
極付半導体素子5の他端が整流用制御極付半導体素子4
を介して接続されている。ここで、整流用制御極付半導
体素子4の制御極は、2次巻線n2の一側に、フライホ
イール用制御極付半導体素子5の制御極は2次巻線n2
の他側に、それぞれ接続されている。負荷接続用の出力
端子8は、平滑用コンデンサ8の両端に接続されてい
る。
A series circuit of a DC power supply 1 and a switching element 2 is connected to a primary winding n 1 of a transformer 3.
On the other hand, 2 on one side of the winding n 2 of the transformer 3 (filled circle (-
One side of the semiconductor element 5 with the control electrode for flywheel in a circuit in which the semiconductor element 5 with the control electrode for flywheel is connected in parallel to the series circuit of the choke coil 6 for smoothing and the capacitor 7 for smoothing Connected, secondary winding n
The 2 other side, the other end control commutation of the flywheel control Kiwametsuki semiconductor element 5 in the circuit Kiwametsuki semiconductor element 4
Connected through. Here, the control electrode of the rectifying control Kiwametsuki semiconductor element 4, on one side of the secondary winding n 2, the control electrode of the control flywheel Kiwametsuki semiconductor element 5 is the secondary winding n 2
On the other side. The output terminal 8 for connecting a load is connected to both ends of the smoothing capacitor 8.

【0005】図3及び図4において、a,b,cはそれ
ぞれ制御極付半導体素子4の制御極電圧(FETの場
合、ゲート・ドレイン間電圧)、出力端子電流(FET
の場合、ソースからドレインへ流れる電流)、出力端子
電圧(FETの場合、ソース・ドレイン間電圧)であ
り、d,e,fはそれぞれフライホイール用制御極付半
導体素子5の制御極電圧(FETの場合、ゲート・ドレ
イン間電圧)、出力端子電流(FETの場合、ソースか
らドレインへ流れる電流)、出力端子電圧(FETの場
合、ソース・ドレイン間電圧)である。
In FIGS. 3 and 4, a, b, and c denote a control pole voltage (gate-drain voltage in the case of FET) and an output terminal current (FET
, The current flowing from the source to the drain) and the output terminal voltage (the source-drain voltage in the case of the FET), and d, e, and f are the control pole voltages (FETs) of the semiconductor element 5 with the control pole for flywheel, respectively. In the case of, a gate-drain voltage), an output terminal current (a current flowing from a source to a drain in the case of an FET), and an output terminal voltage (a source-drain voltage in the case of an FET).

【0006】図3の従来例の回路動作を図4を用いて説
明すると、次のとおりである。図4中に示す時刻t0
スイッチング素子2の制御極に正の電圧が印加される
と、スイッチング素子2がオンしてトランス3の1次巻
線n1に直流電源1の電圧が印加され、2次巻線n2に黒
丸印(・印)側が正の極性の電圧が生じる。これにより
トランス3の励磁インダクタンス(図示せず)が励磁さ
れるとともに、制御極電圧aが正の極性となって整流用
制御付半導体素子4がオンし(図4中のa,c参照)、
電流は出力端子8の下側端子から整流用制御極付半導体
素子4、2次巻線n2、チョークコイル6、出力端子8
の上側端子を通って負荷(図示せず)に流れる(図4中
のb参照)。
The circuit operation of the conventional example shown in FIG. 3 will be described below with reference to FIG. When a positive voltage is applied to the control pole of switching element 2 at time t 0 shown in FIG. 4, switching element 2 is turned on, and the voltage of DC power supply 1 is applied to primary winding n 1 of transformer 3. , black circles in the secondary winding n 2 (· mark) side is positive polarity voltage occurs. As a result, the exciting inductance (not shown) of the transformer 3 is excited, the control pole voltage a becomes positive polarity, and the rectifying control semiconductor element 4 is turned on (see a and c in FIG. 4).
The current flows from the lower terminal of the output terminal 8 to the semiconductor element 4 having the control electrode for rectification, the secondary winding n 2 , the choke coil 6, and the output terminal 8.
Flows to a load (not shown) through the upper terminal (see b in FIG. 4).

【0007】時刻t1でスイッチング素子2の制御極の
電圧を零にすると、スイッチング素子2がオフする。こ
こで、トランス3の励磁インダクタンスに蓄えられたエ
ネルギーにより、トランス3の励磁インダクタンスとス
イッチング素子2の出力容量(FETの場合、ドレイン
・ソース間容量とドレイン・ゲート間容量の和)、整流
用制御極付半導体素子4の出力容量(FETの場合、ド
レイン・ソース間容量とドレイン・ゲート間容量の
和)、フライホイール用制御極付半導体素子5の入力容
量(FETの場合、ゲート・ソース間容量とドレイン・
ゲート間容量の和)との間で共振が生じる。これにより
トランス3の1次巻線n1、2次巻線n2の電圧が反転
し、黒丸印(・印)側が負の極性の正弦波状電圧(以
後、フライバック電圧とよぶ。)が生じる。この電圧で
制御極電圧aが負の極性となって整流用制御極付半導体
素子4がオフし(図4中のa,c参照)、制御極電圧d
が正の極性となってフライホイール用制御付半導体素子
5がオンする(図4中のd,f参照)。チョークコイル
6の電流は、フライホイール用制御極付半導体素子5を
通り、出力端子8に接続される負荷を通って還流する
(図4中のe参照)。
When the voltage of the control electrode of the switching element 2 is reduced to zero at time t 1 , the switching element 2 is turned off. Here, by the energy stored in the exciting inductance of the transformer 3, the exciting inductance of the transformer 3 and the output capacity of the switching element 2 (sum of the drain-source capacity and the drain-gate capacity in the case of FET), rectification control The output capacitance of the semiconductor element 4 with a pole (the sum of the capacitance between the drain and the source and the capacitance between the drain and the gate in the case of the FET), and the input capacitance of the semiconductor element 5 with the control pole for the flywheel (the capacitance between the gate and the source in the case of the FET) And drain
(Sum of capacitance between gates). As a result, the voltages of the primary winding n 1 and the secondary winding n 2 of the transformer 3 are inverted, and a sine wave voltage (hereinafter referred to as a flyback voltage) having a negative polarity on the black circle (•) side is generated. . With this voltage, the control electrode voltage a becomes negative polarity and the semiconductor element 4 with the control electrode for rectification is turned off (see a and c in FIG. 4), and the control electrode voltage d
Becomes positive polarity, and the flywheel-controlled semiconductor element 5 is turned on (see d and f in FIG. 4). The current of the choke coil 6 flows back through the load connected to the output terminal 8 through the semiconductor element 5 with the control electrode for flywheel (see e in FIG. 4).

【0008】時刻t2でトランス3のフライバック電圧
が零になるとフライホイール用制御極付半導体素子5が
オフし(図4中のd,f参照)、チョークコイル6の電
流はフライホイール用制御極付半導体素子5の寄生ダイ
オード10を通り、出力端子8に接続される負荷を通っ
て還流する(図4中のe参照)。
When the flyback voltage of the transformer 3 becomes zero at time t 2 , the semiconductor element 5 with the flywheel control pole is turned off (see d and f in FIG. 4), and the current of the choke coil 6 is controlled by the flywheel. The electric current returns through the parasitic diode 10 of the semiconductor element 5 with a pole and through the load connected to the output terminal 8 (see e in FIG. 4).

【0009】時刻t3でスイッチング素子2の制御極に
正の電圧が印加されるとスイッチング素子2がオンし、
トランスの2次巻線n2に再び黒丸印(・印)側が正の
極性の電圧が誘起して、制御極電圧aが正の極性となっ
て整流用制御極付半導体素子4がオンし、制御極電圧d
が負の極性となってフライホイール用制御極付半導体素
子5がオフし、以後、同様の動作を繰り返す。
When a positive voltage is applied to the control pole of switching element 2 at time t 3 , switching element 2 turns on,
Trans again filled circle in the secondary winding n 2 (· mark) side is positive polarity voltage induced control electrode voltage a rectification control Kiwametsuki semiconductor element 4 becomes positive polarity is turned on, Control pole voltage d
Becomes negative polarity, the semiconductor element 5 with the control electrode for flywheel is turned off, and thereafter the same operation is repeated.

【0010】さて、図3の回路では、整流用制御極付半
導体素子4にはオンすべき期間(t0〜t1)中、制御極
電圧aが印加されるが、フライホイール用制御極付半導
体素子5の制御極電圧dは主トランス3のフライバック
電圧を用いているため、オンすべき期間(t1〜t3)の
うちフライバック電圧の発生しているt1〜t2の期間し
か制御極に駆動電圧が印加されない(図4中のd参
照)。従ってt2〜t3の期間にフライホイール用制御極
付半導体素子5はオンせず、寄生ダイオード10がオン
して、この期間の出力端子電圧がフライホイール用制御
極付半導体素子5・オン時の出力端子間電圧(FETの
場合、ソース・ドレイン間電圧)よりも上昇する(図4
中のf参照)。
[0010] Now, in the circuit of Figure 3, during the period for on-the rectifying control Kiwametsuki semiconductor element 4 (t 0 ~t 1), but the control electrode voltage a is applied, the control flywheel Kiwametsuki since the control electrode voltage d of the semiconductor element 5 is used flyback voltage of the main transformer 3, the flyback voltage generator to have a period of t 1 ~t 2 of the period to be on (t 1 ~t 3) Only the drive voltage is applied to the control pole (see d in FIG. 4). Thus t 2 ~t flywheel control Kiwametsuki semiconductor element 5 in the period of 3 does not turn on, the parasitic diode 10 is turned on, when the output terminal voltage is controlled flywheel Kiwametsuki semiconductor element 5 On this period (The voltage between the source and the drain in the case of FET).
(F in middle).

【0011】[0011]

【発明が解決しようとする課題】ところで、FETのよ
うな制御極付半導体素子を整流回路に用いるのは、オン
電圧を0.1〜0.2Vと低く抑えて低損失化を図るた
めであるが、上記従来例の電力変換装置の回路構成では
フライホイール用制御極付半導体素子5の制御極に駆動
電圧が印加されない期間があるため、このような整流回
路の低損失化の効果が十分に発揮できないという欠点が
あった。
The reason why a semiconductor element with a control electrode such as an FET is used in a rectifier circuit is to reduce the on-voltage to 0.1 to 0.2 V to reduce the loss. However, in the circuit configuration of the above-described conventional power converter, there is a period during which no drive voltage is applied to the control pole of the semiconductor element 5 with the flywheel control pole, so that the effect of reducing the loss of such a rectifier circuit is sufficient. There was a drawback that it could not be demonstrated.

【0012】本発明は以上の欠点を除去するためになさ
れたものであり、その目的は、フライホイール用制御極
付半導体素子のオンすべき全期間にわたって、該フライ
ホイール用制御極付半導体素子がオンするのに必要な制
御極電圧が得られるようにして、整流回路の低損失化の
効果が十分発揮できるようにした電力変換装置を提供す
ることにある。
SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor device with a control electrode for a flywheel which is turned on over the entire period when the semiconductor device with a control electrode for a flywheel is to be turned on. It is an object of the present invention to provide a power converter in which a control pole voltage necessary for turning on is obtained, so that the effect of reducing the loss of the rectifier circuit can be sufficiently exhibited.

【0013】[0013]

【課題を解決するための手段】本発明は上記の目的を達
成するため、本発明においては、直流電源とスイッチン
グ素子の直列回路をトランスの1次巻線に接続し、チョ
ークコイルと負荷の直列回路に第1の制御極付半導体素
子を並列に接続した回路における該制御極付半導体素子
の両端のうち一端を前記トランスの2次巻線の一側に直
接接続し、その他端を第2の制御極付半導体素子を介し
て前記2次巻線の他側に接続して成り、前記スイッチン
グ素子を周期的にオン、オフしたときに生じる前記トラ
ンスの2次巻線出力電圧を、前記第1の制御極付半導体
素子のオン時には第2の制御極付半導体素子がオフ、前
者がオフの時には後者がオンの如く、交互に動作させる
ことにより、整流、平滑して負荷に電力を供給するよう
にした電力変換装置において、前記第2の制御極付半導
体素子と並列にコンデンサを接続し、前記スイッチング
素子がオフの時に該スイッチング素子が次にオンする直
前まで前記トランスの2次巻線に生じるフライバック電
圧が前記第1の制御極付半導体素子の制御極の閾値以上
になるように前記コンデンサの静電容量値を設定した構
成とする。
According to the present invention, in order to achieve the above object, in the present invention, a series circuit of a DC power supply and a switching element is connected to a primary winding of a transformer, and a choke coil and a load are connected in series. In a circuit in which a first semiconductor element with a control pole is connected in parallel to a circuit, one end of both ends of the semiconductor element with a control pole is directly connected to one side of a secondary winding of the transformer, and the other end is connected to a second side. The secondary winding output voltage of the transformer, which is connected to the other side of the secondary winding via a semiconductor element with a control pole and is generated when the switching element is periodically turned on and off, is connected to the first winding. When the semiconductor element with a control electrode is turned on, the second semiconductor element with a control electrode is turned off, and when the former is off, the latter is turned on. Power conversion equipment , A capacitor is connected in parallel with the second control electrode-equipped semiconductor element, and when the switching element is off, the flyback voltage generated in the secondary winding of the transformer until immediately before the switching element is next turned on is It shall be the structure in which to set the capacitance value of the capacitor to be equal to or greater than the threshold value of the control electrode of the first control Kiwametsuki semiconductor device.

【0014】[0014]

【作用】本発明の制御極付半導体素子を整流回路に用い
た電力変換装置においては、フライホイール用制御極付
半導体素子に並列に所定の容量のコンデンサを付加し
て、トランスのフライバック電圧発生期間をスイッチン
グ素子のオフ期間の全期間に延ばし、かつ、フライバッ
ク電圧をフライホイール用制御極付半導体素子の閾値電
圧より高くすることにより、フライホイール用制御極付
半導体素子がオンすべき全期間にわたってオンさせて、
そのオン電圧を低く押さえ、低損失な整流回路を実現し
ている。
The semiconductor device with a control electrode according to the present invention is used in a rectifier circuit.
Power converters with flywheel control poles
A capacitor with a predetermined capacity is attached in parallel with the semiconductor element.Addition
Switch on the transformer flyback voltage generation period.
And the flyback
Control voltage for the flywheel
With control pole for flywheel by setting higher than pressure
It is turned on for the entire period when the semiconductor element is to be turned on,
The ON voltage is kept low to realize a low-loss rectifier circuit.
ing.

【0015】[0015]

【実施例】以下、本発明の一実施例を、図面に基づいて
詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【0016】図1は本発明の一実施例の構成を説明する
ための回路図であり、図2はその回路の動作を説明する
ための動作波形図である。図1において、1は直流電
源、2はスイッチング素子、3はトランス、4は整流用
制御極付半導体素子、5はフライホイール用制御極付半
導体素子、6は平滑用チョークコイル、7は平滑用コン
デンサ、8は出力端子、9,10はそれぞれ制御極付半
導体素子4、5の寄生ダイオード、11はコンデンサ、
1はトランス3の1次巻線、n2はトランス3の2次巻
線である。
FIG. 1 is a circuit diagram for explaining the structure of one embodiment of the present invention, and FIG. 2 is an operation waveform diagram for explaining the operation of the circuit. In FIG. 1, 1 is a DC power supply, 2 is a switching element, 3 is a transformer, 4 is a semiconductor element with a control electrode for rectification, 5 is a semiconductor element with a control electrode for flywheel, 6 is a choke coil for smoothing, and 7 is a smoothing choke coil. A capacitor, 8 is an output terminal, 9 and 10 are parasitic diodes of the semiconductor elements 4 and 5 with control electrodes, 11 is a capacitor,
n 1 is a primary winding of the transformer 3, and n 2 is a secondary winding of the transformer 3.

【0017】上記各部材の接続構成は、次のとおりであ
る。トランス3の1次巻線n1には、直流電源1とスイ
ッチング素子2の直列回路が接続される。一方、トラン
ス3の2次巻線n2の一側(黒丸(・)印側)には平滑
用チョークコイル6と平滑用コンデンサ7の直列回路に
フライホイール用制御極付半導体素子5を並列に接続し
た回路におけるフライホイール用制御極付半導体素子5
の一端が直接接続され、2次巻線n2の他側には、前記
回路におけるフライホイール用の制御極付半導体素子5
の他端が整流用制御極付半導体素子4を介して接続され
ている。ここで、整流用制御極付半導体素子4の制御極
は、2次巻線n2の一側に、フライホイール用制御極付
半導体素子5の制御極は2次巻線n2の他側に、それぞ
れ接続されている。負荷接続用の出力端子8は、平滑用
コンデンサ8の両端に接続されている。さらに、本実施
例では、整流用制御極付半導体素子4に並列にコンデン
サ11を接続し、スイッチング素子2がオフの時にトラ
ンス3の2次巻線n2に生じるフライバック電圧が、ス
イッチング素子2が次にオンする直前まで、フライバッ
ク用制御極付半導体素子5の制御極の閾値以上になるよ
うにコンデンサ11の静電容量値を設定する。
The connection configuration of each of the above members is as follows. A series circuit of a DC power supply 1 and a switching element 2 is connected to the primary winding n 1 of the transformer 3. On the other hand, in parallel secondary winding n 2 of one side to the (black circles (-) mark side) control flywheel to the series circuit of the smoothing choke coil 6 and a smoothing capacitor 7 Kiwametsuki semiconductor element 5 of the transformer 3 Semiconductor element 5 with control pole for flywheel in connected circuit
Connected one end of the direct, on the other side of the secondary winding n 2, control of the flywheel in the circuit Kiwametsuki semiconductor element 5
Is connected via a semiconductor element 4 with a control electrode for rectification. Here, the control electrode of the rectifying control Kiwametsuki semiconductor element 4, on one side of the secondary winding n 2, the other side of the control electrode 2 winding n 2 of the flywheel control Kiwametsuki semiconductor element 5 , Are connected respectively. The output terminal 8 for connecting a load is connected to both ends of the smoothing capacitor 8. Further, in this embodiment, by connecting a capacitor 11 in parallel to the rectification control Kiwametsuki semiconductor element 4, the switching element 2 is the flyback voltage occurring in the secondary winding n 2 of the transformer 3 during the OFF, the switching element 2 The capacitance value of the capacitor 11 is set so as to be equal to or more than the threshold value of the control electrode of the semiconductor element 5 with the control electrode for flyback until immediately before is turned on.

【0018】図1及び図2において、a,b,cはそれ
ぞれ整流用制御極付半導体素子4の制御極電圧(FET
の場合、ゲート・ドレイン間電圧)、出力端子電流(F
ETの場合、ソースからドレインへ流れる電流)、出力
端子電圧(FETの場合ソース・ドレイン間電圧)であ
り、d,e,fはそれぞれフライホイール用制御極付半
導体素子5の制御極電圧(FETの場合、ゲート・ドレ
イン間電圧)、出力端子電流(FETの場合、ソースか
らドレインへ流れる電流)、出力端子電圧(FETの場
合、ソース・ドレイン間電圧)である。なお、図2中の
時刻t0,t1,t3は、比較を容易にするため、従来例
の動作波形を示した図4中のt0,t1,t3に対応させ
てある。
In FIGS. 1 and 2, a, b, and c denote control electrode voltages (FETs) of the semiconductor element 4 having a rectifying control electrode, respectively.
In the case of, the gate-drain voltage) and the output terminal current (F
In the case of ET, it is a current flowing from the source to the drain), and an output terminal voltage (source-drain voltage in the case of FET), and d, e, and f are control electrode voltages (FETs) of the semiconductor element 5 having a control electrode for flywheel, respectively. In the case of, a gate-drain voltage), an output terminal current (a current flowing from a source to a drain in the case of an FET), and an output terminal voltage (a source-drain voltage in the case of an FET). The times t 0 , t 1 , and t 3 in FIG. 2 correspond to t 0 , t 1 , and t 3 in FIG. 4 showing the operation waveforms of the conventional example for easy comparison.

【0019】以下、上記のように構成した実施例の動作
および作用を説明する。
The operation and operation of the embodiment configured as described above will be described below.

【0020】まず、図1及び図2により上記実施例の回
路動作を説明する。図2中の時刻t0でスイッチング素
子2の制御極に正の電圧が印加されるとスイッチング素
子2がオンし、トランス3の1次巻線n1に直流電源1
の電圧が印加され、2次巻線n2に黒丸印(・印)側が
正の極性の電圧が生じる。これによりトランス3の励磁
インダクタンス(図示せず)が励磁されるとともに、制
御極電圧aが正の極性となって整流用制御極付半導体素
子4がオンし(図2中のa,c参照)、電流は出力端子
8の下側端子から該整流用制御極付半導体素子4、2次
巻線n2、チョークコイル6、出力端子8の上側端子を
通って負荷(図示せず)に流れる(図2中のb参照)。
First, the circuit operation of the above embodiment will be described with reference to FIGS. When a positive voltage is applied to the control pole of the switching element 2 at time t 0 in FIG. 2, the switching element 2 is turned on, and the DC power supply 1 is connected to the primary winding n 1 of the transformer 3.
The voltage of the applied black dot in the secondary winding n 2 (· mark) side is positive polarity voltage occurs. As a result, the exciting inductance (not shown) of the transformer 3 is excited, and the control pole voltage a becomes a positive polarity to turn on the semiconductor element 4 with the rectifying control pole (see a and c in FIG. 2). A current flows from the lower terminal of the output terminal 8 to the load (not shown) through the semiconductor device 4 with the control electrode for rectification, the secondary winding n 2 , the choke coil 6, and the upper terminal of the output terminal 8. (See b in FIG. 2).

【0021】時刻t1でスイッチング素子2の制御極の
電圧を零にするとスイッチング素子2がオフし、トラン
ス3の励磁インダクタンスに蓄えられたエネルギーによ
りトランス3の励磁インダクタンスとスイッチング素子
2の出力容量(FETの場合、ドレイン・ソース間容量
とドレイン・ゲート間容量の和)、整流用制御極付半導
体素子4の出力容量(FETの場合、ドレイン・ソース
間容量とドレイン・ゲート間容量の和)、フライホイー
ル用制御極付半導体素子5の入力容量(FETの場合、
ゲート・ソース間容量とドレイン・ゲート間容量の和)
及びコンデンサ11との間で共振が生じる。これにより
トランス3の1次巻線n1、2次巻線n2の電圧が反転
し、黒丸印(・印)側が負の極性の正弦波状のフライバ
ック電圧が生じる。この電圧で制御極電圧aが負の極性
となって整流用制御極付半導体素子4がオフし(図2中
のa,c参照)、制御極電圧dが正の極性となってフラ
イホイール用制御極付半導体素子5がオンし(図2中の
d,f参照)、チョークコイル6の電流はフライホイー
ル用制御極付半導体素子5を通り、出力端子8に接続さ
れる図略の負荷を通って還流する(図2中のe参照)。
このようにコンデンサ11を付加すると、トランス3の
フライバック電圧の共振周期が長くなる。そこで、フラ
イバック電圧の発生期間(共振周期の約1/2の期間に
相当)が時刻t1から次にスイッチング素子2がオンす
る時刻t3までの期間になるように、かつ、フライバッ
ク電圧の絶対値がフライホイール用制御極付半導体素子
5の制御極の閾値電圧より高くなるようにコンデンサ1
1の静電容量を選ぶと、時刻t1から時刻t3までフライ
ホイール用制御極付半導体素子5がオンし続け、そのオ
ン電圧は低く維持される(図2中のf参照)。
When the voltage at the control pole of the switching element 2 is reduced to zero at time t 1 , the switching element 2 is turned off, and the energy stored in the excitation inductance of the transformer 3 causes the excitation inductance of the transformer 3 and the output capacitance of the switching element 2 ( In the case of an FET, the sum of the drain-source capacity and the drain-gate capacity), the output capacity of the semiconductor element 4 with a rectifying control electrode (in the case of the FET, the sum of the drain-source capacity and the drain-gate capacity), Input capacitance of semiconductor element 5 with control electrode for flywheel (for FET,
Sum of gate-source capacitance and drain-gate capacitance)
And resonance with the capacitor 11. As a result, the voltages of the primary winding n 1 and the secondary winding n 2 of the transformer 3 are inverted, and a sine wave flyback voltage having a negative polarity on the black circle (•) side is generated. With this voltage, the control pole voltage a has a negative polarity and the semiconductor element 4 with a control electrode for rectification is turned off (see a and c in FIG. 2), and the control pole voltage d has a positive polarity and is used for a flywheel. The semiconductor element 5 with the control electrode is turned on (see d and f in FIG. 2), and the current of the choke coil 6 passes through the semiconductor element 5 with the control electrode for flywheel and passes through a load (not shown) connected to the output terminal 8. Reflux through (see e in FIG. 2).
When the capacitor 11 is added in this manner, the resonance period of the flyback voltage of the transformer 3 becomes longer. Therefore, the generation period of the flyback voltage such that the period until time t 3 when turned on next switching element 2 from the time t 1 (corresponding to a period of about half the resonance period), and the flyback voltage Of the control electrode of the flywheel control electrode-equipped semiconductor element 5 so that the absolute value of
When the capacitance of 1 is selected, the semiconductor element 5 with the control electrode for flywheel continues to be turned on from time t 1 to time t 3 , and its ON voltage is kept low (see f in FIG. 2).

【0022】時刻t3でスイッチング素子2がオンする
と、トランス3の2次巻線n2に再び黒丸印(・印)側
が正極性の電圧が誘起して、制御極電圧aが正の極性と
なって整流用制御極付半導体素子4がオンし、制御極電
圧dが負の極性となってフライホイール用制御極付半導
体素子5がオフし、以後、同様の動作を繰り返す。
When the switching element 2 is turned on at time t 3 , a positive polarity voltage is again induced on the secondary winding n 2 of the transformer 3 on the black circle (•) side, so that the control pole voltage a has a positive polarity. As a result, the semiconductor element 4 with a control electrode for rectification is turned on, the control electrode voltage d becomes negative polarity, and the semiconductor element 5 with a control electrode for flywheel is turned off. Thereafter, the same operation is repeated.

【0023】なお、上記実施例におけるコンデンサ11
をフライホイール用制御極付半導体素子5の制御極と出
力端子間に接続しても上記と同様の効果が得られる。
Incidentally, the capacitor 11 in the above embodiment is used.
Is connected between the control electrode and the output terminal of the semiconductor element 5 with the control electrode for flywheel, the same effect as described above can be obtained.

【0024】トランス3の巻線に並列にコンデンサを接
続してもフライバック電圧発生期間を延ばすことができ
るが、スイッチング素子2のスイッチング時にコンデン
サの充放電損が発生する。これに対しコンデンサ11を
整流用制御極付半導体素子4に並列接続すると、コンデ
ンサ11の充放電はフライバック電圧の共振により行わ
れるので損失が発生しない利点がある。
The flyback voltage generation period can be extended by connecting a capacitor in parallel with the winding of the transformer 3, but charge and discharge loss of the capacitor occurs when the switching element 2 is switched. On the other hand, when the capacitor 11 is connected in parallel to the semiconductor element 4 having a control electrode for rectification, the charge and discharge of the capacitor 11 are performed by resonance of the flyback voltage, so that there is an advantage that no loss occurs.

【0025】なお、参考例として、コンデンサ11を付
加するかわりに、トランス3のフライバック電圧発生期
間が時刻t1から次にスイッチング素子2がオンする時
刻t3までの期間になるようにトランス3の励磁インダ
クタンスを選定できれば同様の効果が得られる。
[0025] As a reference example, instead of adding the capacitor 11, the transformer 3 so that the next period until time t 3 when the switching element 2 is turned on flyback voltage generating period of the transformer 3 from time t 1 The same effect can be obtained if the exciting inductance of (1) can be selected.

【0026】コンデンサ11の容量値は、以下に示す式
を用いて設定できる。直流電源1の電圧をE1、スイッ
チング素子2のオン時間をT1、スイッチングの繰り返
し周期をT、トランス3の1次巻線数をN1、2次巻線
数をN2、1次巻線n1から見た励磁インダクタンスをL
m、スイッチング素子2の出力容量値(FETの場合、
ドレイン・ソース間容量とドレイン・ゲート間容量の
和)をC2、整流用制御極付半導体素子4の出力容量値
(FETの場合、ドレイン・ソース間容量とドレイン・
ゲート間容量の和)をC3、フライホイール用制御極付
半導体素子5の入力容量値(FETの場合、ゲート・ソ
ース間容量とドレイン・ゲート間容量の和)をC4、コ
ンデンサ11の容量値をC11とすると、トランス3の2
次巻線n2に誘起するフライバック電圧瞬時値の絶対値
υ(t)は次の式(1)で与えられる。
The capacitance value of the capacitor 11 can be set using the following equation. The voltage of the DC power supply 1 is E 1 , the on-time of the switching element 2 is T 1 , the switching repetition period is T, the number of primary windings of the transformer 3 is N 1 , the number of secondary windings is N 2 , and the primary winding is The excitation inductance viewed from line n 1 is L
m, the output capacitance value of the switching element 2 (for an FET,
The sum of the drain-source capacitance and the drain-gate capacitance is represented by C 2 , and the output capacitance value of the semiconductor element 4 having a rectifying control electrode (for a FET, the drain-source capacitance and the drain-source capacitance).
The sum of the gate-to-gate capacitance) is C 3 , the input capacitance value (the sum of the gate-source capacitance and the drain-gate capacitance in the case of an FET) of the semiconductor element 5 with the control electrode for flywheel is C 4 , and the capacitance of the capacitor 11. a value of the C 11, 2 of the transformer 3
The absolute value υ (t) of the instantaneous flyback voltage value induced in the next winding n 2 is given by the following equation (1).

【0027】[0027]

【数1】 (Equation 1)

【0028】ここで、Here,

【0029】[0029]

【数2】 (Equation 2)

【0030】tは図2の時刻t0からの時間を表す。T represents the time from time t 0 in FIG.

【0031】図2の時刻t3におけるフライバック電圧
の絶対値がフライホイール用制御極付半導体素子5の制
御極閾値電圧Vthより高くなるには、 υ(T)≧Vth (2) を満足する必要がある。(2)式に(1)式を代入する
In order for the absolute value of the flyback voltage at time t 3 in FIG. 2 to become higher than the control pole threshold voltage Vth of the flywheel control pole semiconductor device 5, it is necessary to satisfy the following condition: 満 足 (T) ≧ Vth (2) is there. Substituting equation (1) into equation (2)

【0032】[0032]

【数3】 (Equation 3)

【0033】となる。(3)式を満足するようにコンデ
ンサ11の容量値C11 選定する。時刻t3におけるフ
ライバック電圧の絶対値がフライホイール用制御極付半
導体素子5の制御極閾値電圧Vthより高くなり過ぎる
と、スイッチング素子2の出力容量、整流用制御極付半
導体素子4の入力容量、フライホイール用制御極付半導
体素子5の出力容量、等の充放電損が大きくなるので、
(3)式の左辺の値がフライホイール用制御極付半導体
素子5の制御極閾値電圧Vth付近になるようにコンデ
ンサ11の容量値C11 設定するのが良い。
## EQU1 ## (3) selecting the capacitance value C 1 1 capacitor 11 so as to satisfy the equation. If the absolute value of the flyback voltage at time t 3 becomes too higher than the control pole threshold voltage Vth of the flywheel control pole semiconductor element 5, the output capacitance of the switching element 2 and the input capacitance of the rectification control pole semiconductor element 4. , The charge / discharge loss such as the output capacity of the semiconductor element 5 with the control electrode for the flywheel increases,
(3) of the left side of the value may be set the capacitance value C 1 1 capacitor 11 so that the vicinity of the control electrode the threshold voltage Vth of the control Kiwametsuki semiconductor device 5 for the flywheel.

【0034】例えば、E1=48 V,T1=1.14
μs,T=2.5 μs,N1/N2=4,Lm=100
μH,C2=170 pF,C3=1.2 nF,C4
=6.9 nF,Vth=3 V,とすると、コンデン
サ11の容量値C11は23.5nFとなる。
For example, E 1 = 48 V, T 1 = 1.14
μs, T = 2.5 μs, N 1 / N 2 = 4, Lm = 100
μH, C 2 = 170 pF, C 3 = 1.2 nF, C 4
= 6.9 nF, Vth = 3 V , and when the capacitance value C 11 of the capacitor 11 becomes 23.5NF.

【0035】ここで、本実施例の効果を具体例により従
来例との比較で示すと、次のとおりである。例えば、入
力電圧48V、出力5V10A、変換周波数400kH
zで、図1の本実施例の電力変換装置を動作させたと
き、図3の従来例によるコンデンサ11がない場合の装
置全体の電力損は5.5W、電力変換率は89.4%で
あったが、コンデンサ11として25nFの静電容量値
のコンデンサを付加することにより電力損は4.9Wと
10%減少し、電力変換効率は91.5%と2%上昇す
る。また、トランスのフライバック電圧発生期間をスイ
ッチング素子オフ期間の全期間に延ばすことにより、フ
ライバック電圧のピーク値が低くなる。例えば、本実施
例による上記の電力変換装置では、図3の従来例による
コンデンサ11がない場合にフライバック電圧のピーク
値がトランス2次側で24Vであるが、コンデンサ11
として25nFの静電容量値のコンデンサを付加するこ
とによりピーク値は14Vと40%減少する。このた
め、コンデンサ11がない図3の従来例の場合は制御極
付半導体素子として40V程度の耐圧が必要であるが、
本実施例ではコンデンサ11を付加することにより耐圧
は20V程度でよくなる。これにより、低耐圧でオン電
圧が小さい制御極付半導体素子を用いることができるの
で、整流回路のより一層の低損失化ができる。
Here, the effect of the present embodiment will be described below in comparison with a conventional example by a specific example. For example, input voltage 48V, output 5V10A, conversion frequency 400kHz
When the power converter of the present embodiment in FIG. 1 is operated at z, the power loss of the entire device without the capacitor 11 according to the conventional example in FIG. 3 is 5.5 W, and the power conversion rate is 89.4%. However, by adding a capacitor having a capacitance value of 25 nF as the capacitor 11, the power loss is reduced by 10% to 4.9 W and the power conversion efficiency is increased by 2% to 91.5%. In addition, the peak value of the flyback voltage is reduced by extending the flyback voltage generation period of the transformer to the entire period of the switching element off period. For example, in the above-described power converter according to the present embodiment, the peak value of the flyback voltage is 24 V on the secondary side of the transformer when there is no capacitor 11 according to the conventional example in FIG.
By adding a capacitor having a capacitance value of 25 nF, the peak value is reduced to 14 V by 40%. For this reason, in the case of the conventional example of FIG. 3 without the capacitor 11, a withstand voltage of about 40 V is required as the semiconductor element with the control electrode.
In this embodiment, the addition of the capacitor 11 improves the breakdown voltage to about 20V. Thus, a semiconductor element with a control electrode having a low withstand voltage and a small on-voltage can be used, so that the loss of the rectifier circuit can be further reduced.

【0036】以上説明したように、コンデンサ11の容
値を選定することにより、制御極付半導体素子4,5
のオン電圧は、図2中のc、fに示すようにオン期間全
域で低い値に押えられ、低損失な整流回路が実現され
る。
As described above, by selecting the capacitance value of the capacitor 11, the semiconductor elements 4, 5
Is suppressed to a low value throughout the ON period as shown by c and f in FIG. 2, and a low-loss rectifier circuit is realized.

【0037】なお、本実施例では制御極付半導体素子の
制御極をトランスの2次巻線で直接駆動する整流回路で
説明しているが、トランスに別巻線を設けてそれにより
制御極を駆動する整流回路でも同様の効果が得られる。
また、トランスのフライバック電圧を直流電源1、平滑
用コンデンサ8、別に設けた直流電源、等でクランプし
て、フライバック電圧のピーク値を押さえるようにした
電力変換回路でも同様の効果が得られる。
In this embodiment, the control pole of the semiconductor element with the control pole is described as a rectifier circuit which is directly driven by the secondary winding of the transformer. However, another winding is provided in the transformer to drive the control pole. A similar effect can be obtained even with a rectifier circuit that performs this operation.
A similar effect can be obtained in a power conversion circuit in which the flyback voltage of the transformer is clamped by the DC power supply 1, the smoothing capacitor 8, a separately provided DC power supply, or the like so as to suppress the peak value of the flyback voltage. .

【0038】[0038]

【発明の効果】以上述べたように、本発明によれば、電
力変換装置において、フライホイール用制御極付半導体
素子に並列にコンデンサを付加して、トランスのフライ
バック電圧発生期間をスイッチング素子のオフ期間の全
期間に延ばし、かつ、フライバック電圧の絶対値がフラ
イホイール用制御極付半導体素子制御極の閾値電圧より
高くするようにしたので、フライホイール用制御極付半
導体素子がオンすべき全期間にわたって該フライホイー
ル用制御極付半導体素子の制御極に電圧を印加できる。
これによりフライホイール用制御極付半導体素子のオン
期間の全域にわたってオン電圧を低く押さえることがで
き、低損失な整流回路が構成できる。
As described above, according to the present invention, according to the present invention, in the power conversion device, and pressurized with a capacitor in parallel to the flywheel control Kiwametsuki semiconductor element, the switching element flyback voltage generating period of the transformer And the absolute value of the flyback voltage is set to be higher than the threshold voltage of the control electrode for the flywheel control electrode, so that the flywheel control electrode semiconductor element is turned on. A voltage can be applied to the control pole of the flywheel control pole-equipped semiconductor element over the entire period.
As a result, the ON voltage can be kept low throughout the ON period of the semiconductor element with a control electrode for a flywheel, and a low-loss rectifier circuit can be configured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

【図2】図1に示す実施例の回路の動作波形を示す波形
図である。
FIG. 2 is a waveform chart showing operation waveforms of the circuit of the embodiment shown in FIG.

【図3】整流手段として制御極付半導体素子を用いるよ
うにした電力変換回路の従来例を示す回路図である。
FIG. 3 is a circuit diagram showing a conventional example of a power conversion circuit in which a semiconductor element with a control electrode is used as a rectifier.

【図4】図3に示す従来例の回路の動作波形を示す波形
図である。
FIG. 4 is a waveform chart showing operation waveforms of the circuit of the conventional example shown in FIG.

【符号の説明】[Explanation of symbols]

1…直流電源 2…スイッチング素子 3…トランス 4…整流用制御極付半導体素子 5…フライホイール用制御極付半導体素子 6…平滑用チョークコイル 7…平滑コンデンサ 8…出力端子 9,10…制御極付半導体素子の寄生ダイオード 11…コンデンサ a…整流用制御極付半導体素子4の制御極電圧 b…整流用制御極付半導体素子4の出力端子電流 c…整流用制御極付半導体素子4の出力端子電圧 d…フライホイール用制御極付半導体素子5の制御極電
圧 e…フライホイール用制御極付半導体素子5の出力端子
電流 f…フライホイール用制御極付半導体素子5の出力端子
電圧
DESCRIPTION OF SYMBOLS 1 ... DC power supply 2 ... Switching element 3 ... Transformer 4 ... Rectifier control electrode semiconductor element 5 ... Flywheel control electrode semiconductor element 6 ... Smoothing choke coil 7 ... Smoothing capacitor 8 ... Output terminal 9, 10 ... Control electrode Parasitic diode of attached semiconductor element 11 ... Capacitor a ... Control electrode voltage of rectifying control electrode semiconductor element 4 b ... Output terminal current of rectifying control electrode semiconductor element 4 c ... Output terminal of rectifying control electrode semiconductor element 4 Voltage d: Control pole voltage of semiconductor element 5 with control electrode for flywheel e: Output terminal current of semiconductor element 5 with control pole for flywheel f: Output terminal voltage of semiconductor element 5 with control pole for flywheel

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−175975(JP,A) (58)調査した分野(Int.Cl.7,DB名) H02M 3/28 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-175975 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H02M 3/28

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 直流電源とスイッチング素子の直列回路
をトランスの1次巻線に接続し、チョークコイルと負荷
の直列回路に第1の制御極付半導体素子を並列に接続し
た回路における該制御極付半導体素子の両端のうち一端
を前記トランスの2次巻線の一側に直接接続し、その他
端を第2の制御極付半導体素子を介して前記2次巻線の
他側に接続して成り、前記スイッチング素子を周期的に
オン、オフしたときに生じる前記トランスの2次巻線出
力電圧を、前記第1の制御極付半導体素子のオン時には
第2の制御極付半導体素子がオフ、前者がオフの時には
後者がオンの如く、交互に動作させることにより、整
流、平滑して負荷に電力を供給するようにした電力変換
装置において、 前記第2の制御極付半導体素子と並列にコンデンサを接
続し、前記スイッチング素子がオフの時に該スイッチン
グ素子が次にオンする直前まで前記トランスの2次巻線
に生じるフライバック電圧が前記第1の制御極付半導体
素子の制御極の閾値以上になるように前記コンデンサの
静電容量値を設定したことを特徴とする制御極付半導体
素子を整流回路に用いた電力変換装置。
1. A control circuit in a circuit in which a series circuit of a DC power supply and a switching element is connected to a primary winding of a transformer, and a semiconductor element with a first control pole is connected in parallel to a series circuit of a choke coil and a load. One end of both ends of the attached semiconductor element is directly connected to one side of the secondary winding of the transformer, and the other end is connected to the other side of the secondary winding via a second semiconductor element with a control pole. The secondary winding output voltage of the transformer, which is generated when the switching element is periodically turned on and off, and the second control electrode-equipped semiconductor element is turned off when the first control electrode-equipped semiconductor element is turned on; In the power converter, when the former is off, the latter is turned on, and the latter is alternately operated, so that the power is rectified and smoothed to supply power to the load. Connect When the switching element is turned off, the flyback voltage generated in the secondary winding of the transformer until immediately before the switching element is turned on next becomes equal to or higher than the threshold value of the control pole of the first control poled semiconductor element. A power converter using a semiconductor element with a control electrode for a rectifier circuit, wherein a capacitance value of a capacitor is set.
JP04261129A 1992-09-30 1992-09-30 Power converter using semiconductor element with control pole for rectifier circuit Expired - Lifetime JP3137765B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04261129A JP3137765B2 (en) 1992-09-30 1992-09-30 Power converter using semiconductor element with control pole for rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04261129A JP3137765B2 (en) 1992-09-30 1992-09-30 Power converter using semiconductor element with control pole for rectifier circuit

Publications (2)

Publication Number Publication Date
JPH06113537A JPH06113537A (en) 1994-04-22
JP3137765B2 true JP3137765B2 (en) 2001-02-26

Family

ID=17357502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04261129A Expired - Lifetime JP3137765B2 (en) 1992-09-30 1992-09-30 Power converter using semiconductor element with control pole for rectifier circuit

Country Status (1)

Country Link
JP (1) JP3137765B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3570595B2 (en) * 1996-12-04 2004-09-29 株式会社デンソー Inductive load drive

Also Published As

Publication number Publication date
JPH06113537A (en) 1994-04-22

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