JP3138538B2 - Semiconductor nonvolatile memory element and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a method for reducing leakage current, stabilizing memory characteristics, and improving reliability due to a parasitic tapered gate transistor formed in a bird's beak region. It is about.

[0002]

2. Description of the Related Art The structure of a conventional nonvolatile memory element will be described with reference to the sectional view of FIG. FIG. 6 is a cross-sectional view of the memory transistor in the channel width direction. In the manufacturing process of the nonvolatile memory element, an element isolation step described below is performed to form a memory element region.

A memory element region 10 and a thick field oxide film 6 in a field region surrounding the memory element region 10 are formed on a semiconductor substrate 7 having a first conductivity type by using a selective oxidation method. When this memory element region 10 is formed,
Between the field oxide film 6 having a thick field region and the memory element region 10, a silicon dioxide film having an inclined shape called a bird's beak 15 is formed.

Thereafter, a silicon dioxide film serving as a memory oxide film 2 is formed on the surface of the memory element region 10, a nitride film 3 and a top oxide film 4 are formed on the memory oxide film 2, and a memory gate electrode is formed. 5 is formed. This polycrystalline silicon film is etched using a photoetching technique to form a memory gate electrode 5.

Thereafter, although not shown in FIG. 6, a source region and a drain region of the second conductivity type are formed using the memory gate electrode as a mask to form a nonvolatile memory element.

In the nonvolatile memory element structure obtained by the conventional manufacturing method described with reference to FIG. 6, when a sufficiently high positive voltage is applied to the memory gate electrode, electrons in the conduction band of the silicon crystal are caused by a tunnel phenomenon. It passes through the thin silicon dioxide film of the memory oxide film and is trapped at the interface between the memory oxide film and the nitride film, in the nitride film, and at the interface between the nitride film and the top oxide film. As a result, negative charges are accumulated in the nitride film, and the threshold voltage changes. The memory characteristics are obtained by the change in the threshold voltage of the memory transistor.

[0007]

The memory transistor of the nonvolatile memory element manufactured by the above-mentioned conventional method has the following problems. A parasitic tapered gate transistor is formed in a bird's beak generated at the time of selective oxidation.

As described above, a sufficiently high positive voltage is applied to the memory gate electrode of the memory transistor manufactured by the conventional method, and negative charges are accumulated in the nitride film. In this case, the threshold value of the memory transistor is increased, and an enhancement operation is performed.

In this state, when a voltage is gradually applied to the memory gate electrode, in the element region of the memory transistor,
No current flows because the threshold voltage is high. However, in a parasitic taper gate transistor formed in a bird's beak, a current flows at a low gate applied voltage and becomes a leak current.

FIG. 5 is a graph showing one example. FIG.
In the graph, the horizontal axis shows the gate voltage, and the vertical axis shows the drain current in logarithm.

As shown in FIG. 5, in the relationship between the gate voltage (Vg) and the drain current (Id) of the memory transistor, the drain current flows at a low gate voltage. For this reason, in the memory characteristics, there arises a problem that the write / erase width becomes narrow.

[0012] An object of the present invention is to provide a nonvolatile memory element capable of preventing a write / erase width in a memory characteristic from being reduced by reducing a leakage current due to a parasitic tapered gate transistor. ,
It is an object of the present invention to provide a manufacturing method thereof.

[0013]

In order to achieve the above object, the present invention employs a semiconductor nonvolatile memory element structure described below and a method of manufacturing the same.

According to the structure of the semiconductor nonvolatile memory element of the present invention, the memory insulating film in the channel width direction of the memory transistor includes a memory element region including a memory oxide film, a nitride film, and a top oxide film, and a memory oxide film. It is composed of a high-threshold region including a thick sacrificial oxide film, a nitride film, and a top oxide film.

In the structure of the semiconductor nonvolatile memory element according to the present invention, the thickness of the memory oxide film forming the memory insulating film is smaller in the channel width direction of the memory transistor than the region in contact with the field oxide film.

According to a method of manufacturing a semiconductor nonvolatile memory device of the present invention, a field oxide film is formed in a field region around a device region of a semiconductor substrate of a first conductivity type, and a sacrificial oxide film is formed in a device region. A step of removing a sacrificial oxide film in a memory element region not in contact with a field oxide film by a photoetching technique; a step of sequentially forming a memory oxide film, a nitride film and a top oxide film; Forming a memory oxide film, a nitride film, and a top oxide film, forming a gate electrode material over the entire surface, forming a memory gate electrode by a photo-etching technique, and forming a region aligned with the memory gate electrode. A step of forming a high-concentration impurity layer in the element region, a step of forming an insulating film for multilayer wiring mainly composed of a silicon dioxide film, And a step of forming a contact window in the insulating film for multilayer wiring by etching, and forming a wiring metal.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. First, the structure of a semiconductor nonvolatile memory element according to the present invention will be described with reference to the cross-sectional view of FIG. 1. FIG. 1 is a cross-sectional view of a memory transistor in a channel width direction.

As shown in FIG. 1, a memory insulating film provided below a memory electrode 5 of a memory transistor includes a memory element region 10 composed of a memory oxide film 2, a nitride film 3, and a top oxide film 4, and a memory oxide film. The structure includes a high threshold region 11 composed of a sacrificial oxide film 1 which is an oxide film thicker than the film 2, a nitride film 3 and a top oxide film 4.

Next, a description will be given of a manufacturing method for forming the structure of the semiconductor nonvolatile memory element of the present invention described with reference to FIG. 2 and 3 are cross-sectional views in the channel width direction of a memory transistor showing a manufacturing method for manufacturing a structure of a nonvolatile memory element according to the present invention in the order of steps.

First, as shown in FIG. 2, a memory element region 10 and a high threshold region 1 of a P-type semiconductor substrate 7 are formed.
1, a field oxide film 6 having a thickness of 700 nm is formed by a so-called selective oxidation process of oxidizing using an oxidation resistant film such as a silicon nitride film as a mask. After that, the oxidation resistant film is removed.

Next, an oxidizing process is performed in a mixed gas of oxygen and nitrogen to form a sacrificial oxide film 1 made of silicon dioxide having a thickness of about 50 nm on the entire surface.

Next, a resist 13 which is a photosensitive material is formed on the entire surface.
Is formed by a spin coating method, and is exposed and developed using a predetermined photomask to form an opening in the resist 13 in the memory element region 10.

Thereafter, using the resist 13 as a mask, the sacrificial oxide film 1 in the memory element region 10 is removed by etching the sacrificial oxide film 1 using a hydrofluoric acid buffer. afterwards,
The resist 13 used as an etching mask is removed.

Next, as shown in FIG. 3, an oxidation process is performed in a mixed gas of oxygen and nitrogen, and a memory oxide film 2 made of a silicon dioxide film having a thickness of about 2 nm is formed in the opening of the sacrificial oxide film 1. Is formed in the memory element region 10 in the inside.

Next, a nitride film 3 made of a silicon nitride film is formed on the entire surface including the memory oxide film 2 by a chemical vapor deposition method (hereinafter, referred to as a CVD method) to a thickness of about 9 nm.

Further, an oxidation treatment is performed in an oxidizing atmosphere to oxidize the nitride film 3 to form a top oxide film 4 made of a silicon dioxide film on the nitride film 3.

The memory oxide film 2, the nitride film 3, and the top oxide film 4 constitute a memory insulating film of a memory transistor.

Thereafter, a polycrystalline silicon film to be the memory gate electrode 5 is formed on the entire surface by the CVD method.

Next, a resist 13 is formed on the entire surface, exposed and developed using a predetermined photomask, and a resist 13 is formed on the memory element region 10 for forming the memory gate electrode 5 and the high threshold region 11. 13 is formed.

Thereafter, using the resist 13 as an etching mask, the polycrystalline silicon film to be the memory gate electrode 5 is etched by dry etching using a mixed gas of sulfur hexafluoride and oxygen as an etching gas.

Next, the top oxide film 4 is etched with a hydrofluoric acid buffer solution, and the nitride film 3 is further etched by dry etching using a mixed gas of sulfur hexafluoride and oxygen as an etching gas.

Thus, a memory insulating film including the memory oxide film 2, the nitride film 3, and the top oxide film 4 is formed in the memory element region 10. Further, in the high threshold region 11, a memory insulating film including the sacrificial oxide film 1, the nitride film 3, and the top oxide film 4 is formed.

Next, although not shown in FIG. 3, an N-type impurity having a conductivity type opposite to that of the semiconductor substrate 7 is obtained by using the memory gate electrode 5 made of a polycrystalline silicon film as an impurity blocking film for ion implantation. Phosphorus, acceleration energy 50k
eV, ion implantation amount 4.0 × 10 ¹⁵ atoms / cm ²
The source region and the drain region, which are high-concentration impurity layers of the second conductivity type, are formed by performing ion implantation under the ion implantation conditions of the order.

Thereafter, although not shown, a multi-layer wiring insulating film mainly composed of a silicon dioxide film is formed by a general method, and a contact window is formed in the multi-layer wiring insulating film using a photo-etching technique. A nonvolatile memory element is obtained by forming aluminum as a wiring metal.

[0035]

As apparent from the above description, in the semiconductor nonvolatile memory element of the present invention, the bird's beak region in which the parasitic tapered gate transistor is formed is composed of the sacrificial oxide film, the nitride film, and the top oxide film. This is a high threshold region, which is sufficiently higher than the threshold voltage of the memory element region.

Therefore, even when a high voltage is applied to the memory gate electrode and writing and erasing of the memory transistor are performed, the threshold voltage of the memory transistor is determined by the memory element region, and the conventional leak current caused by the parasitic taper gate transistor is small. Can be suppressed.

One example is shown in the graph of FIG. 4 showing the gate voltage and drain current characteristics of the memory transistor. As shown in FIG. 4, in the relationship between the gate voltage and the drain current of the nonvolatile memory element, it is possible to suppress the leak current in which the drain current flows at a low gate voltage as shown in FIG.

As described above, by suppressing the leak current, in the memory characteristics, when a positive potential is applied to the memory gate electrode, an enhancement operation is performed, and the write width increases. Therefore, the time for applying the positive potential to the memory gate electrode is reduced as compared with the conventional case. As described above, according to the present structure and the manufacturing method thereof, the memory characteristics can be improved.

As a result, a highly reliable nonvolatile memory element can be formed, and a nonvolatile memory element having stable characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 4 is a graph showing characteristics of a gate voltage and a drain current of a memory transistor manufactured according to the present invention.

FIG. 5 is a graph showing characteristics of a gate voltage and a drain current of a memory transistor prepared by a conventional method.

FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor nonvolatile memory element.

[Explanation of symbols]

 Reference Signs List 1 sacrificial oxide film 2 memory oxide film 3 nitride film 4 top oxide film 5 memory gate electrode 6 field oxide film 7 semiconductor substrate 10 memory element region 11 high threshold region 15 bird's beak

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] A memory insulating film in a channel width direction of a memory transistor constituting a semiconductor nonvolatile memory element has a memory element region including a memory oxide film, a nitride film, and a top oxide film, and has a thickness greater than that of the memory oxide film. And a high threshold region including a thick sacrificial oxide film, a nitride film, and a top oxide film. 2. The non-volatile semiconductor memory device according to claim 1, wherein the thickness of the memory oxide film forming the memory insulating film in the channel width direction of the memory transistor is smaller than a region in contact with the field oxide film. . 3. A field oxide film is formed in a field region around a memory element region and a high threshold region of a semiconductor substrate of a first conductivity type, and a sacrificial oxide film is formed in the memory element region and the high threshold region. And removing the sacrificial oxide film in the memory element region separated from the field oxide film by photo-etching technology , and sequentially forming the memory oxide film, the nitride film, and the top oxide film.
Forming, forming a memory gate electrode material over the entire surface, and etching the memory gate electrode material by photoetching technology.
To form a memory gate electrode,
A step of sequentially etching the nitride film, a step of forming a high-concentration impurity layer in an element region in a region aligned with the memory gate electrode, and a step of forming an insulating film for multilayer wiring mainly composed of a silicon dioxide film. A method for manufacturing a semiconductor nonvolatile memory element, comprising: a step of forming a contact window in an insulating film for multilayer wiring by a photoetching technique; and a step of forming a wiring metal.